added txt guide to configurable Bochs CPU model
This commit is contained in:
Stanislav Shwartsman
parent
7bbfee58a2
commit
0c32889d24
504
bochs/docs-html/cpu_configurability.txt
Executable file
504
bochs/docs-html/cpu_configurability.txt
Executable file
@ -0,0 +1,504 @@
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Bochs CPU configurability - go over all CPUID feature extensions and see how and where it affects Bochs configurable CPU engine
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1. ISA Feature: X87 (FPU on chip)
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The FPU can be present on chip before CPUID as well, for example in 80386.
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Enables CPUID[0x00000001].EDX[0] and x87 instructions.
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Without X87 FPU instruction will execute stub FPU_ESC.
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Controlled by BX_SUPPORT_X87 configure option only, cannot be toggled in runtime.
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2. CPU Feature: VME (Virtual-8086 Mode enhancements)
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First introduced in Pentium.
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Enables CPUID[0x00000001].EDX[1] flag.
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Controls ability to set CR4[0] (VME) and CR4[1] (PVE) bits.
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The CR4 controls enable Virtual-8086 Mode enhancements functionality.
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Dependency: BX_CPU_LEVEL >= 4 for CR4 support.
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3. CPU Feature: Debug Extensions (I/O breakpoints)
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Enables CPUID[0x00000001].EDX[2] flag.
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Controls ability to set CR4[3] (Debug Extensions) bit.
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The bit controls DR4/DR5 (DR4/DR5 are aliased to DR6/DR7 without CR4.DE set) and enables I/O breakpoints.
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Dependency: BX_CPU_LEVEL >= 4 for CR4 support.
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4. CPU Feature: Page Size Extensions
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Enables CPUID[0x00000001].EDX[3] flag.
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Controls ability to set CR4[4] (PSE) bit.
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The bit is checked during page walk in order to enable 4MB pages through PDE.PS bit.
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The PDE.PS bit is ignored if CR4.PSE is clear
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Dependency: BX_CPU_LEVEL >= 4 for CR4 support.
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5. CPU Feature: Time Stamp Counter
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First introduced in Pentium.
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Enables CPUID[0x00000001].EDX[4] flag.
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Controls ability to set CR4[2] (TSD) bit.
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Enables RDTSC instruction (the instruction will #UD if the Time Stamp Counter is not supported).
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Enables MSR 0x010 IA_MSR_TSC.
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Dependency: MSR
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6. ISA Feature: MSR
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First introduced in Pentium.
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Enables CPUID[0x00000001].EDX[5] flag.
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Enables RDMSR/WRMSR instructions (the instructions will #UD if the MSR is not supported).
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Enables access to Model Specific MSR registers.
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7. CPU Feature: Physical Address Extensions
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Enables CPUID[0x00000001].EDX[6] flag.
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Controls ability to set CR4[5] (PAE) bit.
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The bit is checked during page walk in order to enable PAE paging mode.
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Dependency: BX_CPU_LEVEL >= 4 for CR4 support.
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8. CPU Feature: Machine Check
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Enables CPUID[0x00000001].EDX[7] (Machine Check Exception) flag.
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Enables CPUID[0x00000001].EDX[14] (Machine Check Architecture) flag.
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Controls ability to set CR4[6] (MCE) bit.
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Enables Machine Check MSR registers and ability to trigger machine check exception.
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Note, that Bochs can never trigger the machine check exception.
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Dependency: MSR
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9. ISA Feature: CMPXCHG8B instruction
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First introduced in Pentium.
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Enables CPUID[0x00000001].EDX[8] flag.
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Enables CMPXCHG8B instruction (the instruction will #UD otherwise).
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10. CPU Feature: APIC on chip
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Enables MSR_APIC_BASE register.
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Enables CPUID[0x00000001].EDX[9] (Apic on Chip) flag. The CPUID bit is read from MSR_APIC_BASE[11] (Global Enable Bit).
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Enables CPUID[0x00000001].EBX[31:24] (Local Apic ID) reporting.
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Enables Local APIC functionality.
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Without Local APIC the system behaves as Local APIC is globally disabled.
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Dependency: MSR
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11. ISA Feature: SYSENTER/SYSEXIT support
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First introduced in P6.
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Enables CPUID[0x00000001].EDX[11] flag.
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Enables IA_SYSENTER_CS_MSR, IA_SYSENTER_ESP_MSR, IA_SYSENTER_EIP_MSR.
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Enables SYSENTER/SYSEXIT instructions (will #UD otherwise)
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Dependency: MSR
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12. CPU Feature: MTRR
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Enables CPUID[0x00000001].EDX[12] flag.
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Enables MTRR MSR registers.
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Enables Memory Type (not yet implemented).
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Dependency: MSR
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13. CPU Feature: Global Pages
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Enables CPUID[0x00000001].EDX[13] flag. Controls ability to set CR4[7] (PGE) bit.
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Enables PTE Global bit during page walk and global pages support.
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Dependency: BX_CPU_LEVEL >= 4 for CR4 support.
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14. ISA Feature: CMOV
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First introduced in P6.
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Enables CPUID[0x00000001].EDX[15] flag.
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Enables CMOV/FCMOV instructions (will #UD otherwise).
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15. CPU Feature: PAT
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Enables CPUID[0x00000001].EDX[16] flag.
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Enables PAT MSR register.
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Enables PAT bit in page tables.
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Extends Memory Type calculation algorithm (not yet implemented).
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Dependency: MSR
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16. CPU Feature: PSE-36
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Enables CPUID[0x00000001].EDX[17] flag.
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Enables generation of > 32 bit physical address during regular non-PAE page walk.
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Current can't be turned on/off on runtime, controlled using BX_PHY_ADDRESS_LONG configure variable.
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Dependency: Indicates > 32bit physical address support.
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17. CPU Feature: PSN (Processor Serial Number)
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Enables CPUID[0x00000001].EDX[18] flag.
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Enables CPUID leaf 0x00000003 (Processor Serial Number).
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Not implemented in Bochs.
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18. ISA Feature: CLFLUSH
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Enables CPUID[0x00000001].EDX[19] flag.
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Enables CPUID[0x00000001].EBX[15:08] (CLFLUSH cache line size) reporting.
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Enables CLFLUSH instruction (will #UD otherwise).
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19. CPU Feature: Debug Store
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???
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Enables CPUID[0x00000001].EDX[21] flag.
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Not implemented in Bochs.
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20. CPU Feature: ACPI: Thermal Monitor and Software Controlled Clock Facilities
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???
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Enables CPUID[0x00000001].EDX[22] flag.
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Not implemented in Bochs.
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21. ISA Feature: MMX
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First introduced in Pentium.
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Enables CPUID[0x00000001].EDX[23] flag.
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Enables MMX instructions (will #UD otherwise).
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Dependency: X87 (sharing the same registers)
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22. ISA Feature: FXSAVE/FXRSTOR
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First introduced in P6 (together with SSE?).
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Enables CPUID[0x00000001].EDX[24] flag.
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Controls ability to set CR4[9] (OSFXSR) bit.
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Enables FXSAVE/FXRSTOR instructions (will #UD otherwise).
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23. ISA Feature: SSE
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Enables CPUID[0x00000001].EDX[25] flag.
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Controls ability to set CR4[10] (OSXMMEXCPT) bit.
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Enables SSE decoding scheme (0x66, 0xF2 and 0xF3 prefixes as opcode extension).
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Enables MXCSR and SSE registers.
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Enables SSE instructions (will #UD otherwise) and new #XF exception.
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Dependency: FXSAVE/FXRSTOR
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24. ISA Feature: SSE2
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Enables CPUID[0x00000001].EDX[26] flag.
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Enables MXCSR.DAZ bit support.
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Enables SSE2 instructions (will #UD otherwise).
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Dependency: SSE
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25. CPU Feature: Self snoop
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Uarch only, not emulation visible.
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Enables CPUID[0x00000001].EDX[27] flag.
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26. CPU Feature: Hyper Threading Technology
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Enables CPUID[0x00000001].EDX[28] flag.
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Enables CPUID[0x00000001].EBX[23:16] (Number of logical processors in one physical processor) reporting.
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Indicates that CPU supports hyper-threading technology (not emulation visible).
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27. CPU Feature: Thermal Monitor
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???
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Enables CPUID[0x00000001].EDX[29] flag.
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Not implemented in Bochs.
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28. CPU Feature: PBE (Pending Break Enable)
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???
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Enables CPUID[0x00000001].EDX[31] flag.
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Not implemented in Bochs.
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29. ISA Feature: SSE3
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Enables CPUID[0x00000001].ECX[0] flag.
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Enables SSE3 instructions (will #UD otherwise).
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Dependency: SSE
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30. ISA Feature: AES and PCLMULQDQ instruction
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Enables CPUID[0x00000001].ECX[1] flag (PCLMULQDQ).
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Enables CPUID[0x00000001].ECX[25] flag (AES).
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Enables PCLMULQDQ instruction (will #UD otherwise).
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Enables AES instruction (will #UD otherwise).
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Dependency: SSSE3 (3-byte opcode)
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31. CPU Feature: DTES64 (64-bit DS area)
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???
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Enables CPUID[0x00000001].ECX[2] flag.
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Not implemented in Bochs.
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32. ISA Feature: MONITOR/MWAIT
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Enables CPUID[0x00000001].ECX[3] flag.
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Enables CPUID[0x00000005] leaf (MONITOR/MWAIT).
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Enables MONITOR/MWAIT instructions (will #UD otherwise).
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Enables power management sleep states (can enter to sleep state with MWAIT).
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33. CPU Feature: DS-CPL (CPL qualified debug store)
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???
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Enables CPUID[0x00000001].ECX[4] flag.
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Not implemented in Bochs.
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34. ISA Feature: VMX
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Enables CPUID[0x00000001].ECX[5] flag.
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Controls ability to set CR4[13] (VMXE) bit.
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Enables VMX MSR registers.
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Enables VMX instructions (will #UD otherwise).
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VMX mode can be enabled only using VMX instructions.
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35. ISA Feature: SMX
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Enables CPUID[0x00000001].ECX[6] flag.
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Controls ability to set CR4[14] (SMXE) bit.
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Enables SMX instruction GETSEC (will #UD otherwise).
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SMX mode can be enabled only using SMX instruction.
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36. CPU Feature: EST (Enhanced Intel SpeedStep Technology)
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???
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Enables CPUID[0x00000001].ECX[7] flag.
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Not implemented in Bochs.
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37. CPU Feature: TM2 (Thermal Monitor 2)
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???
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Enables CPUID[0x00000001].ECX[8] flag.
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Not implemented in Bochs.
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38. ISA Feature: SSSE3
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Enables CPUID[0x00000001].ECX[9] flag.
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Enables SSSE3 instructions (will #UD otherwise).
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Enables 3-byte opcode decoding.
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Dependency: SSE
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39. CPU Feature: CNXT-ID: L1 context ID
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???
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Enables CPUID[0x00000001].ECX[10] flag.
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Not implemented in Bochs.
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30. ISA Feature: FMA
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Enables CPUID[0x00000001].ECX[12] flag.
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Enables Intel 3-src FMA instructions (will #UD otherwise).
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Dependency: AVX (VEX encoded)
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31. ISA Feature: CMPXCHG16B
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Enables CPUID[0x00000001].ECX[13] flag.
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Enables CMPXCHG16B instruction (will #UD otherwise).
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Dependency: Long Mode
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32. CPU Feature: xTPR update control
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???
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Enables CPUID[0x00000001].ECX[14] flag.
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Not implemented in Bochs.
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33. CPU Feature: PDCM (Perfon and Debug Capability MSR)
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???
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Enables CPUID[0x00000001].ECX[15] flag.
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Not implemented in Bochs.
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34. CPU Feature: PCID
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Enables CPUID[0x00000001].ECX[17] flag.
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Controls ability to set CR4[17] (PCID) bit.
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PCID functionality is enabled under CR4.PCID set.
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Selective TLB flush on PCID switch is not implemented in Bochs (always flush whole TLB).
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35. CPU Feature: DCA (Direct Cache Access)
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???
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Enables CPUID[0x00000001].ECX[18] flag.
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Not implemented in Bochs.
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36. ISA Feature: SSE4.1
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Enables CPUID[0x00000001].ECX[19] flag.
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Enables SSE4.1 instructions (will #UD otherwise).
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Dependency: SSSE3 (3-byte opcodes)
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37. ISA Feature: SSE4.2
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Enables CPUID[0x00000001].ECX[20] flag.
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Enables SSE4.2 instructions (will #UD otherwise).
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Dependency: SSSE3 (3-byte opcodes)
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38. CPU Feature: X2APIC
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Enables CPUID[0x00000001].ECX[21] flag.
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Enables X2APIC MSR registers.
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Enables X2APIC mode in the Local APIC.
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39. ISA Feature: MOVBE
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Enables CPUID[0x00000001].ECX[22] flag.
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Enables MOVBE instruction (will #UD otherwise).
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Dependency: SSSE3 (3-byte opcodes)
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40. ISA Feature: POPCNT
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Enables CPUID[0x00000001].ECX[23] flag.
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Enables POPCNT instruction (will #UD otherwise).
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Dependency: SSE (encoded with SSE prefixes)
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41. CPU Feature: TSC Deadline
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???
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Enables CPUID[0x00000001].ECX[24] flag.
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Not implemented in Bochs.
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42. ISA Feature: XSAVE
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Enables CPUID[0x00000001].ECX[26] flag.
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Enables CPUID[0x00000001].ECX[27] flag (copy from CR4.OSXSAVE bit).
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Controls ability to set CR4[18] (OSXSAVE) bit.
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Enables CPUID[0x0000000D] leaf (MONITOR/MWAIT).
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Enables XCR0 register.
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Enables XSETBW/XGETBV/XSAVE/XRSTOR instructions (will #UD otherwise).
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43. ISA Feature: AVX
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Enables CPUID[0x00000001].ECX[28] flag.
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Enables XCR0[2] (AVX) bit.
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Enables CPUID[0x0000000D][2] subleaf leaf.
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Enables AVX registers.
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Enables VEX prefix decoding and AVX instructions (will #UD otherwise).
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Dependency: XSAVE
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44. ISA Feature: AVX_F16C
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Enables CPUID[0x00000001].ECX[29] flag.
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Enables VCVTPH2PS/VCVTPS2PH instructions (will #UD otherwise).
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Dependency: AVX (VEX encoded)
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45. ISA Feature: RDRAND
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Enables CPUID[0x00000001].ECX[30] flag.
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Enables RDRAND instructions (will #UD otherwise).
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Not implemented in Bochs.
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46. ISA Feature: FS_GS_BASE
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Enables CPUID[0x00000007].EBX[0] flag.
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Controls ability to set CR4[16] (FSGSBASE) bit.
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Enables FS/GS BASE access instructions (will #UD otherwise).
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Dependency: Long Mode only
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47. CPU Feature: SMEP
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Enables CPUID[0x00000007].EBX[7] flag.
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Controls ability to set CR4[20] (SMEP) bit.
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Enables Supervisor Mode Execution Protection during PAE mode page walk.
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Enables FS/GS BASE access instructions (will #UD otherwise).
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Dependency: PAE
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48. ISA Feature: SYSCALL/SYSRET
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Enables CPUID[0x80000001].EDX[11] flag.
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Controls ability to set EFER.SCE bit.
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Enables MSR_STAR, MSR_LSTAR, MSR_CSTAR registers.
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Enables SYSCALL/SYSRET instructions (will #UD otherwise).
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On Intel SYSCALL/SYSRET supported in long mode only, AMD allow protected mode as well.
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Bochs follow AMD implementation.
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Dependency: Long Mode, MSR
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49. CPU Feature: NX
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Enables CPUID[0x80000001].EDX[20] flag.
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Controls ability to set EFER.NX bit.
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Enables Non-execute protection during PAE mode page walk.
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Dependency: PAE
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50. ISA Feature: AMD MMX Extensions
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???
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Enables CPUID[0x80000001].EDX[22] flag.
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Not implemented in Bochs.
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51. CPU Feature: FFXSR
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Enables CPUID[0x80000001].EDX[25] flag.
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Controls ability to set EFER.FFXSR bit.
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Enables Fast FXSAVE/FXRSTOR functionality under long mode.
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Dependency: Long Mode
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52. CPU Feature: 1G pages
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Enables CPUID[0x80000001].EDX[26] flag.
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Enables PDPE.PS bit and 1G paging support during long mode page walk.
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Dependency: Long Mode
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53. ISA Feature: RDTSCP
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Enables CPUID[0x80000001].EDX[27] flag.
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Enables MSR_TSC_AUX register.
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Enables RDTSCP instruction (will #UD otherwise).
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Dependency: TSC
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54. ISA Feature: Long Mode
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Enables CPUID[0x80000001].EDX[29] flag.
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Controls setting of EFER.LMA (Long Mode Active) and EFER.LME (Long Mode Enabled) bits.
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Enables Long Mode with new registers, new instructions and new decoding scheme.
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Enables long mode MSR registers.
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Enables 48-bt linear addressing and CPUID[0x80000008].EAX (maximum linear and physical address width)
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55. ISA Feature: 3DNow! Ext
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Enables CPUID[0x80000001].EDX[30] flag.
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Enables 3DNow! EXT instructions (will #UD otherwise).
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Dependency: 3DNOW
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56. ISA Feature: 3DNow!
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Enables CPUID[0x80000001].EDX[31] flag.
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Enables 3DNow! instructions (will #UD otherwise).
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||||
Dependency: MMX
|
||||
|
||||
57. ISA Feature: Long Mode LAHF/SAHF support
|
||||
|
||||
Enables CPUID[0x80000001].ECX[0] flag.
|
||||
Enables LAHF/SAHF instructions in long mode (will #UD otherwise).
|
||||
|
||||
58. CPU Feature: Misaligned SSE
|
||||
|
||||
Enables CPUID[0x80000001].ECX[7] flag.
|
||||
Controls setting of MXCSR.MM bit.
|
||||
Enables misaligned SSE memory accesses without #GP fault.
|
||||
|
||||
Dependency: SSE
|
||||
|
||||
59. ISA Feature: PrefetchW
|
||||
|
||||
Enables CPUID[0x80000001].ECX[8] flag.
|
||||
Set if PREFETCHW implemented as real HW prefetch.
|
||||
Loading…
Reference in New Issue
Block a user