Performance mod: I implemented a suggestion from Peter Tattam
and Jas Sandys-Lumsdaine to split out common instructions into variants which deal with the mod=11b case (Reg-Reg) and the other cases (which do memory ops). Actually, I only split MOV_GwEw and MOV_GdEd for now. According to some instrumentation of a Win95 boot, they were the most frequently used opcode by far.
This commit is contained in:
Kevin Lawton
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.85 2002-09-28 00:54:04 kevinlawton Exp $
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// $Id: cpu.h,v 1.86 2002-09-28 05:38:11 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1649,8 +1649,15 @@ union {
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BX_SMF void MOV_EdGd(bxInstruction_c *);
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BX_SMF void MOV_EwGw(bxInstruction_c *);
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BX_SMF void MOV_GbEb(bxInstruction_c *);
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BX_SMF void MOV_GdEd(bxInstruction_c *);
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BX_SMF void MOV_GdEGd(bxInstruction_c *);
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BX_SMF void MOV_GdEEd(bxInstruction_c *);
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BX_SMF void MOV_GwEw(bxInstruction_c *);
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BX_SMF void MOV_GwEGw(bxInstruction_c *);
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BX_SMF void MOV_GwEEw(bxInstruction_c *);
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BX_SMF void MOV_EwSw(bxInstruction_c *);
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BX_SMF void LEA_GdM(bxInstruction_c *);
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BX_SMF void LEA_GwM(bxInstruction_c *);
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@ -2956,6 +2963,7 @@ IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
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#define BxPrefix 0x0010 // bit 4
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#define BxAnother 0x0020 // bit 5
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#define SplitMod11b 0x0040 // bit 6
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#define BxRepeatable 0x0800 // bit 11 (pass through to metaInfo field)
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#define BxRepeatableZF 0x1000 // bit 12 (pass through to metaInfo field)
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#define BxGroupN 0x0100 // bits 8
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: data_xfer16.cc,v 1.15 2002-09-22 18:22:24 kevinlawton Exp $
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// $Id: data_xfer16.cc,v 1.16 2002-09-28 05:38:11 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -71,19 +71,23 @@ BX_CPU_C::MOV_EwGw(bxInstruction_c *i)
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void
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BX_CPU_C::MOV_GwEw(bxInstruction_c *i)
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BX_CPU_C::MOV_GwEGw(bxInstruction_c *i)
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{
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Bit16u op2_16;
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// 2nd modRM operand Ex, is known to be a general register Gw.
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Bit16u op2_16;
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if (i->modC0()) {
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op2_16 = BX_READ_16BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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}
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op2_16 = BX_READ_16BIT_REG(i->rm());
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BX_WRITE_16BIT_REG(i->nnn(), op2_16);
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}
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BX_WRITE_16BIT_REG(i->nnn(), op2_16);
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void
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BX_CPU_C::MOV_GwEEw(bxInstruction_c *i)
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{
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// 2nd modRM operand Ex, is known to be a memory operand, Ew.
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Bit16u op2_16;
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read_virtual_word(i->seg(), RMAddr(i), &op2_16);
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BX_WRITE_16BIT_REG(i->nnn(), op2_16);
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}
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void
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: data_xfer32.cc,v 1.16 2002-09-22 18:22:24 kevinlawton Exp $
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// $Id: data_xfer32.cc,v 1.17 2002-09-28 05:38:11 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -80,21 +80,24 @@ BX_CPU_C::MOV_EdGd(bxInstruction_c *i)
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void
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BX_CPU_C::MOV_GdEd(bxInstruction_c *i)
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BX_CPU_C::MOV_GdEGd(bxInstruction_c *i)
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{
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Bit32u op2_32;
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// 2nd modRM operand Ex, is known to be a general register Gd.
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Bit32u op2_32;
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if (i->modC0()) {
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op2_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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}
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BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
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op2_32 = BX_READ_32BIT_REG(i->rm());
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BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
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}
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void
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BX_CPU_C::MOV_GdEEd(bxInstruction_c *i)
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{
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// 2nd modRM operand Ex, is known to be a memory operand, Ed.
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Bit32u op2_32;
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read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
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BX_WRITE_32BIT_REGZ(i->nnn(), op2_32);
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}
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void
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BX_CPU_C::LEA_GdM(bxInstruction_c *i)
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.23 2002-09-28 00:54:04 kevinlawton Exp $
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// $Id: fetchdecode.cc,v 1.24 2002-09-28 05:38:11 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -344,6 +344,16 @@ static BxOpcodeInfo_t BxOpcodeInfoG9[8] = {
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/* 7 */ { 0, &BX_CPU_C::BxError }
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};
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static BxOpcodeInfo_t opcodesMOV_GwEw[2] = {
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{ 0, &BX_CPU_C::MOV_GwEEw },
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{ 0, &BX_CPU_C::MOV_GwEGw }
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};
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static BxOpcodeInfo_t opcodesMOV_GdEd[2] = {
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{ 0, &BX_CPU_C::MOV_GdEEd },
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{ 0, &BX_CPU_C::MOV_GdEGd }
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};
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#if BX_SUPPORT_MMX
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static BxOpcodeInfo_t BxOpcodeInfoGAw[8] = { /* MMX */
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/* 0 */ { 0, &BX_CPU_C::BxError },
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@ -523,7 +533,7 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 88 */ { BxAnother, &BX_CPU_C::MOV_EbGb },
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/* 89 */ { BxAnother, &BX_CPU_C::MOV_EwGw },
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/* 8A */ { BxAnother, &BX_CPU_C::MOV_GbEb },
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/* 8B */ { BxAnother, &BX_CPU_C::MOV_GwEw },
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/* 8B */ { BxAnother | SplitMod11b, (BxExecutePtr_t)opcodesMOV_GwEw },
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/* 8C */ { BxAnother, &BX_CPU_C::MOV_EwSw },
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/* 8D */ { BxAnother, &BX_CPU_C::LEA_GwM },
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/* 8E */ { BxAnother, &BX_CPU_C::MOV_SwEw },
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@ -1052,7 +1062,7 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
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/* 88 */ { BxAnother, &BX_CPU_C::MOV_EbGb },
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/* 89 */ { BxAnother, &BX_CPU_C::MOV_EdGd },
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/* 8A */ { BxAnother, &BX_CPU_C::MOV_GbEb },
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/* 8B */ { BxAnother, &BX_CPU_C::MOV_GdEd },
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/* 8B */ { BxAnother | SplitMod11b, (BxExecutePtr_t)opcodesMOV_GdEd },
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/* 8C */ { BxAnother, &BX_CPU_C::MOV_EwSw },
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/* 8D */ { BxAnother, &BX_CPU_C::LEA_GdM },
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/* 8E */ { BxAnother, &BX_CPU_C::MOV_SwEw },
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@ -1847,6 +1857,14 @@ modrm_done:
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instruction->DTAttr = BxDTOpcodeInfo[b1+offset].DTAttr;
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instruction->DTFPtr = BxDTOpcodeInfo[b1+offset].DTASFPtr;
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#endif
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// For high frequency opcodes, two variants of the instruction are
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// implemented; one for the mod=11b case (Reg-Reg), and one for
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// the other cases (Reg-Mem).
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if (attr & SplitMod11b) {
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BxOpcodeInfo_t *OpcodeInfoPtr;
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OpcodeInfoPtr = (BxOpcodeInfo_t *) instruction->execute;
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instruction->execute = OpcodeInfoPtr[mod==0xc0].ExecutePtr;
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}
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}
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}
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