diff --git a/bochs/cpu/arith16.cc b/bochs/cpu/arith16.cc index 6bd5afd2a..fd0e418f9 100644 --- a/bochs/cpu/arith16.cc +++ b/bochs/cpu/arith16.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: arith16.cc,v 1.9 2002-09-13 22:31:02 kevinlawton Exp $ +// $Id: arith16.cc,v 1.10 2002-09-17 22:50:51 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -34,44 +34,46 @@ void -BX_CPU_C::INC_RX(BxInstruction_t *i) +BX_CPU_C::INC_RX(bxInstruction_c *i) { Bit16u rx; -#if BX_SUPPORT_X86_64 - rx = ++ BX_CPU_THIS_PTR gen_reg[i->nnn].word.rx; -#else - rx = ++ BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx; -#endif + rx = ++ BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].word.rx; +//#if BX_SUPPORT_X86_64 +// rx = ++ BX_CPU_THIS_PTR gen_reg[i->nnn()].word.rx; +//#else +// rx = ++ BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx; +//#endif SET_FLAGS_OSZAP_16(0, 0, rx, BX_INSTR_INC16); } void -BX_CPU_C::DEC_RX(BxInstruction_t *i) +BX_CPU_C::DEC_RX(bxInstruction_c *i) { Bit16u rx; -#if BX_SUPPORT_X86_64 - rx = -- BX_CPU_THIS_PTR gen_reg[i->nnn].word.rx; -#else - rx = -- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx; -#endif + rx = -- BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].word.rx; +//#if BX_SUPPORT_X86_64 +// rx = -- BX_CPU_THIS_PTR gen_reg[i->nnn()].word.rx; +//#else +// rx = -- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx; +//#endif SET_FLAGS_OSZAP_16(0, 0, rx, BX_INSTR_DEC16); } void -BX_CPU_C::ADD_EwGw(BxInstruction_t *i) +BX_CPU_C::ADD_EwGw(bxInstruction_c *i) { Bit16u op2_16, op1_16, sum_16; /* op2_16 is a register, i->rm_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -81,8 +83,8 @@ BX_CPU_C::ADD_EwGw(BxInstruction_t *i) sum_16 = op1_16 + op2_16; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, sum_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), sum_16); } else { write_virtual_word(i->seg, i->rm_addr, &sum_16); @@ -93,17 +95,17 @@ BX_CPU_C::ADD_EwGw(BxInstruction_t *i) void -BX_CPU_C::ADD_GwEw(BxInstruction_t *i) +BX_CPU_C::ADD_GwEw(bxInstruction_c *i) { Bit16u op1_16, op2_16, sum_16; /* op1_16 is a register, i->rm_addr is an index of a register */ - op1_16 = BX_READ_16BIT_REG(i->nnn); + op1_16 = BX_READ_16BIT_REG(i->nnn()); /* op2_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -113,20 +115,20 @@ BX_CPU_C::ADD_GwEw(BxInstruction_t *i) sum_16 = op1_16 + op2_16; /* now write sum back to destination */ - BX_WRITE_16BIT_REG(i->nnn, sum_16); + BX_WRITE_16BIT_REG(i->nnn(), sum_16); SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD16); } void -BX_CPU_C::ADD_AXIw(BxInstruction_t *i) +BX_CPU_C::ADD_AXIw(bxInstruction_c *i) { Bit16u op1_16, op2_16, sum_16; op1_16 = AX; - op2_16 = i->Iw; + op2_16 = i->Iw(); sum_16 = op1_16 + op2_16; @@ -137,7 +139,7 @@ BX_CPU_C::ADD_AXIw(BxInstruction_t *i) } void -BX_CPU_C::ADC_EwGw(BxInstruction_t *i) +BX_CPU_C::ADC_EwGw(bxInstruction_c *i) { Boolean temp_CF; Bit16u op2_16, op1_16, sum_16; @@ -148,11 +150,11 @@ BX_CPU_C::ADC_EwGw(BxInstruction_t *i) /* op2_16 is a register, i->rm_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -162,8 +164,8 @@ BX_CPU_C::ADC_EwGw(BxInstruction_t *i) sum_16 = op1_16 + op2_16 + temp_CF; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, sum_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), sum_16); } else { Write_RMW_virtual_word(sum_16); @@ -175,7 +177,7 @@ BX_CPU_C::ADC_EwGw(BxInstruction_t *i) void -BX_CPU_C::ADC_GwEw(BxInstruction_t *i) +BX_CPU_C::ADC_GwEw(bxInstruction_c *i) { Boolean temp_CF; Bit16u op1_16, op2_16, sum_16; @@ -184,11 +186,11 @@ BX_CPU_C::ADC_GwEw(BxInstruction_t *i) /* op1_16 is a register, i->rm_addr is an index of a register */ - op1_16 = BX_READ_16BIT_REG(i->nnn); + op1_16 = BX_READ_16BIT_REG(i->nnn()); /* op2_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -198,7 +200,7 @@ BX_CPU_C::ADC_GwEw(BxInstruction_t *i) sum_16 = op1_16 + op2_16 + temp_CF; /* now write sum back to destination */ - BX_WRITE_16BIT_REG(i->nnn, sum_16); + BX_WRITE_16BIT_REG(i->nnn(), sum_16); SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16, temp_CF); @@ -206,7 +208,7 @@ BX_CPU_C::ADC_GwEw(BxInstruction_t *i) void -BX_CPU_C::ADC_AXIw(BxInstruction_t *i) +BX_CPU_C::ADC_AXIw(bxInstruction_c *i) { Boolean temp_CF; Bit16u op1_16, op2_16, sum_16; @@ -215,7 +217,7 @@ BX_CPU_C::ADC_AXIw(BxInstruction_t *i) op1_16 = AX; - op2_16 = i->Iw; + op2_16 = i->Iw(); sum_16 = op1_16 + op2_16 + temp_CF; @@ -230,7 +232,7 @@ BX_CPU_C::ADC_AXIw(BxInstruction_t *i) void -BX_CPU_C::SBB_EwGw(BxInstruction_t *i) +BX_CPU_C::SBB_EwGw(bxInstruction_c *i) { Boolean temp_CF; Bit16u op2_16, op1_16, diff_16; @@ -240,11 +242,11 @@ BX_CPU_C::SBB_EwGw(BxInstruction_t *i) /* op2_16 is a register, i->rm_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -254,8 +256,8 @@ BX_CPU_C::SBB_EwGw(BxInstruction_t *i) diff_16 = op1_16 - (op2_16 + temp_CF); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, diff_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), diff_16); } else { Write_RMW_virtual_word(diff_16); @@ -267,7 +269,7 @@ BX_CPU_C::SBB_EwGw(BxInstruction_t *i) void -BX_CPU_C::SBB_GwEw(BxInstruction_t *i) +BX_CPU_C::SBB_GwEw(bxInstruction_c *i) { Boolean temp_CF; @@ -278,11 +280,11 @@ BX_CPU_C::SBB_GwEw(BxInstruction_t *i) /* op1_16 is a register, i->rm_addr is an index of a register */ - op1_16 = BX_READ_16BIT_REG(i->nnn); + op1_16 = BX_READ_16BIT_REG(i->nnn()); /* op2_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -292,7 +294,7 @@ BX_CPU_C::SBB_GwEw(BxInstruction_t *i) diff_16 = op1_16 - (op2_16 + temp_CF); /* now write diff back to destination */ - BX_WRITE_16BIT_REG(i->nnn, diff_16); + BX_WRITE_16BIT_REG(i->nnn(), diff_16); SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, diff_16, BX_INSTR_SBB16, temp_CF); @@ -300,7 +302,7 @@ BX_CPU_C::SBB_GwEw(BxInstruction_t *i) void -BX_CPU_C::SBB_AXIw(BxInstruction_t *i) +BX_CPU_C::SBB_AXIw(bxInstruction_c *i) { Boolean temp_CF; Bit16u op1_16, op2_16, diff_16; @@ -310,7 +312,7 @@ BX_CPU_C::SBB_AXIw(BxInstruction_t *i) op1_16 = AX; - op2_16 = i->Iw; + op2_16 = i->Iw(); diff_16 = op1_16 - (op2_16 + temp_CF); @@ -324,7 +326,7 @@ BX_CPU_C::SBB_AXIw(BxInstruction_t *i) void -BX_CPU_C::SBB_EwIw(BxInstruction_t *i) +BX_CPU_C::SBB_EwIw(bxInstruction_c *i) { Boolean temp_CF; Bit16u op2_16, op1_16, diff_16; @@ -334,11 +336,11 @@ BX_CPU_C::SBB_EwIw(BxInstruction_t *i) - op2_16 = i->Iw; + op2_16 = i->Iw(); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -348,8 +350,8 @@ BX_CPU_C::SBB_EwIw(BxInstruction_t *i) diff_16 = op1_16 - (op2_16 + temp_CF); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, diff_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), diff_16); } else { Write_RMW_virtual_word(diff_16); @@ -361,17 +363,17 @@ BX_CPU_C::SBB_EwIw(BxInstruction_t *i) void -BX_CPU_C::SUB_EwGw(BxInstruction_t *i) +BX_CPU_C::SUB_EwGw(bxInstruction_c *i) { Bit16u op2_16, op1_16, diff_16; /* op2_16 is a register, i->rm_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -381,8 +383,8 @@ BX_CPU_C::SUB_EwGw(BxInstruction_t *i) diff_16 = op1_16 - op2_16; /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, diff_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), diff_16); } else { Write_RMW_virtual_word(diff_16); @@ -393,17 +395,17 @@ BX_CPU_C::SUB_EwGw(BxInstruction_t *i) void -BX_CPU_C::SUB_GwEw(BxInstruction_t *i) +BX_CPU_C::SUB_GwEw(bxInstruction_c *i) { Bit16u op1_16, op2_16, diff_16; /* op1_16 is a register, i->rm_addr is an index of a register */ - op1_16 = BX_READ_16BIT_REG(i->nnn); + op1_16 = BX_READ_16BIT_REG(i->nnn()); /* op2_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -413,19 +415,19 @@ BX_CPU_C::SUB_GwEw(BxInstruction_t *i) diff_16 = op1_16 - op2_16; /* now write diff back to destination */ - BX_WRITE_16BIT_REG(i->nnn, diff_16); + BX_WRITE_16BIT_REG(i->nnn(), diff_16); SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_SUB16); } void -BX_CPU_C::SUB_AXIw(BxInstruction_t *i) +BX_CPU_C::SUB_AXIw(bxInstruction_c *i) { Bit16u op1_16, op2_16, diff_16; op1_16 = AX; - op2_16 = i->Iw; + op2_16 = i->Iw(); diff_16 = op1_16 - op2_16; @@ -438,17 +440,17 @@ BX_CPU_C::SUB_AXIw(BxInstruction_t *i) void -BX_CPU_C::CMP_EwGw(BxInstruction_t *i) +BX_CPU_C::CMP_EwGw(bxInstruction_c *i) { Bit16u op2_16, op1_16, diff_16; /* op2_16 is a register, i->rm_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -462,17 +464,17 @@ BX_CPU_C::CMP_EwGw(BxInstruction_t *i) void -BX_CPU_C::CMP_GwEw(BxInstruction_t *i) +BX_CPU_C::CMP_GwEw(bxInstruction_c *i) { Bit16u op1_16, op2_16, diff_16; /* op1_16 is a register, i->rm_addr is an index of a register */ - op1_16 = BX_READ_16BIT_REG(i->nnn); + op1_16 = BX_READ_16BIT_REG(i->nnn()); /* op2_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -486,13 +488,13 @@ BX_CPU_C::CMP_GwEw(BxInstruction_t *i) void -BX_CPU_C::CMP_AXIw(BxInstruction_t *i) +BX_CPU_C::CMP_AXIw(bxInstruction_c *i) { Bit16u op1_16, op2_16, diff_16; op1_16 = AX; - op2_16 = i->Iw; + op2_16 = i->Iw(); diff_16 = op1_16 - op2_16; @@ -501,7 +503,7 @@ BX_CPU_C::CMP_AXIw(BxInstruction_t *i) void -BX_CPU_C::CBW(BxInstruction_t *i) +BX_CPU_C::CBW(bxInstruction_c *i) { /* CBW: no flags are effected */ @@ -509,7 +511,7 @@ BX_CPU_C::CBW(BxInstruction_t *i) } void -BX_CPU_C::CWD(BxInstruction_t *i) +BX_CPU_C::CWD(bxInstruction_c *i) { /* CWD: no flags are affected */ @@ -523,7 +525,7 @@ BX_CPU_C::CWD(BxInstruction_t *i) void -BX_CPU_C::XADD_EwGw(BxInstruction_t *i) +BX_CPU_C::XADD_EwGw(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -536,11 +538,11 @@ BX_CPU_C::XADD_EwGw(BxInstruction_t *i) */ /* op2 is a register, i->rm_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -550,18 +552,18 @@ BX_CPU_C::XADD_EwGw(BxInstruction_t *i) sum_16 = op1_16 + op2_16; /* now write sum back to destination */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { // and write destination into source // Note: if both op1 & op2 are registers, the last one written // should be the sum, as op1 & op2 may be the same register. // For example: XADD AL, AL - BX_WRITE_16BIT_REG(i->nnn, op1_16); - BX_WRITE_16BIT_REG(i->rm, sum_16); + BX_WRITE_16BIT_REG(i->nnn(), op1_16); + BX_WRITE_16BIT_REG(i->rm(), sum_16); } else { Write_RMW_virtual_word(sum_16); /* and write destination into source */ - BX_WRITE_16BIT_REG(i->nnn, op1_16); + BX_WRITE_16BIT_REG(i->nnn(), op1_16); } @@ -574,15 +576,15 @@ BX_CPU_C::XADD_EwGw(BxInstruction_t *i) void -BX_CPU_C::ADD_EwIw(BxInstruction_t *i) +BX_CPU_C::ADD_EwIw(bxInstruction_c *i) { Bit16u op2_16, op1_16, sum_16; - op2_16 = i->Iw; + op2_16 = i->Iw(); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -604,8 +606,8 @@ BX_CPU_C::ADD_EwIw(BxInstruction_t *i) #endif /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, sum_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), sum_16); } else { Write_RMW_virtual_word(sum_16); @@ -621,7 +623,7 @@ BX_CPU_C::ADD_EwIw(BxInstruction_t *i) } void -BX_CPU_C::ADC_EwIw(BxInstruction_t *i) +BX_CPU_C::ADC_EwIw(bxInstruction_c *i) { Boolean temp_CF; Bit16u op2_16, op1_16, sum_16; @@ -629,11 +631,11 @@ BX_CPU_C::ADC_EwIw(BxInstruction_t *i) temp_CF = get_CF(); - op2_16 = i->Iw; + op2_16 = i->Iw(); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -643,8 +645,8 @@ BX_CPU_C::ADC_EwIw(BxInstruction_t *i) sum_16 = op1_16 + op2_16 + temp_CF; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, sum_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), sum_16); } else { Write_RMW_virtual_word(sum_16); @@ -656,16 +658,16 @@ BX_CPU_C::ADC_EwIw(BxInstruction_t *i) void -BX_CPU_C::SUB_EwIw(BxInstruction_t *i) +BX_CPU_C::SUB_EwIw(bxInstruction_c *i) { Bit16u op2_16, op1_16, diff_16; - op2_16 = i->Iw; + op2_16 = i->Iw(); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -675,8 +677,8 @@ BX_CPU_C::SUB_EwIw(BxInstruction_t *i) diff_16 = op1_16 - op2_16; /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, diff_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), diff_16); } else { Write_RMW_virtual_word(diff_16); @@ -686,16 +688,16 @@ BX_CPU_C::SUB_EwIw(BxInstruction_t *i) } void -BX_CPU_C::CMP_EwIw(BxInstruction_t *i) +BX_CPU_C::CMP_EwIw(bxInstruction_c *i) { Bit16u op2_16, op1_16, diff_16; - op2_16 = i->Iw; + op2_16 = i->Iw(); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -710,14 +712,14 @@ BX_CPU_C::CMP_EwIw(BxInstruction_t *i) void -BX_CPU_C::NEG_Ew(BxInstruction_t *i) +BX_CPU_C::NEG_Ew(bxInstruction_c *i) { Bit16u op1_16, diff_16; /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -727,8 +729,8 @@ BX_CPU_C::NEG_Ew(BxInstruction_t *i) diff_16 = 0 - op1_16; /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, diff_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), diff_16); } else { Write_RMW_virtual_word(diff_16); @@ -739,13 +741,13 @@ BX_CPU_C::NEG_Ew(BxInstruction_t *i) void -BX_CPU_C::INC_Ew(BxInstruction_t *i) +BX_CPU_C::INC_Ew(bxInstruction_c *i) { Bit16u op1_16; /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -755,8 +757,8 @@ BX_CPU_C::INC_Ew(BxInstruction_t *i) op1_16++; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, op1_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), op1_16); } else { Write_RMW_virtual_word(op1_16); @@ -767,13 +769,13 @@ BX_CPU_C::INC_Ew(BxInstruction_t *i) void -BX_CPU_C::DEC_Ew(BxInstruction_t *i) +BX_CPU_C::DEC_Ew(bxInstruction_c *i) { Bit16u op1_16; /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -783,8 +785,8 @@ BX_CPU_C::DEC_Ew(BxInstruction_t *i) op1_16--; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, op1_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), op1_16); } else { Write_RMW_virtual_word(op1_16); @@ -795,15 +797,15 @@ BX_CPU_C::DEC_Ew(BxInstruction_t *i) void -BX_CPU_C::CMPXCHG_EwGw(BxInstruction_t *i) +BX_CPU_C::CMPXCHG_EwGw(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) Bit16u op2_16, op1_16, diff_16; /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -818,10 +820,10 @@ BX_CPU_C::CMPXCHG_EwGw(BxInstruction_t *i) // ZF = 1 set_ZF(1); // dest <-- src - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, op2_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), op2_16); } else { Write_RMW_virtual_word(op2_16); diff --git a/bochs/cpu/arith32.cc b/bochs/cpu/arith32.cc index 2f9fcb2b0..e78f159bd 100644 --- a/bochs/cpu/arith32.cc +++ b/bochs/cpu/arith32.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: arith32.cc,v 1.11 2002-09-15 01:36:13 kevinlawton Exp $ +// $Id: arith32.cc,v 1.12 2002-09-17 22:50:51 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -41,30 +41,40 @@ void -BX_CPU_C::INC_ERX(BxInstruction_t *i) +BX_CPU_C::INC_ERX(bxInstruction_c *i) { Bit32u erx; + erx = ++ BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].dword.erx; #if BX_SUPPORT_X86_64 - erx = ++ BX_CPU_THIS_PTR gen_reg[i->nnn].dword.erx; - BX_CPU_THIS_PTR gen_reg[i->nnn].dword.hrx = 0; -#else - erx = ++ BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx; + BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].dword.hrx = 0; #endif + +//#if BX_SUPPORT_X86_64 +// erx = ++ BX_CPU_THIS_PTR gen_reg[i->nnn()].dword.erx; +// BX_CPU_THIS_PTR gen_reg[i->nnn()].dword.hrx = 0; +//#else +// erx = ++ BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx; +//#endif SET_FLAGS_OSZAP_32(0, 0, erx, BX_INSTR_INC32); } void -BX_CPU_C::DEC_ERX(BxInstruction_t *i) +BX_CPU_C::DEC_ERX(bxInstruction_c *i) { Bit32u erx; + erx = -- BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].dword.erx; #if BX_SUPPORT_X86_64 - erx = -- BX_CPU_THIS_PTR gen_reg[i->nnn].dword.erx; - BX_CPU_THIS_PTR gen_reg[i->nnn].dword.hrx = 0; -#else - erx = -- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx; + BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].dword.hrx = 0; #endif + +//#if BX_SUPPORT_X86_64 +// erx = -- BX_CPU_THIS_PTR gen_reg[i->nnn()].dword.erx; +// BX_CPU_THIS_PTR gen_reg[i->nnn()].dword.hrx = 0; +//#else +// erx = -- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx; +//#endif SET_FLAGS_OSZAP_32(0, 0, erx, BX_INSTR_DEC32); } @@ -72,17 +82,17 @@ BX_CPU_C::DEC_ERX(BxInstruction_t *i) void -BX_CPU_C::ADD_EdGd(BxInstruction_t *i) +BX_CPU_C::ADD_EdGd(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op2_32, op1_32, sum_32; /* op2_32 is a register, i->rm_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -92,8 +102,8 @@ BX_CPU_C::ADD_EdGd(BxInstruction_t *i) sum_32 = op1_32 + op2_32; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, sum_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), sum_32); } else { Write_RMW_virtual_dword(sum_32); @@ -104,17 +114,17 @@ BX_CPU_C::ADD_EdGd(BxInstruction_t *i) void -BX_CPU_C::ADD_GdEd(BxInstruction_t *i) +BX_CPU_C::ADD_GdEd(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op1_32, op2_32, sum_32; /* op1_32 is a register, i->rm_addr is an index of a register */ - op1_32 = BX_READ_32BIT_REG(i->nnn); + op1_32 = BX_READ_32BIT_REG(i->nnn()); /* op2_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -124,21 +134,21 @@ BX_CPU_C::ADD_GdEd(BxInstruction_t *i) sum_32 = op1_32 + op2_32; /* now write sum back to destination */ - BX_WRITE_32BIT_REGZ(i->nnn, sum_32); + BX_WRITE_32BIT_REGZ(i->nnn(), sum_32); SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32); } void -BX_CPU_C::ADD_EAXId(BxInstruction_t *i) +BX_CPU_C::ADD_EAXId(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op1_32, op2_32, sum_32; op1_32 = EAX; - op2_32 = i->Id; + op2_32 = i->Id(); sum_32 = op1_32 + op2_32; @@ -149,7 +159,7 @@ BX_CPU_C::ADD_EAXId(BxInstruction_t *i) } void -BX_CPU_C::ADC_EdGd(BxInstruction_t *i) +BX_CPU_C::ADC_EdGd(bxInstruction_c *i) { Boolean temp_CF; @@ -160,11 +170,11 @@ BX_CPU_C::ADC_EdGd(BxInstruction_t *i) Bit32u op2_32, op1_32, sum_32; /* op2_32 is a register, i->rm_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -174,8 +184,8 @@ BX_CPU_C::ADC_EdGd(BxInstruction_t *i) sum_32 = op1_32 + op2_32 + temp_CF; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, sum_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), sum_32); } else { Write_RMW_virtual_dword(sum_32); @@ -187,7 +197,7 @@ BX_CPU_C::ADC_EdGd(BxInstruction_t *i) void -BX_CPU_C::ADC_GdEd(BxInstruction_t *i) +BX_CPU_C::ADC_GdEd(bxInstruction_c *i) { Boolean temp_CF; @@ -198,11 +208,11 @@ BX_CPU_C::ADC_GdEd(BxInstruction_t *i) Bit32u op1_32, op2_32, sum_32; /* op1_32 is a register, i->rm_addr is an index of a register */ - op1_32 = BX_READ_32BIT_REG(i->nnn); + op1_32 = BX_READ_32BIT_REG(i->nnn()); /* op2_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -212,7 +222,7 @@ BX_CPU_C::ADC_GdEd(BxInstruction_t *i) sum_32 = op1_32 + op2_32 + temp_CF; /* now write sum back to destination */ - BX_WRITE_32BIT_REGZ(i->nnn, sum_32); + BX_WRITE_32BIT_REGZ(i->nnn(), sum_32); SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, sum_32, BX_INSTR_ADC32, temp_CF); @@ -220,7 +230,7 @@ BX_CPU_C::ADC_GdEd(BxInstruction_t *i) void -BX_CPU_C::ADC_EAXId(BxInstruction_t *i) +BX_CPU_C::ADC_EAXId(bxInstruction_c *i) { Boolean temp_CF; @@ -231,7 +241,7 @@ BX_CPU_C::ADC_EAXId(BxInstruction_t *i) op1_32 = EAX; - op2_32 = i->Id; + op2_32 = i->Id(); sum_32 = op1_32 + op2_32 + temp_CF; @@ -246,7 +256,7 @@ BX_CPU_C::ADC_EAXId(BxInstruction_t *i) void -BX_CPU_C::SBB_EdGd(BxInstruction_t *i) +BX_CPU_C::SBB_EdGd(bxInstruction_c *i) { Boolean temp_CF; @@ -257,11 +267,11 @@ BX_CPU_C::SBB_EdGd(BxInstruction_t *i) Bit32u op2_32, op1_32, diff_32; /* op2_32 is a register, i->rm_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -271,8 +281,8 @@ BX_CPU_C::SBB_EdGd(BxInstruction_t *i) diff_32 = op1_32 - (op2_32 + temp_CF); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, diff_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), diff_32); } else { Write_RMW_virtual_dword(diff_32); @@ -284,7 +294,7 @@ BX_CPU_C::SBB_EdGd(BxInstruction_t *i) void -BX_CPU_C::SBB_GdEd(BxInstruction_t *i) +BX_CPU_C::SBB_GdEd(bxInstruction_c *i) { Boolean temp_CF; @@ -295,11 +305,11 @@ BX_CPU_C::SBB_GdEd(BxInstruction_t *i) Bit32u op1_32, op2_32, diff_32; /* op1_32 is a register, i->rm_addr is an index of a register */ - op1_32 = BX_READ_32BIT_REG(i->nnn); + op1_32 = BX_READ_32BIT_REG(i->nnn()); /* op2_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -309,7 +319,7 @@ BX_CPU_C::SBB_GdEd(BxInstruction_t *i) diff_32 = op1_32 - (op2_32 + temp_CF); /* now write diff back to destination */ - BX_WRITE_32BIT_REGZ(i->nnn, diff_32); + BX_WRITE_32BIT_REGZ(i->nnn(), diff_32); SET_FLAGS_OSZAPC_32_CF(op1_32, op2_32, diff_32, BX_INSTR_SBB32, temp_CF); @@ -317,7 +327,7 @@ BX_CPU_C::SBB_GdEd(BxInstruction_t *i) void -BX_CPU_C::SBB_EAXId(BxInstruction_t *i) +BX_CPU_C::SBB_EAXId(bxInstruction_c *i) { Boolean temp_CF; @@ -328,7 +338,7 @@ BX_CPU_C::SBB_EAXId(BxInstruction_t *i) op1_32 = EAX; - op2_32 = i->Id; + op2_32 = i->Id(); diff_32 = op1_32 - (op2_32 + temp_CF); @@ -342,7 +352,7 @@ BX_CPU_C::SBB_EAXId(BxInstruction_t *i) void -BX_CPU_C::SBB_EdId(BxInstruction_t *i) +BX_CPU_C::SBB_EdId(bxInstruction_c *i) { Boolean temp_CF; @@ -352,11 +362,11 @@ BX_CPU_C::SBB_EdId(BxInstruction_t *i) /* for 32 bit operand size mode */ Bit32u op2_32, op1_32, diff_32; - op2_32 = i->Id; + op2_32 = i->Id(); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -366,8 +376,8 @@ BX_CPU_C::SBB_EdId(BxInstruction_t *i) diff_32 = op1_32 - (op2_32 + temp_CF); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, diff_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), diff_32); } else { Write_RMW_virtual_dword(diff_32); @@ -379,17 +389,17 @@ BX_CPU_C::SBB_EdId(BxInstruction_t *i) void -BX_CPU_C::SUB_EdGd(BxInstruction_t *i) +BX_CPU_C::SUB_EdGd(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op2_32, op1_32, diff_32; /* op2_32 is a register, i->rm_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -399,8 +409,8 @@ BX_CPU_C::SUB_EdGd(BxInstruction_t *i) diff_32 = op1_32 - op2_32; /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, diff_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), diff_32); } else { Write_RMW_virtual_dword(diff_32); @@ -411,17 +421,17 @@ BX_CPU_C::SUB_EdGd(BxInstruction_t *i) void -BX_CPU_C::SUB_GdEd(BxInstruction_t *i) +BX_CPU_C::SUB_GdEd(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op1_32, op2_32, diff_32; /* op1_32 is a register, i->rm_addr is an index of a register */ - op1_32 = BX_READ_32BIT_REG(i->nnn); + op1_32 = BX_READ_32BIT_REG(i->nnn()); /* op2_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -431,20 +441,20 @@ BX_CPU_C::SUB_GdEd(BxInstruction_t *i) diff_32 = op1_32 - op2_32; /* now write diff back to destination */ - BX_WRITE_32BIT_REGZ(i->nnn, diff_32); + BX_WRITE_32BIT_REGZ(i->nnn(), diff_32); SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_INSTR_SUB32); } void -BX_CPU_C::SUB_EAXId(BxInstruction_t *i) +BX_CPU_C::SUB_EAXId(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op1_32, op2_32, diff_32; op1_32 = EAX; - op2_32 = i->Id; + op2_32 = i->Id(); diff_32 = op1_32 - op2_32; @@ -456,17 +466,17 @@ BX_CPU_C::SUB_EAXId(BxInstruction_t *i) void -BX_CPU_C::CMP_EdGd(BxInstruction_t *i) +BX_CPU_C::CMP_EdGd(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op2_32, op1_32, diff_32; /* op2_32 is a register, i->rm_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -480,17 +490,17 @@ BX_CPU_C::CMP_EdGd(BxInstruction_t *i) void -BX_CPU_C::CMP_GdEd(BxInstruction_t *i) +BX_CPU_C::CMP_GdEd(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op1_32, op2_32, diff_32; /* op1_32 is a register, i->rm_addr is an index of a register */ - op1_32 = BX_READ_32BIT_REG(i->nnn); + op1_32 = BX_READ_32BIT_REG(i->nnn()); /* op2_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -504,14 +514,14 @@ BX_CPU_C::CMP_GdEd(BxInstruction_t *i) void -BX_CPU_C::CMP_EAXId(BxInstruction_t *i) +BX_CPU_C::CMP_EAXId(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op1_32, op2_32, diff_32; op1_32 = EAX; - op2_32 = i->Id; + op2_32 = i->Id(); diff_32 = op1_32 - op2_32; @@ -520,7 +530,7 @@ BX_CPU_C::CMP_EAXId(BxInstruction_t *i) void -BX_CPU_C::CWDE(BxInstruction_t *i) +BX_CPU_C::CWDE(bxInstruction_c *i) { /* CBW: no flags are effected */ Bit32u temp; @@ -530,7 +540,7 @@ BX_CPU_C::CWDE(BxInstruction_t *i) } void -BX_CPU_C::CDQ(BxInstruction_t *i) +BX_CPU_C::CDQ(bxInstruction_c *i) { /* CDQ: no flags are affected */ @@ -556,14 +566,14 @@ BX_CPU_C::CDQ(BxInstruction_t *i) // {OF,B1} = CMPXCHG 16|32 void -BX_CPU_C::CMPXCHG_XBTS(BxInstruction_t *i) +BX_CPU_C::CMPXCHG_XBTS(bxInstruction_c *i) { BX_INFO(("CMPXCHG_XBTS:")); UndefinedOpcode(i); } void -BX_CPU_C::CMPXCHG_IBTS(BxInstruction_t *i) +BX_CPU_C::CMPXCHG_IBTS(bxInstruction_c *i) { BX_INFO(("CMPXCHG_IBTS:")); UndefinedOpcode(i); @@ -571,7 +581,7 @@ BX_CPU_C::CMPXCHG_IBTS(BxInstruction_t *i) void -BX_CPU_C::XADD_EdGd(BxInstruction_t *i) +BX_CPU_C::XADD_EdGd(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -584,11 +594,11 @@ BX_CPU_C::XADD_EdGd(BxInstruction_t *i) */ /* op2 is a register, i->rm_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -598,18 +608,18 @@ BX_CPU_C::XADD_EdGd(BxInstruction_t *i) sum_32 = op1_32 + op2_32; /* now write sum back to destination */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { // and write destination into source // Note: if both op1 & op2 are registers, the last one written // should be the sum, as op1 & op2 may be the same register. // For example: XADD AL, AL - BX_WRITE_32BIT_REGZ(i->nnn, op1_32); - BX_WRITE_32BIT_REGZ(i->rm, sum_32); + BX_WRITE_32BIT_REGZ(i->nnn(), op1_32); + BX_WRITE_32BIT_REGZ(i->rm(), sum_32); } else { Write_RMW_virtual_dword(sum_32); /* and write destination into source */ - BX_WRITE_32BIT_REGZ(i->nnn, op1_32); + BX_WRITE_32BIT_REGZ(i->nnn(), op1_32); } @@ -622,15 +632,15 @@ BX_CPU_C::XADD_EdGd(BxInstruction_t *i) void -BX_CPU_C::ADD_EdId(BxInstruction_t *i) +BX_CPU_C::ADD_EdId(bxInstruction_c *i) { Bit32u op2_32, op1_32, sum_32; - op2_32 = i->Id; + op2_32 = i->Id(); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -652,8 +662,8 @@ BX_CPU_C::ADD_EdId(BxInstruction_t *i) #endif /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, sum_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), sum_32); } else { Write_RMW_virtual_dword(sum_32); @@ -669,7 +679,7 @@ BX_CPU_C::ADD_EdId(BxInstruction_t *i) } void -BX_CPU_C::ADC_EdId(BxInstruction_t *i) +BX_CPU_C::ADC_EdId(bxInstruction_c *i) { Boolean temp_CF; @@ -678,11 +688,11 @@ BX_CPU_C::ADC_EdId(BxInstruction_t *i) /* for 32 bit operand size mode */ Bit32u op2_32, op1_32, sum_32; - op2_32 = i->Id; + op2_32 = i->Id(); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -692,8 +702,8 @@ BX_CPU_C::ADC_EdId(BxInstruction_t *i) sum_32 = op1_32 + op2_32 + temp_CF; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, sum_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), sum_32); } else { Write_RMW_virtual_dword(sum_32); @@ -705,16 +715,16 @@ BX_CPU_C::ADC_EdId(BxInstruction_t *i) void -BX_CPU_C::SUB_EdId(BxInstruction_t *i) +BX_CPU_C::SUB_EdId(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op2_32, op1_32, diff_32; - op2_32 = i->Id; + op2_32 = i->Id(); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -724,8 +734,8 @@ BX_CPU_C::SUB_EdId(BxInstruction_t *i) diff_32 = op1_32 - op2_32; /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, diff_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), diff_32); } else { Write_RMW_virtual_dword(diff_32); @@ -735,16 +745,16 @@ BX_CPU_C::SUB_EdId(BxInstruction_t *i) } void -BX_CPU_C::CMP_EdId(BxInstruction_t *i) +BX_CPU_C::CMP_EdId(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op2_32, op1_32, diff_32; - op2_32 = i->Id; + op2_32 = i->Id(); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -760,14 +770,14 @@ BX_CPU_C::CMP_EdId(BxInstruction_t *i) void -BX_CPU_C::NEG_Ed(BxInstruction_t *i) +BX_CPU_C::NEG_Ed(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op1_32, diff_32; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -777,8 +787,8 @@ BX_CPU_C::NEG_Ed(BxInstruction_t *i) diff_32 = 0 - op1_32; /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, diff_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), diff_32); } else { Write_RMW_virtual_dword(diff_32); @@ -789,13 +799,13 @@ BX_CPU_C::NEG_Ed(BxInstruction_t *i) void -BX_CPU_C::INC_Ed(BxInstruction_t *i) +BX_CPU_C::INC_Ed(bxInstruction_c *i) { Bit32u op1_32; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -805,8 +815,8 @@ BX_CPU_C::INC_Ed(BxInstruction_t *i) op1_32++; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, op1_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), op1_32); } else { Write_RMW_virtual_dword(op1_32); @@ -817,13 +827,13 @@ BX_CPU_C::INC_Ed(BxInstruction_t *i) void -BX_CPU_C::DEC_Ed(BxInstruction_t *i) +BX_CPU_C::DEC_Ed(bxInstruction_c *i) { Bit32u op1_32; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -833,8 +843,8 @@ BX_CPU_C::DEC_Ed(BxInstruction_t *i) op1_32--; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, op1_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), op1_32); } else { Write_RMW_virtual_dword(op1_32); @@ -845,15 +855,15 @@ BX_CPU_C::DEC_Ed(BxInstruction_t *i) void -BX_CPU_C::CMPXCHG_EdGd(BxInstruction_t *i) +BX_CPU_C::CMPXCHG_EdGd(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) Bit32u op2_32, op1_32, diff_32; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -868,10 +878,10 @@ BX_CPU_C::CMPXCHG_EdGd(BxInstruction_t *i) // ZF = 1 set_ZF(1); // dest <-- src - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, op2_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), op2_32); } else { Write_RMW_virtual_dword(op2_32); @@ -889,13 +899,13 @@ BX_CPU_C::CMPXCHG_EdGd(BxInstruction_t *i) } void -BX_CPU_C::CMPXCHG8B(BxInstruction_t *i) +BX_CPU_C::CMPXCHG8B(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 5) || (BX_CPU_LEVEL_HACKED >= 5) Bit32u op1_64_lo, op1_64_hi, diff; - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_INFO(("CMPXCHG8B: dest is reg: #UD")); UndefinedOpcode(i); } diff --git a/bochs/cpu/arith64.cc b/bochs/cpu/arith64.cc index adc41ceac..b9d8aac36 100644 --- a/bochs/cpu/arith64.cc +++ b/bochs/cpu/arith64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: arith64.cc,v 1.1 2002-09-13 15:53:22 kevinlawton Exp $ +// $Id: arith64.cc,v 1.2 2002-09-17 22:50:51 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -35,20 +35,22 @@ /* I don't think these versions accessible in 64 bit mode void -BX_CPU_C::INC_RRX(BxInstruction_t *i) +BX_CPU_C::INC_RRX(bxInstruction_c *i) { Bit32u rrx; - rrx = ++ BX_CPU_THIS_PTR gen_reg[i->nnn].rrx; + rrx = ++ BX_CPU_THIS_PTR gen_reg[(i->b1 & 0x07) + i->rex_b()].rrx; + //rrx = ++ BX_CPU_THIS_PTR gen_reg[i->nnn()].rrx; SET_FLAGS_OSZAP_64(0, 0, rrx, BX_INSTR_INC64); } void -BX_CPU_C::DEC_RRX(BxInstruction_t *i) +BX_CPU_C::DEC_RRX(bxInstruction_c *i) { Bit32u rrx; - rrx = -- BX_CPU_THIS_PTR gen_reg[i->nnn].rrx; + rrx = -- BX_CPU_THIS_PTR gen_reg[(i->b1 & 0x07) + i->rex_b()].rrx; + //rrx = -- BX_CPU_THIS_PTR gen_reg[i->nnn()].rrx; SET_FLAGS_OSZAP_64(0, 0, rrx, BX_INSTR_DEC64); } @@ -57,17 +59,17 @@ BX_CPU_C::DEC_RRX(BxInstruction_t *i) void -BX_CPU_C::ADD_EqGq(BxInstruction_t *i) +BX_CPU_C::ADD_EqGq(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op2_64, op1_64, sum_64; /* op2_64 is a register, i->rm_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -77,8 +79,8 @@ BX_CPU_C::ADD_EqGq(BxInstruction_t *i) sum_64 = op1_64 + op2_64; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, sum_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), sum_64); } else { write_RMW_virtual_qword(sum_64); @@ -89,17 +91,17 @@ BX_CPU_C::ADD_EqGq(BxInstruction_t *i) void -BX_CPU_C::ADD_GqEq(BxInstruction_t *i) +BX_CPU_C::ADD_GqEq(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op1_64, op2_64, sum_64; /* op1_64 is a register, i->rm_addr is an index of a register */ - op1_64 = BX_READ_64BIT_REG(i->nnn); + op1_64 = BX_READ_64BIT_REG(i->nnn()); /* op2_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -109,21 +111,21 @@ BX_CPU_C::ADD_GqEq(BxInstruction_t *i) sum_64 = op1_64 + op2_64; /* now write sum back to destination */ - BX_WRITE_64BIT_REG(i->nnn, sum_64); + BX_WRITE_64BIT_REG(i->nnn(), sum_64); SET_FLAGS_OSZAPC_64(op1_64, op2_64, sum_64, BX_INSTR_ADD64); } void -BX_CPU_C::ADD_RAXId(BxInstruction_t *i) +BX_CPU_C::ADD_RAXId(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op1_64, op2_64, sum_64; op1_64 = RAX; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); sum_64 = op1_64 + op2_64; @@ -134,7 +136,7 @@ BX_CPU_C::ADD_RAXId(BxInstruction_t *i) } void -BX_CPU_C::ADC_EqGq(BxInstruction_t *i) +BX_CPU_C::ADC_EqGq(bxInstruction_c *i) { Boolean temp_CF; @@ -145,11 +147,11 @@ BX_CPU_C::ADC_EqGq(BxInstruction_t *i) Bit64u op2_64, op1_64, sum_64; /* op2_64 is a register, i->rm_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -159,8 +161,8 @@ BX_CPU_C::ADC_EqGq(BxInstruction_t *i) sum_64 = op1_64 + op2_64 + temp_CF; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, sum_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), sum_64); } else { write_RMW_virtual_qword(sum_64); @@ -172,7 +174,7 @@ BX_CPU_C::ADC_EqGq(BxInstruction_t *i) void -BX_CPU_C::ADC_GqEq(BxInstruction_t *i) +BX_CPU_C::ADC_GqEq(bxInstruction_c *i) { Boolean temp_CF; @@ -183,11 +185,11 @@ BX_CPU_C::ADC_GqEq(BxInstruction_t *i) Bit64u op1_64, op2_64, sum_64; /* op1_64 is a register, i->rm_addr is an index of a register */ - op1_64 = BX_READ_64BIT_REG(i->nnn); + op1_64 = BX_READ_64BIT_REG(i->nnn()); /* op2_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -197,7 +199,7 @@ BX_CPU_C::ADC_GqEq(BxInstruction_t *i) sum_64 = op1_64 + op2_64 + temp_CF; /* now write sum back to destination */ - BX_WRITE_64BIT_REG(i->nnn, sum_64); + BX_WRITE_64BIT_REG(i->nnn(), sum_64); SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, sum_64, BX_INSTR_ADC64, temp_CF); @@ -205,7 +207,7 @@ BX_CPU_C::ADC_GqEq(BxInstruction_t *i) void -BX_CPU_C::ADC_RAXId(BxInstruction_t *i) +BX_CPU_C::ADC_RAXId(bxInstruction_c *i) { Boolean temp_CF; @@ -216,7 +218,7 @@ BX_CPU_C::ADC_RAXId(BxInstruction_t *i) op1_64 = RAX; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); sum_64 = op1_64 + op2_64 + temp_CF; @@ -231,7 +233,7 @@ BX_CPU_C::ADC_RAXId(BxInstruction_t *i) void -BX_CPU_C::SBB_EqGq(BxInstruction_t *i) +BX_CPU_C::SBB_EqGq(bxInstruction_c *i) { Boolean temp_CF; @@ -242,11 +244,11 @@ BX_CPU_C::SBB_EqGq(BxInstruction_t *i) Bit64u op2_64, op1_64, diff_64; /* op2_64 is a register, i->rm_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -256,8 +258,8 @@ BX_CPU_C::SBB_EqGq(BxInstruction_t *i) diff_64 = op1_64 - (op2_64 + temp_CF); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, diff_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), diff_64); } else { write_RMW_virtual_qword(diff_64); @@ -269,7 +271,7 @@ BX_CPU_C::SBB_EqGq(BxInstruction_t *i) void -BX_CPU_C::SBB_GqEq(BxInstruction_t *i) +BX_CPU_C::SBB_GqEq(bxInstruction_c *i) { Boolean temp_CF; @@ -280,11 +282,11 @@ BX_CPU_C::SBB_GqEq(BxInstruction_t *i) Bit64u op1_64, op2_64, diff_64; /* op1_64 is a register, i->rm_addr is an index of a register */ - op1_64 = BX_READ_64BIT_REG(i->nnn); + op1_64 = BX_READ_64BIT_REG(i->nnn()); /* op2_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -294,7 +296,7 @@ BX_CPU_C::SBB_GqEq(BxInstruction_t *i) diff_64 = op1_64 - (op2_64 + temp_CF); /* now write diff back to destination */ - BX_WRITE_64BIT_REG(i->nnn, diff_64); + BX_WRITE_64BIT_REG(i->nnn(), diff_64); SET_FLAGS_OSZAPC_64_CF(op1_64, op2_64, diff_64, BX_INSTR_SBB64, temp_CF); @@ -302,7 +304,7 @@ BX_CPU_C::SBB_GqEq(BxInstruction_t *i) void -BX_CPU_C::SBB_RAXId(BxInstruction_t *i) +BX_CPU_C::SBB_RAXId(bxInstruction_c *i) { Boolean temp_CF; @@ -313,7 +315,7 @@ BX_CPU_C::SBB_RAXId(BxInstruction_t *i) op1_64 = RAX; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); diff_64 = op1_64 - (op2_64 + temp_CF); @@ -327,7 +329,7 @@ BX_CPU_C::SBB_RAXId(BxInstruction_t *i) void -BX_CPU_C::SBB_EqId(BxInstruction_t *i) +BX_CPU_C::SBB_EqId(bxInstruction_c *i) { Boolean temp_CF; @@ -337,11 +339,11 @@ BX_CPU_C::SBB_EqId(BxInstruction_t *i) /* for 64 bit operand size mode */ Bit64u op2_64, op1_64, diff_64; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -351,8 +353,8 @@ BX_CPU_C::SBB_EqId(BxInstruction_t *i) diff_64 = op1_64 - (op2_64 + temp_CF); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, diff_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), diff_64); } else { write_RMW_virtual_qword(diff_64); @@ -364,17 +366,17 @@ BX_CPU_C::SBB_EqId(BxInstruction_t *i) void -BX_CPU_C::SUB_EqGq(BxInstruction_t *i) +BX_CPU_C::SUB_EqGq(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op2_64, op1_64, diff_64; /* op2_64 is a register, i->rm_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -384,8 +386,8 @@ BX_CPU_C::SUB_EqGq(BxInstruction_t *i) diff_64 = op1_64 - op2_64; /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, diff_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), diff_64); } else { write_RMW_virtual_qword(diff_64); @@ -396,17 +398,17 @@ BX_CPU_C::SUB_EqGq(BxInstruction_t *i) void -BX_CPU_C::SUB_GqEq(BxInstruction_t *i) +BX_CPU_C::SUB_GqEq(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op1_64, op2_64, diff_64; /* op1_64 is a register, i->rm_addr is an index of a register */ - op1_64 = BX_READ_64BIT_REG(i->nnn); + op1_64 = BX_READ_64BIT_REG(i->nnn()); /* op2_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -416,20 +418,20 @@ BX_CPU_C::SUB_GqEq(BxInstruction_t *i) diff_64 = op1_64 - op2_64; /* now write diff back to destination */ - BX_WRITE_64BIT_REG(i->nnn, diff_64); + BX_WRITE_64BIT_REG(i->nnn(), diff_64); SET_FLAGS_OSZAPC_64(op1_64, op2_64, diff_64, BX_INSTR_SUB64); } void -BX_CPU_C::SUB_RAXId(BxInstruction_t *i) +BX_CPU_C::SUB_RAXId(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op1_64, op2_64, diff_64; op1_64 = RAX; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); diff_64 = op1_64 - op2_64; @@ -441,17 +443,17 @@ BX_CPU_C::SUB_RAXId(BxInstruction_t *i) void -BX_CPU_C::CMP_EqGq(BxInstruction_t *i) +BX_CPU_C::CMP_EqGq(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op2_64, op1_64, diff_64; /* op2_64 is a register, i->rm_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -465,17 +467,17 @@ BX_CPU_C::CMP_EqGq(BxInstruction_t *i) void -BX_CPU_C::CMP_GqEq(BxInstruction_t *i) +BX_CPU_C::CMP_GqEq(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op1_64, op2_64, diff_64; /* op1_64 is a register, i->rm_addr is an index of a register */ - op1_64 = BX_READ_64BIT_REG(i->nnn); + op1_64 = BX_READ_64BIT_REG(i->nnn()); /* op2_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -489,14 +491,14 @@ BX_CPU_C::CMP_GqEq(BxInstruction_t *i) void -BX_CPU_C::CMP_RAXId(BxInstruction_t *i) +BX_CPU_C::CMP_RAXId(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op1_64, op2_64, diff_64; op1_64 = RAX; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); diff_64 = op1_64 - op2_64; @@ -506,7 +508,7 @@ BX_CPU_C::CMP_RAXId(BxInstruction_t *i) #ifdef ignore void -BX_CPU_C::CWDE64(BxInstruction_t *i) +BX_CPU_C::CWDE64(bxInstruction_c *i) { /* CBW: no flags are effected */ @@ -515,7 +517,7 @@ BX_CPU_C::CWDE64(BxInstruction_t *i) #endif void -BX_CPU_C::CDQE(BxInstruction_t *i) +BX_CPU_C::CDQE(bxInstruction_c *i) { /* CWDE: no flags are affected */ @@ -523,7 +525,7 @@ BX_CPU_C::CDQE(BxInstruction_t *i) } void -BX_CPU_C::CQO(BxInstruction_t *i) +BX_CPU_C::CQO(bxInstruction_c *i) { /* CQO: no flags are affected */ @@ -550,14 +552,14 @@ BX_CPU_C::CQO(BxInstruction_t *i) // {OF,B1} = CMPXCHG 16|64 void -BX_CPU_C::CMPXCHG_XBTS(BxInstruction_t *i) +BX_CPU_C::CMPXCHG_XBTS(bxInstruction_c *i) { BX_INFO(("CMPXCHG_XBTS:")); UndefinedOpcode(i); } void -BX_CPU_C::CMPXCHG_IBTS(BxInstruction_t *i) +BX_CPU_C::CMPXCHG_IBTS(bxInstruction_c *i) { BX_INFO(("CMPXCHG_IBTS:")); UndefinedOpcode(i); @@ -567,7 +569,7 @@ BX_CPU_C::CMPXCHG_IBTS(BxInstruction_t *i) void -BX_CPU_C::XADD_EqGq(BxInstruction_t *i) +BX_CPU_C::XADD_EqGq(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -580,11 +582,11 @@ BX_CPU_C::XADD_EqGq(BxInstruction_t *i) */ /* op2 is a register, i->rm_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -594,18 +596,18 @@ BX_CPU_C::XADD_EqGq(BxInstruction_t *i) sum_64 = op1_64 + op2_64; /* now write sum back to destination */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { // and write destination into source // Note: if both op1 & op2 are registers, the last one written // should be the sum, as op1 & op2 may be the same register. // For example: XADD AL, AL - BX_WRITE_64BIT_REG(i->nnn, op1_64); - BX_WRITE_64BIT_REG(i->rm, sum_64); + BX_WRITE_64BIT_REG(i->nnn(), op1_64); + BX_WRITE_64BIT_REG(i->rm(), sum_64); } else { write_RMW_virtual_qword(sum_64); /* and write destination into source */ - BX_WRITE_64BIT_REG(i->nnn, op1_64); + BX_WRITE_64BIT_REG(i->nnn(), op1_64); } @@ -618,16 +620,16 @@ BX_CPU_C::XADD_EqGq(BxInstruction_t *i) void -BX_CPU_C::ADD_EqId(BxInstruction_t *i) +BX_CPU_C::ADD_EqId(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op2_64, op1_64, sum_64; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -637,8 +639,8 @@ BX_CPU_C::ADD_EqId(BxInstruction_t *i) sum_64 = op1_64 + op2_64; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, sum_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), sum_64); } else { write_RMW_virtual_qword(sum_64); @@ -648,7 +650,7 @@ BX_CPU_C::ADD_EqId(BxInstruction_t *i) } void -BX_CPU_C::ADC_EqId(BxInstruction_t *i) +BX_CPU_C::ADC_EqId(bxInstruction_c *i) { Boolean temp_CF; @@ -657,11 +659,11 @@ BX_CPU_C::ADC_EqId(BxInstruction_t *i) /* for 64 bit operand size mode */ Bit64u op2_64, op1_64, sum_64; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -671,8 +673,8 @@ BX_CPU_C::ADC_EqId(BxInstruction_t *i) sum_64 = op1_64 + op2_64 + temp_CF; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, sum_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), sum_64); } else { write_RMW_virtual_qword(sum_64); @@ -684,16 +686,16 @@ BX_CPU_C::ADC_EqId(BxInstruction_t *i) void -BX_CPU_C::SUB_EqId(BxInstruction_t *i) +BX_CPU_C::SUB_EqId(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op2_64, op1_64, diff_64; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -703,8 +705,8 @@ BX_CPU_C::SUB_EqId(BxInstruction_t *i) diff_64 = op1_64 - op2_64; /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, diff_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), diff_64); } else { write_RMW_virtual_qword(diff_64); @@ -714,16 +716,16 @@ BX_CPU_C::SUB_EqId(BxInstruction_t *i) } void -BX_CPU_C::CMP_EqId(BxInstruction_t *i) +BX_CPU_C::CMP_EqId(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op2_64, op1_64, diff_64; - op2_64 = i->Id; + op2_64 = i->Id(); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -739,14 +741,14 @@ BX_CPU_C::CMP_EqId(BxInstruction_t *i) void -BX_CPU_C::NEG_Eq(BxInstruction_t *i) +BX_CPU_C::NEG_Eq(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op1_64, diff_64; /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -756,8 +758,8 @@ BX_CPU_C::NEG_Eq(BxInstruction_t *i) diff_64 = 0 - op1_64; /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, diff_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), diff_64); } else { write_RMW_virtual_qword(diff_64); @@ -768,13 +770,13 @@ BX_CPU_C::NEG_Eq(BxInstruction_t *i) void -BX_CPU_C::INC_Eq(BxInstruction_t *i) +BX_CPU_C::INC_Eq(bxInstruction_c *i) { Bit64u op1_64; /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -784,8 +786,8 @@ BX_CPU_C::INC_Eq(BxInstruction_t *i) op1_64++; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, op1_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), op1_64); } else { write_RMW_virtual_qword(op1_64); @@ -796,13 +798,13 @@ BX_CPU_C::INC_Eq(BxInstruction_t *i) void -BX_CPU_C::DEC_Eq(BxInstruction_t *i) +BX_CPU_C::DEC_Eq(bxInstruction_c *i) { Bit64u op1_64; /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -812,8 +814,8 @@ BX_CPU_C::DEC_Eq(BxInstruction_t *i) op1_64--; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, op1_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), op1_64); } else { write_RMW_virtual_qword(op1_64); @@ -824,15 +826,15 @@ BX_CPU_C::DEC_Eq(BxInstruction_t *i) void -BX_CPU_C::CMPXCHG_EqGq(BxInstruction_t *i) +BX_CPU_C::CMPXCHG_EqGq(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) Bit64u op2_64, op1_64, diff_64; /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -847,10 +849,10 @@ BX_CPU_C::CMPXCHG_EqGq(BxInstruction_t *i) // ZF = 1 set_ZF(1); // dest <-- src - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, op2_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), op2_64); } else { write_RMW_virtual_qword(op2_64); diff --git a/bochs/cpu/arith8.cc b/bochs/cpu/arith8.cc index f0b9f49ca..7be09e054 100644 --- a/bochs/cpu/arith8.cc +++ b/bochs/cpu/arith8.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: arith8.cc,v 1.8 2002-09-13 17:28:14 kevinlawton Exp $ +// $Id: arith8.cc,v 1.9 2002-09-17 22:50:51 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -37,16 +37,16 @@ void -BX_CPU_C::ADD_EbGb(BxInstruction_t *i) +BX_CPU_C::ADD_EbGb(bxInstruction_c *i) { Bit8u op2, op1, sum; /* op2 is a register, i->rm_addr is an index of a register */ - op2 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { read_RMW_virtual_byte(i->seg, i->rm_addr, &op1); @@ -55,8 +55,8 @@ BX_CPU_C::ADD_EbGb(BxInstruction_t *i) sum = op1 + op2; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, sum); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, sum); } else { Write_RMW_virtual_byte(sum); @@ -68,17 +68,17 @@ BX_CPU_C::ADD_EbGb(BxInstruction_t *i) void -BX_CPU_C::ADD_GbEb(BxInstruction_t *i) +BX_CPU_C::ADD_GbEb(bxInstruction_c *i) { Bit8u op1, op2, sum; /* op1 is a register, i->rm_addr is an index of a register */ - op1 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op1 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -88,21 +88,21 @@ BX_CPU_C::ADD_GbEb(BxInstruction_t *i) sum = op1 + op2; /* now write sum back to destination, which is a register */ - BX_WRITE_8BIT_REGx(i->nnn, i->extend8bit, sum); + BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bit, sum); SET_FLAGS_OSZAPC_8(op1, op2, sum, BX_INSTR_ADD8); } void -BX_CPU_C::ADD_ALIb(BxInstruction_t *i) +BX_CPU_C::ADD_ALIb(bxInstruction_c *i) { Bit8u op1, op2, sum; op1 = AL; - op2 = i->Ib; + op2 = i->Ib(); sum = op1 + op2; @@ -114,7 +114,7 @@ BX_CPU_C::ADD_ALIb(BxInstruction_t *i) void -BX_CPU_C::ADC_EbGb(BxInstruction_t *i) +BX_CPU_C::ADC_EbGb(bxInstruction_c *i) { Bit8u op2, op1, sum; Boolean temp_CF; @@ -123,11 +123,11 @@ BX_CPU_C::ADC_EbGb(BxInstruction_t *i) /* op2 is a register, i->rm_addr is an index of a register */ - op2 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -138,8 +138,8 @@ BX_CPU_C::ADC_EbGb(BxInstruction_t *i) /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, sum); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, sum); } else { Write_RMW_virtual_byte(sum); @@ -150,7 +150,7 @@ BX_CPU_C::ADC_EbGb(BxInstruction_t *i) void -BX_CPU_C::ADC_GbEb(BxInstruction_t *i) +BX_CPU_C::ADC_GbEb(bxInstruction_c *i) { Bit8u op1, op2, sum; Boolean temp_CF; @@ -159,11 +159,11 @@ BX_CPU_C::ADC_GbEb(BxInstruction_t *i) /* op1 is a register, i->rm_addr is an index of a register */ - op1 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op1 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -176,12 +176,12 @@ BX_CPU_C::ADC_GbEb(BxInstruction_t *i) temp_CF); /* now write sum back to destination, which is a register */ - BX_WRITE_8BIT_REGx(i->nnn, i->extend8bit, sum); + BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bit, sum); } void -BX_CPU_C::ADC_ALIb(BxInstruction_t *i) +BX_CPU_C::ADC_ALIb(bxInstruction_c *i) { Bit8u op1, op2, sum; Boolean temp_CF; @@ -191,7 +191,7 @@ BX_CPU_C::ADC_ALIb(BxInstruction_t *i) op1 = AL; - op2 = i->Ib; + op2 = i->Ib(); sum = op1 + op2 + temp_CF; @@ -204,7 +204,7 @@ BX_CPU_C::ADC_ALIb(BxInstruction_t *i) void -BX_CPU_C::SBB_EbGb(BxInstruction_t *i) +BX_CPU_C::SBB_EbGb(bxInstruction_c *i) { Bit8u op2_8, op1_8, diff_8; Boolean temp_CF; @@ -213,11 +213,11 @@ BX_CPU_C::SBB_EbGb(BxInstruction_t *i) /* op2 is a register, i->rm_addr is an index of a register */ - op2_8 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2_8 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op1_8 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -227,8 +227,8 @@ BX_CPU_C::SBB_EbGb(BxInstruction_t *i) diff_8 = op1_8 - (op2_8 + temp_CF); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, diff_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, diff_8); } else { Write_RMW_virtual_byte(diff_8); @@ -240,7 +240,7 @@ BX_CPU_C::SBB_EbGb(BxInstruction_t *i) void -BX_CPU_C::SBB_GbEb(BxInstruction_t *i) +BX_CPU_C::SBB_GbEb(bxInstruction_c *i) { Bit8u op1_8, op2_8, diff_8; Boolean temp_CF; @@ -249,11 +249,11 @@ BX_CPU_C::SBB_GbEb(BxInstruction_t *i) /* op1 is a register, i->rm_addr is an index of a register */ - op1_8 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op1_8 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -263,7 +263,7 @@ BX_CPU_C::SBB_GbEb(BxInstruction_t *i) diff_8 = op1_8 - (op2_8 + temp_CF); /* now write diff back to destination, which is a register */ - BX_WRITE_8BIT_REGx(i->nnn, i->extend8bit, diff_8); + BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bit, diff_8); SET_FLAGS_OSZAPC_8_CF(op1_8, op2_8, diff_8, BX_INSTR_SBB8, temp_CF); @@ -271,7 +271,7 @@ BX_CPU_C::SBB_GbEb(BxInstruction_t *i) void -BX_CPU_C::SBB_ALIb(BxInstruction_t *i) +BX_CPU_C::SBB_ALIb(bxInstruction_c *i) { Bit8u op1_8, op2_8, diff_8; Boolean temp_CF; @@ -281,7 +281,7 @@ BX_CPU_C::SBB_ALIb(BxInstruction_t *i) op1_8 = AL; - op2_8 = i->Ib; + op2_8 = i->Ib(); diff_8 = op1_8 - (op2_8 + temp_CF); @@ -294,18 +294,18 @@ BX_CPU_C::SBB_ALIb(BxInstruction_t *i) void -BX_CPU_C::SBB_EbIb(BxInstruction_t *i) +BX_CPU_C::SBB_EbIb(bxInstruction_c *i) { Bit8u op2_8, op1_8, diff_8; Boolean temp_CF; temp_CF = get_CF(); - op2_8 = i->Ib; + op2_8 = i->Ib(); /* op1_8 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -315,8 +315,8 @@ BX_CPU_C::SBB_EbIb(BxInstruction_t *i) diff_8 = op1_8 - (op2_8 + temp_CF); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, diff_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, diff_8); } else { Write_RMW_virtual_byte(diff_8); @@ -329,17 +329,17 @@ BX_CPU_C::SBB_EbIb(BxInstruction_t *i) void -BX_CPU_C::SUB_EbGb(BxInstruction_t *i) +BX_CPU_C::SUB_EbGb(bxInstruction_c *i) { Bit8u op2_8, op1_8, diff_8; /* op2 is a register, i->rm_addr is an index of a register */ - op2_8 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2_8 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op1_8 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -349,8 +349,8 @@ BX_CPU_C::SUB_EbGb(BxInstruction_t *i) diff_8 = op1_8 - op2_8; /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, diff_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, diff_8); } else { Write_RMW_virtual_byte(diff_8); @@ -361,17 +361,17 @@ BX_CPU_C::SUB_EbGb(BxInstruction_t *i) void -BX_CPU_C::SUB_GbEb(BxInstruction_t *i) +BX_CPU_C::SUB_GbEb(bxInstruction_c *i) { Bit8u op1_8, op2_8, diff_8; /* op1 is a register, i->rm_addr is an index of a register */ - op1_8 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op1_8 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -381,20 +381,20 @@ BX_CPU_C::SUB_GbEb(BxInstruction_t *i) diff_8 = op1_8 - op2_8; /* now write diff back to destination, which is a register */ - BX_WRITE_8BIT_REGx(i->nnn, i->extend8bit, diff_8); + BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bit, diff_8); SET_FLAGS_OSZAPC_8(op1_8, op2_8, diff_8, BX_INSTR_SUB8); } void -BX_CPU_C::SUB_ALIb(BxInstruction_t *i) +BX_CPU_C::SUB_ALIb(bxInstruction_c *i) { Bit8u op1_8, op2_8, diff_8; op1_8 = AL; - op2_8 = i->Ib; + op2_8 = i->Ib(); diff_8 = op1_8 - op2_8; @@ -407,17 +407,17 @@ BX_CPU_C::SUB_ALIb(BxInstruction_t *i) void -BX_CPU_C::CMP_EbGb(BxInstruction_t *i) +BX_CPU_C::CMP_EbGb(bxInstruction_c *i) { Bit8u op2_8, op1_8, diff_8; /* op2 is a register, i->rm_addr is an index of a register */ - op2_8 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2_8 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op1_8 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -431,16 +431,16 @@ BX_CPU_C::CMP_EbGb(BxInstruction_t *i) void -BX_CPU_C::CMP_GbEb(BxInstruction_t *i) +BX_CPU_C::CMP_GbEb(bxInstruction_c *i) { Bit8u op1_8, op2_8, diff_8; /* op1 is a register, i->rm_addr is an index of a register */ - op1_8 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op1_8 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -455,14 +455,14 @@ BX_CPU_C::CMP_GbEb(BxInstruction_t *i) void -BX_CPU_C::CMP_ALIb(BxInstruction_t *i) +BX_CPU_C::CMP_ALIb(bxInstruction_c *i) { Bit8u op1_8, op2_8, diff_8; op1_8 = AL; - op2_8 = i->Ib; + op2_8 = i->Ib(); diff_8 = op1_8 - op2_8; @@ -471,7 +471,7 @@ BX_CPU_C::CMP_ALIb(BxInstruction_t *i) void -BX_CPU_C::XADD_EbGb(BxInstruction_t *i) +BX_CPU_C::XADD_EbGb(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -484,11 +484,11 @@ BX_CPU_C::XADD_EbGb(BxInstruction_t *i) */ /* op2 is a register, i->rm_addr is an index of a register */ - op2 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -498,18 +498,18 @@ BX_CPU_C::XADD_EbGb(BxInstruction_t *i) sum = op1 + op2; /* now write sum back to destination */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { // and write destination into source // Note: if both op1 & op2 are registers, the last one written // should be the sum, as op1 & op2 may be the same register. // For example: XADD AL, AL - BX_WRITE_8BIT_REGx(i->nnn, i->extend8bit, op1); - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, sum); + BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bit, op1); + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, sum); } else { Write_RMW_virtual_byte(sum); /* and write destination into source */ - BX_WRITE_8BIT_REGx(i->nnn, i->extend8bit, op1); + BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bit, op1); } @@ -521,16 +521,16 @@ BX_CPU_C::XADD_EbGb(BxInstruction_t *i) void -BX_CPU_C::ADD_EbIb(BxInstruction_t *i) +BX_CPU_C::ADD_EbIb(bxInstruction_c *i) { Bit8u op2, op1, sum; - op2 = i->Ib; + op2 = i->Ib(); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -540,8 +540,8 @@ BX_CPU_C::ADD_EbIb(BxInstruction_t *i) sum = op1 + op2; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, sum); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, sum); } else { Write_RMW_virtual_byte(sum); @@ -551,18 +551,18 @@ BX_CPU_C::ADD_EbIb(BxInstruction_t *i) } void -BX_CPU_C::ADC_EbIb(BxInstruction_t *i) +BX_CPU_C::ADC_EbIb(bxInstruction_c *i) { Bit8u op2, op1, sum; Boolean temp_CF; temp_CF = get_CF(); - op2 = i->Ib; + op2 = i->Ib(); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -572,8 +572,8 @@ BX_CPU_C::ADC_EbIb(BxInstruction_t *i) sum = op1 + op2 + temp_CF; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, sum); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, sum); } else { Write_RMW_virtual_byte(sum); @@ -585,16 +585,16 @@ BX_CPU_C::ADC_EbIb(BxInstruction_t *i) void -BX_CPU_C::SUB_EbIb(BxInstruction_t *i) +BX_CPU_C::SUB_EbIb(bxInstruction_c *i) { Bit8u op2_8, op1_8, diff_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); /* op1_8 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -604,8 +604,8 @@ BX_CPU_C::SUB_EbIb(BxInstruction_t *i) diff_8 = op1_8 - op2_8; /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, diff_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, diff_8); } else { Write_RMW_virtual_byte(diff_8); @@ -615,15 +615,15 @@ BX_CPU_C::SUB_EbIb(BxInstruction_t *i) } void -BX_CPU_C::CMP_EbIb(BxInstruction_t *i) +BX_CPU_C::CMP_EbIb(bxInstruction_c *i) { Bit8u op2_8, op1_8, diff_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); /* op1_8 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -637,13 +637,13 @@ BX_CPU_C::CMP_EbIb(BxInstruction_t *i) void -BX_CPU_C::NEG_Eb(BxInstruction_t *i) +BX_CPU_C::NEG_Eb(bxInstruction_c *i) { Bit8u op1_8, diff_8; /* op1_8 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -653,8 +653,8 @@ BX_CPU_C::NEG_Eb(BxInstruction_t *i) diff_8 = 0 - op1_8; /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, diff_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, diff_8); } else { Write_RMW_virtual_byte(diff_8); @@ -665,13 +665,13 @@ BX_CPU_C::NEG_Eb(BxInstruction_t *i) void -BX_CPU_C::INC_Eb(BxInstruction_t *i) +BX_CPU_C::INC_Eb(bxInstruction_c *i) { Bit8u op1; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -682,8 +682,8 @@ BX_CPU_C::INC_Eb(BxInstruction_t *i) op1++; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, op1); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, op1); } else { Write_RMW_virtual_byte(op1); @@ -694,13 +694,13 @@ BX_CPU_C::INC_Eb(BxInstruction_t *i) void -BX_CPU_C::DEC_Eb(BxInstruction_t *i) +BX_CPU_C::DEC_Eb(bxInstruction_c *i) { Bit8u op1_8; /* op1_8 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -710,8 +710,8 @@ BX_CPU_C::DEC_Eb(BxInstruction_t *i) op1_8--; /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, op1_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, op1_8); } else { Write_RMW_virtual_byte(op1_8); @@ -722,15 +722,15 @@ BX_CPU_C::DEC_Eb(BxInstruction_t *i) void -BX_CPU_C::CMPXCHG_EbGb(BxInstruction_t *i) +BX_CPU_C::CMPXCHG_EbGb(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) Bit8u op2_8, op1_8, diff_8; /* op1_8 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -745,10 +745,10 @@ BX_CPU_C::CMPXCHG_EbGb(BxInstruction_t *i) // ZF = 1 set_ZF(1); // dest <-- src - op2_8 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2_8 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, op2_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, op2_8); } else { Write_RMW_virtual_byte(op2_8); diff --git a/bochs/cpu/bcd.cc b/bochs/cpu/bcd.cc index 8ea1b2938..808bcdc75 100644 --- a/bochs/cpu/bcd.cc +++ b/bochs/cpu/bcd.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: bcd.cc,v 1.6 2002-07-06 11:02:35 vruppert Exp $ +// $Id: bcd.cc,v 1.7 2002-09-17 22:50:51 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2002 MandrakeSoft S.A. @@ -36,7 +36,7 @@ void -BX_CPU_C::DAS(BxInstruction_t *) +BX_CPU_C::DAS(bxInstruction_c *) { Bit8u tmpCF, tmpAL; @@ -72,7 +72,7 @@ BX_CPU_C::DAS(BxInstruction_t *) } void -BX_CPU_C::AAA(BxInstruction_t *) +BX_CPU_C::AAA(bxInstruction_c *) { Bit8u ALcarry; @@ -93,7 +93,7 @@ BX_CPU_C::AAA(BxInstruction_t *) } void -BX_CPU_C::AAS(BxInstruction_t *) +BX_CPU_C::AAS(bxInstruction_c *) { Bit8u ALborrow; @@ -115,11 +115,11 @@ BX_CPU_C::AAS(BxInstruction_t *) } void -BX_CPU_C::AAM(BxInstruction_t *i) +BX_CPU_C::AAM(bxInstruction_c *i) { Bit8u al, imm8; - imm8 = i->Ib; + imm8 = i->Ib(); if (imm8 == 0) { exception(BX_DE_EXCEPTION, 0, 0); @@ -139,12 +139,12 @@ BX_CPU_C::AAM(BxInstruction_t *i) } void -BX_CPU_C::AAD(BxInstruction_t *i) +BX_CPU_C::AAD(bxInstruction_c *i) { Bit8u al, imm8; Bit16u ax1, ax2; - imm8 = i->Ib; + imm8 = i->Ib(); ax1 = AH * imm8; ax2 = ax1 + AL; @@ -163,7 +163,7 @@ BX_CPU_C::AAD(BxInstruction_t *i) } void -BX_CPU_C::DAA(BxInstruction_t *) +BX_CPU_C::DAA(bxInstruction_c *) { Bit8u al; diff --git a/bochs/cpu/bit.cc b/bochs/cpu/bit.cc index 5eb740509..68b0f42d9 100644 --- a/bochs/cpu/bit.cc +++ b/bochs/cpu/bit.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: bit.cc,v 1.8 2002-09-15 03:38:52 kevinlawton Exp $ +// $Id: bit.cc,v 1.9 2002-09-17 22:50:51 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -48,7 +48,7 @@ void -BX_CPU_C::SETO_Eb(BxInstruction_t *i) +BX_CPU_C::SETO_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETO: not available on < 386")); @@ -62,8 +62,8 @@ BX_CPU_C::SETO_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -72,7 +72,7 @@ BX_CPU_C::SETO_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETNO_Eb(BxInstruction_t *i) +BX_CPU_C::SETNO_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETNO: not available on < 386")); @@ -86,8 +86,8 @@ BX_CPU_C::SETNO_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -96,7 +96,7 @@ BX_CPU_C::SETNO_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETB_Eb(BxInstruction_t *i) +BX_CPU_C::SETB_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETB: not available on < 386")); @@ -110,8 +110,8 @@ BX_CPU_C::SETB_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -120,7 +120,7 @@ BX_CPU_C::SETB_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETNB_Eb(BxInstruction_t *i) +BX_CPU_C::SETNB_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETNB: not available on < 386")); @@ -134,8 +134,8 @@ BX_CPU_C::SETNB_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -144,7 +144,7 @@ BX_CPU_C::SETNB_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETZ_Eb(BxInstruction_t *i) +BX_CPU_C::SETZ_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETZ: not available on < 386")); @@ -158,8 +158,8 @@ BX_CPU_C::SETZ_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -168,7 +168,7 @@ BX_CPU_C::SETZ_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETNZ_Eb(BxInstruction_t *i) +BX_CPU_C::SETNZ_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETNZ: not available on < 386")); @@ -182,8 +182,8 @@ BX_CPU_C::SETNZ_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -192,7 +192,7 @@ BX_CPU_C::SETNZ_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETBE_Eb(BxInstruction_t *i) +BX_CPU_C::SETBE_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETBE: not available on < 386")); @@ -206,8 +206,8 @@ BX_CPU_C::SETBE_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -216,7 +216,7 @@ BX_CPU_C::SETBE_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETNBE_Eb(BxInstruction_t *i) +BX_CPU_C::SETNBE_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETNBE: not available on < 386")); @@ -230,8 +230,8 @@ BX_CPU_C::SETNBE_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -240,7 +240,7 @@ BX_CPU_C::SETNBE_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETS_Eb(BxInstruction_t *i) +BX_CPU_C::SETS_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETS: not available on < 386")); @@ -254,8 +254,8 @@ BX_CPU_C::SETS_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -264,7 +264,7 @@ BX_CPU_C::SETS_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETNS_Eb(BxInstruction_t *i) +BX_CPU_C::SETNS_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETNL: not available on < 386")); @@ -278,8 +278,8 @@ BX_CPU_C::SETNS_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -288,7 +288,7 @@ BX_CPU_C::SETNS_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETP_Eb(BxInstruction_t *i) +BX_CPU_C::SETP_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETP: not available on < 386")); @@ -302,8 +302,8 @@ BX_CPU_C::SETP_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -312,7 +312,7 @@ BX_CPU_C::SETP_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETNP_Eb(BxInstruction_t *i) +BX_CPU_C::SETNP_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETNP: not available on < 386")); @@ -326,8 +326,8 @@ BX_CPU_C::SETNP_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -336,7 +336,7 @@ BX_CPU_C::SETNP_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETL_Eb(BxInstruction_t *i) +BX_CPU_C::SETL_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETL: not available on < 386")); @@ -350,8 +350,8 @@ BX_CPU_C::SETL_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -360,7 +360,7 @@ BX_CPU_C::SETL_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETNL_Eb(BxInstruction_t *i) +BX_CPU_C::SETNL_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETNL: not available on < 386")); @@ -374,8 +374,8 @@ BX_CPU_C::SETNL_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -384,7 +384,7 @@ BX_CPU_C::SETNL_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETLE_Eb(BxInstruction_t *i) +BX_CPU_C::SETLE_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETLE: not available on < 386")); @@ -398,8 +398,8 @@ BX_CPU_C::SETLE_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -408,7 +408,7 @@ BX_CPU_C::SETLE_Eb(BxInstruction_t *i) } void -BX_CPU_C::SETNLE_Eb(BxInstruction_t *i) +BX_CPU_C::SETNLE_Eb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("SETNLE: not available on < 386")); @@ -422,8 +422,8 @@ BX_CPU_C::SETNLE_Eb(BxInstruction_t *i) result_8 = 0; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { write_virtual_byte(i->seg, i->rm_addr, &result_8); @@ -433,7 +433,7 @@ BX_CPU_C::SETNLE_Eb(BxInstruction_t *i) void -BX_CPU_C::BSF_GvEv(BxInstruction_t *i) +BX_CPU_C::BSF_GvEv(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("BSF_GvEv(): not supported on < 386")); @@ -446,8 +446,8 @@ BX_CPU_C::BSF_GvEv(BxInstruction_t *i) Bit64u op1_64, op2_64; /* op2_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -468,7 +468,7 @@ BX_CPU_C::BSF_GvEv(BxInstruction_t *i) set_ZF(0); /* now write result back to destination */ - BX_WRITE_64BIT_REG(i->nnn, op1_64); + BX_WRITE_64BIT_REG(i->nnn(), op1_64); } else #endif // #if BX_SUPPORT_X86_64 @@ -477,8 +477,8 @@ BX_CPU_C::BSF_GvEv(BxInstruction_t *i) Bit32u op1_32, op2_32; /* op2_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -499,14 +499,14 @@ BX_CPU_C::BSF_GvEv(BxInstruction_t *i) set_ZF(0); /* now write result back to destination */ - BX_WRITE_32BIT_REGZ(i->nnn, op1_32); + BX_WRITE_32BIT_REGZ(i->nnn(), op1_32); } else { /* 16 bit operand size mode */ Bit16u op1_16, op2_16; /* op2_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -527,13 +527,13 @@ BX_CPU_C::BSF_GvEv(BxInstruction_t *i) set_ZF(0); /* now write result back to destination */ - BX_WRITE_16BIT_REG(i->nnn, op1_16); + BX_WRITE_16BIT_REG(i->nnn(), op1_16); } #endif } void -BX_CPU_C::BSR_GvEv(BxInstruction_t *i) +BX_CPU_C::BSR_GvEv(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("BSR_GvEv(): not supported on < 386")); @@ -546,8 +546,8 @@ BX_CPU_C::BSR_GvEv(BxInstruction_t *i) Bit64u op1_64, op2_64; /* op2_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -568,7 +568,7 @@ BX_CPU_C::BSR_GvEv(BxInstruction_t *i) set_ZF(0); /* now write result back to destination */ - BX_WRITE_64BIT_REG(i->nnn, op1_64); + BX_WRITE_64BIT_REG(i->nnn(), op1_64); } else #endif // #if BX_SUPPORT_X86_64 @@ -577,8 +577,8 @@ BX_CPU_C::BSR_GvEv(BxInstruction_t *i) Bit32u op1_32, op2_32; /* op2_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -599,14 +599,14 @@ BX_CPU_C::BSR_GvEv(BxInstruction_t *i) set_ZF(0); /* now write result back to destination */ - BX_WRITE_32BIT_REGZ(i->nnn, op1_32); + BX_WRITE_32BIT_REGZ(i->nnn(), op1_32); } else { /* 16 bit operand size mode */ Bit16u op1_16, op2_16; /* op2_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -627,14 +627,14 @@ BX_CPU_C::BSR_GvEv(BxInstruction_t *i) set_ZF(0); /* now write result back to destination */ - BX_WRITE_16BIT_REG(i->nnn, op1_16); + BX_WRITE_16BIT_REG(i->nnn(), op1_16); } #endif } void -BX_CPU_C::BSWAP_EAX(BxInstruction_t *i) +BX_CPU_C::BSWAP_EAX(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -653,7 +653,7 @@ BX_CPU_C::BSWAP_EAX(BxInstruction_t *i) } void -BX_CPU_C::BSWAP_ECX(BxInstruction_t *i) +BX_CPU_C::BSWAP_ECX(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -671,7 +671,7 @@ BX_CPU_C::BSWAP_ECX(BxInstruction_t *i) #endif } void -BX_CPU_C::BSWAP_EDX(BxInstruction_t *i) +BX_CPU_C::BSWAP_EDX(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -689,7 +689,7 @@ BX_CPU_C::BSWAP_EDX(BxInstruction_t *i) #endif } void -BX_CPU_C::BSWAP_EBX(BxInstruction_t *i) +BX_CPU_C::BSWAP_EBX(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -707,7 +707,7 @@ BX_CPU_C::BSWAP_EBX(BxInstruction_t *i) #endif } void -BX_CPU_C::BSWAP_ESP(BxInstruction_t *i) +BX_CPU_C::BSWAP_ESP(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -725,7 +725,7 @@ BX_CPU_C::BSWAP_ESP(BxInstruction_t *i) #endif } void -BX_CPU_C::BSWAP_EBP(BxInstruction_t *i) +BX_CPU_C::BSWAP_EBP(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -743,7 +743,7 @@ BX_CPU_C::BSWAP_EBP(BxInstruction_t *i) #endif } void -BX_CPU_C::BSWAP_ESI(BxInstruction_t *i) +BX_CPU_C::BSWAP_ESI(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -761,7 +761,7 @@ BX_CPU_C::BSWAP_ESI(BxInstruction_t *i) #endif } void -BX_CPU_C::BSWAP_EDI(BxInstruction_t *i) +BX_CPU_C::BSWAP_EDI(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -782,7 +782,7 @@ BX_CPU_C::BSWAP_EDI(BxInstruction_t *i) #if BX_SUPPORT_X86_64 void -BX_CPU_C::BSWAP_RAX(BxInstruction_t *i) +BX_CPU_C::BSWAP_RAX(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -805,7 +805,7 @@ BX_CPU_C::BSWAP_RAX(BxInstruction_t *i) } void -BX_CPU_C::BSWAP_RCX(BxInstruction_t *i) +BX_CPU_C::BSWAP_RCX(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -827,7 +827,7 @@ BX_CPU_C::BSWAP_RCX(BxInstruction_t *i) #endif } void -BX_CPU_C::BSWAP_RDX(BxInstruction_t *i) +BX_CPU_C::BSWAP_RDX(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -849,7 +849,7 @@ BX_CPU_C::BSWAP_RDX(BxInstruction_t *i) #endif } void -BX_CPU_C::BSWAP_RBX(BxInstruction_t *i) +BX_CPU_C::BSWAP_RBX(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -871,7 +871,7 @@ BX_CPU_C::BSWAP_RBX(BxInstruction_t *i) #endif } void -BX_CPU_C::BSWAP_RSP(BxInstruction_t *i) +BX_CPU_C::BSWAP_RSP(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -893,7 +893,7 @@ BX_CPU_C::BSWAP_RSP(BxInstruction_t *i) #endif } void -BX_CPU_C::BSWAP_RBP(BxInstruction_t *i) +BX_CPU_C::BSWAP_RBP(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -915,7 +915,7 @@ BX_CPU_C::BSWAP_RBP(BxInstruction_t *i) #endif } void -BX_CPU_C::BSWAP_RSI(BxInstruction_t *i) +BX_CPU_C::BSWAP_RSI(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -937,7 +937,7 @@ BX_CPU_C::BSWAP_RSI(BxInstruction_t *i) #endif } void -BX_CPU_C::BSWAP_RDI(BxInstruction_t *i) +BX_CPU_C::BSWAP_RDI(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4) @@ -962,7 +962,7 @@ BX_CPU_C::BSWAP_RDI(BxInstruction_t *i) void -BX_CPU_C::BT_EvGv(BxInstruction_t *i) +BX_CPU_C::BT_EvGv(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("BT_EvGv: not available on <386")); @@ -977,11 +977,11 @@ BX_CPU_C::BT_EvGv(BxInstruction_t *i) Bit64u index; /* op2_64 is a register, op2_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); op2_64 &= 0x3f; set_CF((op1_64 >> op2_64) & 0x01); return; @@ -1004,11 +1004,11 @@ BX_CPU_C::BT_EvGv(BxInstruction_t *i) Bit32s displacement32; /* op2_32 is a register, op2_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); op2_32 &= 0x1f; set_CF((op1_32 >> op2_32) & 0x01); return; @@ -1028,11 +1028,11 @@ BX_CPU_C::BT_EvGv(BxInstruction_t *i) Bit32s displacement32; /* op2_16 is a register, op2_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); op2_16 &= 0x0f; set_CF((op1_16 >> op2_16) & 0x01); return; @@ -1051,7 +1051,7 @@ BX_CPU_C::BT_EvGv(BxInstruction_t *i) } void -BX_CPU_C::BTS_EvGv(BxInstruction_t *i) +BX_CPU_C::BTS_EvGv(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("BTS_EvGv: not available on <386")); @@ -1066,17 +1066,17 @@ BX_CPU_C::BTS_EvGv(BxInstruction_t *i) Bit64u bit_i; /* op2_64 is a register, op2_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); op2_64 &= 0x3f; set_CF((op1_64 >> op2_64) & 0x01); op1_64 |= (((Bit64u) 1) << op2_64); /* now write diff back to destination */ - BX_WRITE_64BIT_REG(i->rm, op1_64); + BX_WRITE_64BIT_REG(i->rm(), op1_64); return; } @@ -1102,17 +1102,17 @@ BX_CPU_C::BTS_EvGv(BxInstruction_t *i) Bit32s displacement32; /* op2_32 is a register, op2_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); op2_32 &= 0x1f; set_CF((op1_32 >> op2_32) & 0x01); op1_32 |= (((Bit32u) 1) << op2_32); /* now write diff back to destination */ - BX_WRITE_32BIT_REGZ(i->rm, op1_32); + BX_WRITE_32BIT_REGZ(i->rm(), op1_32); return; } @@ -1135,17 +1135,17 @@ BX_CPU_C::BTS_EvGv(BxInstruction_t *i) Bit32s displacement32; /* op2_16 is a register, op2_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); op2_16 &= 0x0f; set_CF((op1_16 >> op2_16) & 0x01); op1_16 |= (((Bit16u) 1) << op2_16); /* now write diff back to destination */ - BX_WRITE_16BIT_REG(i->rm, op1_16); + BX_WRITE_16BIT_REG(i->rm(), op1_16); return; } @@ -1167,7 +1167,7 @@ BX_CPU_C::BTS_EvGv(BxInstruction_t *i) } void -BX_CPU_C::BTR_EvGv(BxInstruction_t *i) +BX_CPU_C::BTR_EvGv(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("BTR_EvGv: not available on <386")); @@ -1183,17 +1183,17 @@ BX_CPU_C::BTR_EvGv(BxInstruction_t *i) Bit64u temp_cf; /* op2_64 is a register, op2_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); op2_64 &= 0x3f; set_CF((op1_64 >> op2_64) & 0x01); op1_64 &= ~(((Bit64u) 1) << op2_64); /* now write diff back to destination */ - BX_WRITE_64BIT_REG(i->rm, op1_64); + BX_WRITE_64BIT_REG(i->rm(), op1_64); return; } @@ -1220,17 +1220,17 @@ BX_CPU_C::BTR_EvGv(BxInstruction_t *i) Bit32s displacement32; /* op2_32 is a register, op2_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); op2_32 &= 0x1f; set_CF((op1_32 >> op2_32) & 0x01); op1_32 &= ~(((Bit32u) 1) << op2_32); /* now write diff back to destination */ - BX_WRITE_32BIT_REGZ(i->rm, op1_32); + BX_WRITE_32BIT_REGZ(i->rm(), op1_32); return; } @@ -1254,17 +1254,17 @@ BX_CPU_C::BTR_EvGv(BxInstruction_t *i) Bit32s displacement32; /* op2_16 is a register, op2_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); op2_16 &= 0x0f; set_CF((op1_16 >> op2_16) & 0x01); op1_16 &= ~(((Bit16u) 1) << op2_16); /* now write diff back to destination */ - BX_WRITE_16BIT_REG(i->rm, op1_16); + BX_WRITE_16BIT_REG(i->rm(), op1_16); return; } @@ -1287,7 +1287,7 @@ BX_CPU_C::BTR_EvGv(BxInstruction_t *i) } void -BX_CPU_C::BTC_EvGv(BxInstruction_t *i) +BX_CPU_C::BTC_EvGv(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("BTC_EvGv: not available on <386")); @@ -1301,12 +1301,12 @@ BX_CPU_C::BTC_EvGv(BxInstruction_t *i) Bit64s displacement64; Bit64u temp_CF, index; - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); index = op2_64 & 0x3f; /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); op1_addr = 0; // keep compiler happy } else { @@ -1325,8 +1325,8 @@ BX_CPU_C::BTC_EvGv(BxInstruction_t *i) //op1_64 ^= (((Bit64u) 1) << index); /* toggle bit wrong??? */ /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, op1_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), op1_64); } else { Write_RMW_virtual_qword(op1_64); @@ -1340,12 +1340,12 @@ BX_CPU_C::BTC_EvGv(BxInstruction_t *i) Bit32u op1_32, op2_32, index_32, temp_CF; Bit32s displacement32; - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); index_32 = op2_32 & 0x1f; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); op1_addr = 0; // keep compiler happy } else { @@ -1359,8 +1359,8 @@ BX_CPU_C::BTC_EvGv(BxInstruction_t *i) op1_32 |= (((Bit32u) !temp_CF) << index_32); /* set to complement */ /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, op1_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), op1_32); } else { Write_RMW_virtual_dword(op1_32); @@ -1371,12 +1371,12 @@ BX_CPU_C::BTC_EvGv(BxInstruction_t *i) Bit16u op1_16, op2_16, index_16, temp_CF; Bit16s displacement16; - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); index_16 = op2_16 & 0x0f; /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); op1_addr = 0; // keep compiler happy } else { @@ -1390,8 +1390,8 @@ BX_CPU_C::BTC_EvGv(BxInstruction_t *i) op1_16 |= (((Bit16u) !temp_CF) << index_16); /* set to complement */ /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, op1_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), op1_16); } else { Write_RMW_virtual_word(op1_16); @@ -1402,7 +1402,7 @@ BX_CPU_C::BTC_EvGv(BxInstruction_t *i) } void -BX_CPU_C::BT_EvIb(BxInstruction_t *i) +BX_CPU_C::BT_EvIb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("BT_EvIb: not available on <386")); @@ -1414,12 +1414,12 @@ BX_CPU_C::BT_EvIb(BxInstruction_t *i) Bit64u op1_64; Bit8u op2_8; - op2_8 = i->Ib & 0x3f; + op2_8 = i->Ib() & 0x3f; op2_8 %= 64; /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1435,12 +1435,12 @@ BX_CPU_C::BT_EvIb(BxInstruction_t *i) Bit32u op1_32; Bit8u op2_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); op2_8 %= 32; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1454,12 +1454,12 @@ BX_CPU_C::BT_EvIb(BxInstruction_t *i) Bit8u op2_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); op2_8 %= 16; /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1472,7 +1472,7 @@ BX_CPU_C::BT_EvIb(BxInstruction_t *i) } void -BX_CPU_C::BTS_EvIb(BxInstruction_t *i) +BX_CPU_C::BTS_EvIb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("BTS_EvIb: not available on <386")); @@ -1484,12 +1484,12 @@ BX_CPU_C::BTS_EvIb(BxInstruction_t *i) Bit64u op1_64, temp_CF; Bit8u op2_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); op2_8 %= 64; /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1500,8 +1500,8 @@ BX_CPU_C::BTS_EvIb(BxInstruction_t *i) op1_64 |= (((Bit64u) 1) << op2_8); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, op1_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), op1_64); } else { Write_RMW_virtual_qword(op1_64); @@ -1515,12 +1515,12 @@ BX_CPU_C::BTS_EvIb(BxInstruction_t *i) Bit32u op1_32, temp_CF; Bit8u op2_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); op2_8 %= 32; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1531,8 +1531,8 @@ BX_CPU_C::BTS_EvIb(BxInstruction_t *i) op1_32 |= (((Bit32u) 1) << op2_8); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, op1_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), op1_32); } else { write_RMW_virtual_dword(op1_32); @@ -1544,12 +1544,12 @@ BX_CPU_C::BTS_EvIb(BxInstruction_t *i) Bit8u op2_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); op2_8 %= 16; /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1560,8 +1560,8 @@ BX_CPU_C::BTS_EvIb(BxInstruction_t *i) op1_16 |= (((Bit16u) 1) << op2_8); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, op1_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), op1_16); } else { write_RMW_virtual_word(op1_16); @@ -1572,7 +1572,7 @@ BX_CPU_C::BTS_EvIb(BxInstruction_t *i) } void -BX_CPU_C::BTC_EvIb(BxInstruction_t *i) +BX_CPU_C::BTC_EvIb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("BTC_EvIb: not available on <386")); @@ -1584,12 +1584,12 @@ BX_CPU_C::BTC_EvIb(BxInstruction_t *i) Bit64u op1_64, temp_CF; Bit8u op2_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); op2_8 %= 64; /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1604,8 +1604,8 @@ BX_CPU_C::BTC_EvIb(BxInstruction_t *i) /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, op1_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), op1_64); } else { Write_RMW_virtual_qword(op1_64); @@ -1619,12 +1619,12 @@ BX_CPU_C::BTC_EvIb(BxInstruction_t *i) Bit32u op1_32, temp_CF; Bit8u op2_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); op2_8 %= 32; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1637,8 +1637,8 @@ BX_CPU_C::BTC_EvIb(BxInstruction_t *i) op1_32 |= (((Bit32u) !temp_CF) << op2_8); /* set to complement */ /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, op1_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), op1_32); } else { write_RMW_virtual_dword(op1_32); @@ -1650,12 +1650,12 @@ BX_CPU_C::BTC_EvIb(BxInstruction_t *i) Bit8u op2_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); op2_8 %= 16; /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1667,8 +1667,8 @@ BX_CPU_C::BTC_EvIb(BxInstruction_t *i) op1_16 |= (((Bit16u) !temp_CF) << op2_8); /* set to complement */ /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, op1_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), op1_16); } else { write_RMW_virtual_word(op1_16); @@ -1679,7 +1679,7 @@ BX_CPU_C::BTC_EvIb(BxInstruction_t *i) } void -BX_CPU_C::BTR_EvIb(BxInstruction_t *i) +BX_CPU_C::BTR_EvIb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("BTR_EvIb: not available on <386")); @@ -1691,12 +1691,12 @@ BX_CPU_C::BTR_EvIb(BxInstruction_t *i) Bit64u op1_64, temp_CF; Bit8u op2_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); op2_8 %= 64; /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1707,8 +1707,8 @@ BX_CPU_C::BTR_EvIb(BxInstruction_t *i) op1_64 &= ~(((Bit64u) 1) << op2_8); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, op1_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), op1_64); } else { Write_RMW_virtual_qword(op1_64); @@ -1722,12 +1722,12 @@ BX_CPU_C::BTR_EvIb(BxInstruction_t *i) Bit32u op1_32, temp_CF; Bit8u op2_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); op2_8 %= 32; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1738,8 +1738,8 @@ BX_CPU_C::BTR_EvIb(BxInstruction_t *i) op1_32 &= ~(((Bit32u) 1) << op2_8); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, op1_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), op1_32); } else { write_RMW_virtual_dword(op1_32); @@ -1751,12 +1751,12 @@ BX_CPU_C::BTR_EvIb(BxInstruction_t *i) Bit8u op2_8; - op2_8 = i->Ib; + op2_8 = i->Ib(); op2_8 %= 16; /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1767,8 +1767,8 @@ BX_CPU_C::BTR_EvIb(BxInstruction_t *i) op1_16 &= ~(((Bit16u) 1) << op2_8); /* now write diff back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, op1_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), op1_16); } else { write_RMW_virtual_word(op1_16); diff --git a/bochs/cpu/cpu.cc b/bochs/cpu/cpu.cc index e1e695f8a..0e66e6d6f 100644 --- a/bochs/cpu/cpu.cc +++ b/bochs/cpu/cpu.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: cpu.cc,v 1.43 2002-09-15 15:10:21 kevinlawton Exp $ +// $Id: cpu.cc,v 1.44 2002-09-17 22:50:51 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -115,7 +115,7 @@ extern void REGISTER_IADDR(bx_addr addr); BX_CPU_C::cpu_loop(Bit32s max_instr_count) { unsigned ret; - BxInstruction_t i; + bxInstruction_c i; #if BX_DEBUGGER BX_CPU_THIS_PTR break_point = 0; diff --git a/bochs/cpu/cpu.h b/bochs/cpu/cpu.h index 128866ceb..427ffc1e7 100644 --- a/bochs/cpu/cpu.h +++ b/bochs/cpu/cpu.h @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: cpu.h,v 1.60 2002-09-17 22:14:33 bdenney Exp $ +// $Id: cpu.h,v 1.61 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -648,7 +648,8 @@ typedef void * (*BxVoidFPtr_t)(void); class BX_CPU_C; -typedef struct BxInstruction_tag { +class bxInstruction_c { +public: // prefix stuff here... unsigned attr; // attribute from fetchdecode unsigned b1; // opcode1 byte @@ -658,72 +659,102 @@ typedef struct BxInstruction_tag { #if BX_SUPPORT_X86_64 unsigned os_64, as_64; // OperandSize/AddressSize is 64bit (overrides os_32/as_32) unsigned extend8bit; + unsigned rexB; #else enum { os_64=0, as_64=0 }; // x86-32: hardcode to 0. + enum { rexB=0 }; #endif - unsigned modrm; // mod-nnn-r/m byte - unsigned mod; - unsigned nnn; - unsigned rm; - unsigned sib; // scale-index-base (2nd modrm byte) - unsigned scale; - unsigned index; - unsigned base; - union { - Bit16u displ16u; // for 16-bit modrm forms - Bit32u displ32u; // for 32-bit modrm forms - }; union { + // Form (longest case): opcode/modrm/sib/displacement32/immediate32 + struct { + // Note: if you add more bits, mask the previously upper field, + // in the accessor. + // 27..20 modRM (modrm) + // 19..16 index (sib) + // 15..12 base (sib) + // 11...8 nnn (modrm) + // 7...6 mod (modrm) + // 5...4 scale (sib) + // 3...0 rm (modrm) + Bit32u modRMData; + + union { + Bit16u displ16u; // for 16-bit modrm forms + Bit32u displ32u; // for 32-bit modrm forms + }; + union { + Bit32u Id; + Bit16u Iw; + Bit8u Ib; + }; + union { // This is legacy and will change to the form below + Bit16u Iw2; + Bit8u Ib2; + }; + } modRMForm; + + // Form (longest case): opcode/Id1/Iw2 + struct { + Bit32u Id1; // Not used yet + Bit16u Iw2; // Not used yet + } IxIxForm; + #if BX_SUPPORT_X86_64 - Bit64u Iq; // for MOV Rx,imm64 + // Form: opcode/Iq + struct { + Bit64u Iq; // for MOV Rx,imm64 + } IqForm; #endif - Bit32u Id; - Bit16u Iw; - Bit8u Ib; - }; - union { - Bit8u Ib2; // for ENTER_IwIb - Bit16u Iw2; // for JMP_Ap }; bx_address rm_addr; unsigned ilen; // instruction length #if BX_USE_CPU_SMF - void (*ResolveModrm)(BxInstruction_tag *); - void (*execute)(BxInstruction_tag *); + void (*ResolveModrm)(bxInstruction_c *); + void (*execute)(bxInstruction_c *); #else - void (BX_CPU_C::*ResolveModrm)(BxInstruction_tag *); - void (BX_CPU_C::*execute)(BxInstruction_tag *); + void (BX_CPU_C::*ResolveModrm)(bxInstruction_c *); + void (BX_CPU_C::*execute)(bxInstruction_c *); #endif - } BxInstruction_t; + + BX_CPP_INLINE unsigned rex_b() { return rexB; } + BX_CPP_INLINE unsigned modrm() { return modRMForm.modRMData>>20; } + BX_CPP_INLINE unsigned mod() { return modRMForm.modRMData & 0xc0; } + BX_CPP_INLINE unsigned nnn() { + return (modRMForm.modRMData >> 8) & 0xf; + } + BX_CPP_INLINE unsigned rm() { return modRMForm.modRMData & 0xf; } + BX_CPP_INLINE unsigned sibScale() { + return (modRMForm.modRMData >> 4) & 0x3; + } + BX_CPP_INLINE unsigned sibIndex() { + return (modRMForm.modRMData >> 16) & 0xf; + } + BX_CPP_INLINE unsigned sibBase() { + return (modRMForm.modRMData >> 12) & 0xf; + } + BX_CPP_INLINE Bit32u displ32u() { return modRMForm.displ32u; } + BX_CPP_INLINE Bit16u displ16u() { return modRMForm.displ16u; } + BX_CPP_INLINE Bit32u Id() { return modRMForm.Id; } + BX_CPP_INLINE Bit16u Iw() { return modRMForm.Iw; } + BX_CPP_INLINE Bit8u Ib() { return modRMForm.Ib; } + BX_CPP_INLINE Bit16u Iw2() { return modRMForm.Iw2; } // Legacy + BX_CPP_INLINE Bit8u Ib2() { return modRMForm.Ib2; } // Legacy +#if BX_SUPPORT_X86_64 + BX_CPP_INLINE Bit64u Iq() { return IqForm.Iq; } +#endif + }; #if BX_USE_CPU_SMF -typedef void (*BxExecutePtr_t)(BxInstruction_t *); +typedef void (*BxExecutePtr_t)(bxInstruction_c *); #else -typedef void (BX_CPU_C::*BxExecutePtr_t)(BxInstruction_t *); +typedef void (BX_CPU_C::*BxExecutePtr_t)(bxInstruction_c *); #endif -#if BX_DYNAMIC_TRANSLATION -typedef Bit8u * (*BxDTASResolveModrm_t)(Bit8u *, BxInstruction_t *, - unsigned, unsigned); -#endif - - -#if BX_DYNAMIC_TRANSLATION -// Arrays of function pointers which handle a specific -// mod-rm address format -extern BxDTASResolveModrm_t BxDTResolve32Mod0[]; -extern BxDTASResolveModrm_t BxDTResolve32Mod1or2[]; -extern BxDTASResolveModrm_t BxDTResolve32Mod0Base[]; -extern BxDTASResolveModrm_t BxDTResolve32Mod1or2Base[]; -extern BxDTASResolveModrm_t BxDTResolve16Mod1or2[]; -extern BxDTASResolveModrm_t BxDTResolve16Mod0[]; -#endif - #if BX_CPU_LEVEL < 2 /* no GDTR or IDTR register in an 8086 */ @@ -1226,434 +1257,434 @@ union { void init (BX_MEM_C *addrspace); // prototypes for CPU instructions... - BX_SMF void ADD_EbGb(BxInstruction_t *); - BX_SMF void ADD_EdGd(BxInstruction_t *); - BX_SMF void ADD_GbEb(BxInstruction_t *); - BX_SMF void ADD_GdEd(BxInstruction_t *); - BX_SMF void ADD_ALIb(BxInstruction_t *); - BX_SMF void ADD_EAXId(BxInstruction_t *); - BX_SMF void OR_EbGb(BxInstruction_t *); - BX_SMF void OR_EdGd(BxInstruction_t *); - BX_SMF void OR_EwGw(BxInstruction_t *); - BX_SMF void OR_GbEb(BxInstruction_t *); - BX_SMF void OR_GdEd(BxInstruction_t *); - BX_SMF void OR_GwEw(BxInstruction_t *); - BX_SMF void OR_ALIb(BxInstruction_t *); - BX_SMF void OR_EAXId(BxInstruction_t *); - BX_SMF void OR_AXIw(BxInstruction_t *); + BX_SMF void ADD_EbGb(bxInstruction_c *); + BX_SMF void ADD_EdGd(bxInstruction_c *); + BX_SMF void ADD_GbEb(bxInstruction_c *); + BX_SMF void ADD_GdEd(bxInstruction_c *); + BX_SMF void ADD_ALIb(bxInstruction_c *); + BX_SMF void ADD_EAXId(bxInstruction_c *); + BX_SMF void OR_EbGb(bxInstruction_c *); + BX_SMF void OR_EdGd(bxInstruction_c *); + BX_SMF void OR_EwGw(bxInstruction_c *); + BX_SMF void OR_GbEb(bxInstruction_c *); + BX_SMF void OR_GdEd(bxInstruction_c *); + BX_SMF void OR_GwEw(bxInstruction_c *); + BX_SMF void OR_ALIb(bxInstruction_c *); + BX_SMF void OR_EAXId(bxInstruction_c *); + BX_SMF void OR_AXIw(bxInstruction_c *); - BX_SMF void PUSH_CS(BxInstruction_t *); - BX_SMF void PUSH_DS(BxInstruction_t *); - BX_SMF void POP_DS(BxInstruction_t *); - BX_SMF void PUSH_ES(BxInstruction_t *); - BX_SMF void POP_ES(BxInstruction_t *); - BX_SMF void PUSH_FS(BxInstruction_t *); - BX_SMF void POP_FS(BxInstruction_t *); - BX_SMF void PUSH_GS(BxInstruction_t *); - BX_SMF void POP_GS(BxInstruction_t *); - BX_SMF void PUSH_SS(BxInstruction_t *); - BX_SMF void POP_SS(BxInstruction_t *); + BX_SMF void PUSH_CS(bxInstruction_c *); + BX_SMF void PUSH_DS(bxInstruction_c *); + BX_SMF void POP_DS(bxInstruction_c *); + BX_SMF void PUSH_ES(bxInstruction_c *); + BX_SMF void POP_ES(bxInstruction_c *); + BX_SMF void PUSH_FS(bxInstruction_c *); + BX_SMF void POP_FS(bxInstruction_c *); + BX_SMF void PUSH_GS(bxInstruction_c *); + BX_SMF void POP_GS(bxInstruction_c *); + BX_SMF void PUSH_SS(bxInstruction_c *); + BX_SMF void POP_SS(bxInstruction_c *); - BX_SMF void ADC_EbGb(BxInstruction_t *); - BX_SMF void ADC_EdGd(BxInstruction_t *); - BX_SMF void ADC_GbEb(BxInstruction_t *); - BX_SMF void ADC_GdEd(BxInstruction_t *); - BX_SMF void ADC_ALIb(BxInstruction_t *); - BX_SMF void ADC_EAXId(BxInstruction_t *); - BX_SMF void SBB_EbGb(BxInstruction_t *); - BX_SMF void SBB_EdGd(BxInstruction_t *); - BX_SMF void SBB_GbEb(BxInstruction_t *); - BX_SMF void SBB_GdEd(BxInstruction_t *); - BX_SMF void SBB_ALIb(BxInstruction_t *); - BX_SMF void SBB_EAXId(BxInstruction_t *); + BX_SMF void ADC_EbGb(bxInstruction_c *); + BX_SMF void ADC_EdGd(bxInstruction_c *); + BX_SMF void ADC_GbEb(bxInstruction_c *); + BX_SMF void ADC_GdEd(bxInstruction_c *); + BX_SMF void ADC_ALIb(bxInstruction_c *); + BX_SMF void ADC_EAXId(bxInstruction_c *); + BX_SMF void SBB_EbGb(bxInstruction_c *); + BX_SMF void SBB_EdGd(bxInstruction_c *); + BX_SMF void SBB_GbEb(bxInstruction_c *); + BX_SMF void SBB_GdEd(bxInstruction_c *); + BX_SMF void SBB_ALIb(bxInstruction_c *); + BX_SMF void SBB_EAXId(bxInstruction_c *); - BX_SMF void AND_EbGb(BxInstruction_t *); - BX_SMF void AND_EdGd(BxInstruction_t *); - BX_SMF void AND_EwGw(BxInstruction_t *); - BX_SMF void AND_GbEb(BxInstruction_t *); - BX_SMF void AND_GdEd(BxInstruction_t *); - BX_SMF void AND_GwEw(BxInstruction_t *); - BX_SMF void AND_ALIb(BxInstruction_t *); - BX_SMF void AND_EAXId(BxInstruction_t *); - BX_SMF void AND_AXIw(BxInstruction_t *); - BX_SMF void DAA(BxInstruction_t *); - BX_SMF void SUB_EbGb(BxInstruction_t *); - BX_SMF void SUB_EdGd(BxInstruction_t *); - BX_SMF void SUB_GbEb(BxInstruction_t *); - BX_SMF void SUB_GdEd(BxInstruction_t *); - BX_SMF void SUB_ALIb(BxInstruction_t *); - BX_SMF void SUB_EAXId(BxInstruction_t *); - BX_SMF void DAS(BxInstruction_t *); + BX_SMF void AND_EbGb(bxInstruction_c *); + BX_SMF void AND_EdGd(bxInstruction_c *); + BX_SMF void AND_EwGw(bxInstruction_c *); + BX_SMF void AND_GbEb(bxInstruction_c *); + BX_SMF void AND_GdEd(bxInstruction_c *); + BX_SMF void AND_GwEw(bxInstruction_c *); + BX_SMF void AND_ALIb(bxInstruction_c *); + BX_SMF void AND_EAXId(bxInstruction_c *); + BX_SMF void AND_AXIw(bxInstruction_c *); + BX_SMF void DAA(bxInstruction_c *); + BX_SMF void SUB_EbGb(bxInstruction_c *); + BX_SMF void SUB_EdGd(bxInstruction_c *); + BX_SMF void SUB_GbEb(bxInstruction_c *); + BX_SMF void SUB_GdEd(bxInstruction_c *); + BX_SMF void SUB_ALIb(bxInstruction_c *); + BX_SMF void SUB_EAXId(bxInstruction_c *); + BX_SMF void DAS(bxInstruction_c *); - BX_SMF void XOR_EbGb(BxInstruction_t *); - BX_SMF void XOR_EdGd(BxInstruction_t *); - BX_SMF void XOR_EwGw(BxInstruction_t *); - BX_SMF void XOR_GbEb(BxInstruction_t *); - BX_SMF void XOR_GdEd(BxInstruction_t *); - BX_SMF void XOR_GwEw(BxInstruction_t *); - BX_SMF void XOR_ALIb(BxInstruction_t *); - BX_SMF void XOR_EAXId(BxInstruction_t *); - BX_SMF void XOR_AXIw(BxInstruction_t *); - BX_SMF void AAA(BxInstruction_t *); - BX_SMF void CMP_EbGb(BxInstruction_t *); - BX_SMF void CMP_EdGd(BxInstruction_t *); - BX_SMF void CMP_GbEb(BxInstruction_t *); - BX_SMF void CMP_GdEd(BxInstruction_t *); - BX_SMF void CMP_ALIb(BxInstruction_t *); - BX_SMF void CMP_EAXId(BxInstruction_t *); - BX_SMF void AAS(BxInstruction_t *); + BX_SMF void XOR_EbGb(bxInstruction_c *); + BX_SMF void XOR_EdGd(bxInstruction_c *); + BX_SMF void XOR_EwGw(bxInstruction_c *); + BX_SMF void XOR_GbEb(bxInstruction_c *); + BX_SMF void XOR_GdEd(bxInstruction_c *); + BX_SMF void XOR_GwEw(bxInstruction_c *); + BX_SMF void XOR_ALIb(bxInstruction_c *); + BX_SMF void XOR_EAXId(bxInstruction_c *); + BX_SMF void XOR_AXIw(bxInstruction_c *); + BX_SMF void AAA(bxInstruction_c *); + BX_SMF void CMP_EbGb(bxInstruction_c *); + BX_SMF void CMP_EdGd(bxInstruction_c *); + BX_SMF void CMP_GbEb(bxInstruction_c *); + BX_SMF void CMP_GdEd(bxInstruction_c *); + BX_SMF void CMP_ALIb(bxInstruction_c *); + BX_SMF void CMP_EAXId(bxInstruction_c *); + BX_SMF void AAS(bxInstruction_c *); - BX_SMF void PUSHAD32(BxInstruction_t *); - BX_SMF void PUSHAD16(BxInstruction_t *); - BX_SMF void POPAD32(BxInstruction_t *); - BX_SMF void POPAD16(BxInstruction_t *); - BX_SMF void BOUND_GvMa(BxInstruction_t *); - BX_SMF void ARPL_EwGw(BxInstruction_t *); - BX_SMF void PUSH_Id(BxInstruction_t *); - BX_SMF void PUSH_Iw(BxInstruction_t *); - BX_SMF void IMUL_GdEdId(BxInstruction_t *); - BX_SMF void INSB_YbDX(BxInstruction_t *); - BX_SMF void INSW_YvDX(BxInstruction_t *); - BX_SMF void OUTSB_DXXb(BxInstruction_t *); - BX_SMF void OUTSW_DXXv(BxInstruction_t *); + BX_SMF void PUSHAD32(bxInstruction_c *); + BX_SMF void PUSHAD16(bxInstruction_c *); + BX_SMF void POPAD32(bxInstruction_c *); + BX_SMF void POPAD16(bxInstruction_c *); + BX_SMF void BOUND_GvMa(bxInstruction_c *); + BX_SMF void ARPL_EwGw(bxInstruction_c *); + BX_SMF void PUSH_Id(bxInstruction_c *); + BX_SMF void PUSH_Iw(bxInstruction_c *); + BX_SMF void IMUL_GdEdId(bxInstruction_c *); + BX_SMF void INSB_YbDX(bxInstruction_c *); + BX_SMF void INSW_YvDX(bxInstruction_c *); + BX_SMF void OUTSB_DXXb(bxInstruction_c *); + BX_SMF void OUTSW_DXXv(bxInstruction_c *); - BX_SMF void TEST_EbGb(BxInstruction_t *); - BX_SMF void TEST_EdGd(BxInstruction_t *); - BX_SMF void TEST_EwGw(BxInstruction_t *); - BX_SMF void XCHG_EbGb(BxInstruction_t *); - BX_SMF void XCHG_EdGd(BxInstruction_t *); - BX_SMF void XCHG_EwGw(BxInstruction_t *); - BX_SMF void MOV_EbGb(BxInstruction_t *); - BX_SMF void MOV_EdGd(BxInstruction_t *); - BX_SMF void MOV_EwGw(BxInstruction_t *); - BX_SMF void MOV_GbEb(BxInstruction_t *); - BX_SMF void MOV_GdEd(BxInstruction_t *); - BX_SMF void MOV_GwEw(BxInstruction_t *); - BX_SMF void MOV_EwSw(BxInstruction_t *); - BX_SMF void LEA_GdM(BxInstruction_t *); - BX_SMF void LEA_GwM(BxInstruction_t *); - BX_SMF void MOV_SwEw(BxInstruction_t *); - BX_SMF void POP_Ev(BxInstruction_t *); + BX_SMF void TEST_EbGb(bxInstruction_c *); + BX_SMF void TEST_EdGd(bxInstruction_c *); + BX_SMF void TEST_EwGw(bxInstruction_c *); + BX_SMF void XCHG_EbGb(bxInstruction_c *); + BX_SMF void XCHG_EdGd(bxInstruction_c *); + BX_SMF void XCHG_EwGw(bxInstruction_c *); + BX_SMF void MOV_EbGb(bxInstruction_c *); + BX_SMF void MOV_EdGd(bxInstruction_c *); + BX_SMF void MOV_EwGw(bxInstruction_c *); + BX_SMF void MOV_GbEb(bxInstruction_c *); + BX_SMF void MOV_GdEd(bxInstruction_c *); + BX_SMF void MOV_GwEw(bxInstruction_c *); + BX_SMF void MOV_EwSw(bxInstruction_c *); + BX_SMF void LEA_GdM(bxInstruction_c *); + BX_SMF void LEA_GwM(bxInstruction_c *); + BX_SMF void MOV_SwEw(bxInstruction_c *); + BX_SMF void POP_Ev(bxInstruction_c *); - BX_SMF void CBW(BxInstruction_t *); - BX_SMF void CWD(BxInstruction_t *); - BX_SMF void CALL32_Ap(BxInstruction_t *); - BX_SMF void CALL16_Ap(BxInstruction_t *); - BX_SMF void FWAIT(BxInstruction_t *); - BX_SMF void PUSHF_Fv(BxInstruction_t *); - BX_SMF void POPF_Fv(BxInstruction_t *); - BX_SMF void SAHF(BxInstruction_t *); - BX_SMF void LAHF(BxInstruction_t *); + BX_SMF void CBW(bxInstruction_c *); + BX_SMF void CWD(bxInstruction_c *); + BX_SMF void CALL32_Ap(bxInstruction_c *); + BX_SMF void CALL16_Ap(bxInstruction_c *); + BX_SMF void FWAIT(bxInstruction_c *); + BX_SMF void PUSHF_Fv(bxInstruction_c *); + BX_SMF void POPF_Fv(bxInstruction_c *); + BX_SMF void SAHF(bxInstruction_c *); + BX_SMF void LAHF(bxInstruction_c *); - BX_SMF void MOV_ALOb(BxInstruction_t *); - BX_SMF void MOV_EAXOd(BxInstruction_t *); - BX_SMF void MOV_AXOw(BxInstruction_t *); - BX_SMF void MOV_ObAL(BxInstruction_t *); - BX_SMF void MOV_OdEAX(BxInstruction_t *); - BX_SMF void MOV_OwAX(BxInstruction_t *); - BX_SMF void MOVSB_XbYb(BxInstruction_t *); - BX_SMF void MOVSW_XvYv(BxInstruction_t *); - BX_SMF void CMPSB_XbYb(BxInstruction_t *); - BX_SMF void CMPSW_XvYv(BxInstruction_t *); - BX_SMF void TEST_ALIb(BxInstruction_t *); - BX_SMF void TEST_EAXId(BxInstruction_t *); - BX_SMF void TEST_AXIw(BxInstruction_t *); - BX_SMF void STOSB_YbAL(BxInstruction_t *); - BX_SMF void STOSW_YveAX(BxInstruction_t *); - BX_SMF void LODSB_ALXb(BxInstruction_t *); - BX_SMF void LODSW_eAXXv(BxInstruction_t *); - BX_SMF void SCASB_ALXb(BxInstruction_t *); - BX_SMF void SCASW_eAXXv(BxInstruction_t *); + BX_SMF void MOV_ALOb(bxInstruction_c *); + BX_SMF void MOV_EAXOd(bxInstruction_c *); + BX_SMF void MOV_AXOw(bxInstruction_c *); + BX_SMF void MOV_ObAL(bxInstruction_c *); + BX_SMF void MOV_OdEAX(bxInstruction_c *); + BX_SMF void MOV_OwAX(bxInstruction_c *); + BX_SMF void MOVSB_XbYb(bxInstruction_c *); + BX_SMF void MOVSW_XvYv(bxInstruction_c *); + BX_SMF void CMPSB_XbYb(bxInstruction_c *); + BX_SMF void CMPSW_XvYv(bxInstruction_c *); + BX_SMF void TEST_ALIb(bxInstruction_c *); + BX_SMF void TEST_EAXId(bxInstruction_c *); + BX_SMF void TEST_AXIw(bxInstruction_c *); + BX_SMF void STOSB_YbAL(bxInstruction_c *); + BX_SMF void STOSW_YveAX(bxInstruction_c *); + BX_SMF void LODSB_ALXb(bxInstruction_c *); + BX_SMF void LODSW_eAXXv(bxInstruction_c *); + BX_SMF void SCASB_ALXb(bxInstruction_c *); + BX_SMF void SCASW_eAXXv(bxInstruction_c *); - BX_SMF void RETnear32(BxInstruction_t *); - BX_SMF void RETnear16(BxInstruction_t *); - BX_SMF void LES_GvMp(BxInstruction_t *); - BX_SMF void LDS_GvMp(BxInstruction_t *); - BX_SMF void MOV_EbIb(BxInstruction_t *); - BX_SMF void MOV_EdId(BxInstruction_t *); - BX_SMF void MOV_EwIw(BxInstruction_t *); - BX_SMF void ENTER_IwIb(BxInstruction_t *); - BX_SMF void LEAVE(BxInstruction_t *); - BX_SMF void RETfar32(BxInstruction_t *); - BX_SMF void RETfar16(BxInstruction_t *); + BX_SMF void RETnear32(bxInstruction_c *); + BX_SMF void RETnear16(bxInstruction_c *); + BX_SMF void LES_GvMp(bxInstruction_c *); + BX_SMF void LDS_GvMp(bxInstruction_c *); + BX_SMF void MOV_EbIb(bxInstruction_c *); + BX_SMF void MOV_EdId(bxInstruction_c *); + BX_SMF void MOV_EwIw(bxInstruction_c *); + BX_SMF void ENTER_IwIb(bxInstruction_c *); + BX_SMF void LEAVE(bxInstruction_c *); + BX_SMF void RETfar32(bxInstruction_c *); + BX_SMF void RETfar16(bxInstruction_c *); - BX_SMF void INT1(BxInstruction_t *); - BX_SMF void INT3(BxInstruction_t *); - BX_SMF void INT_Ib(BxInstruction_t *); - BX_SMF void INTO(BxInstruction_t *); - BX_SMF void IRET32(BxInstruction_t *); - BX_SMF void IRET16(BxInstruction_t *); + BX_SMF void INT1(bxInstruction_c *); + BX_SMF void INT3(bxInstruction_c *); + BX_SMF void INT_Ib(bxInstruction_c *); + BX_SMF void INTO(bxInstruction_c *); + BX_SMF void IRET32(bxInstruction_c *); + BX_SMF void IRET16(bxInstruction_c *); - BX_SMF void AAM(BxInstruction_t *); - BX_SMF void AAD(BxInstruction_t *); - BX_SMF void SALC(BxInstruction_t *); - BX_SMF void XLAT(BxInstruction_t *); + BX_SMF void AAM(bxInstruction_c *); + BX_SMF void AAD(bxInstruction_c *); + BX_SMF void SALC(bxInstruction_c *); + BX_SMF void XLAT(bxInstruction_c *); - BX_SMF void LOOPNE_Jb(BxInstruction_t *); - BX_SMF void LOOPE_Jb(BxInstruction_t *); - BX_SMF void LOOP_Jb(BxInstruction_t *); - BX_SMF void JCXZ_Jb(BxInstruction_t *); - BX_SMF void IN_ALIb(BxInstruction_t *); - BX_SMF void IN_eAXIb(BxInstruction_t *); - BX_SMF void OUT_IbAL(BxInstruction_t *); - BX_SMF void OUT_IbeAX(BxInstruction_t *); - BX_SMF void CALL_Aw(BxInstruction_t *); - BX_SMF void CALL_Ad(BxInstruction_t *); - BX_SMF void JMP_Jd(BxInstruction_t *); - BX_SMF void JMP_Jw(BxInstruction_t *); - BX_SMF void JMP_Ap(BxInstruction_t *); - BX_SMF void IN_ALDX(BxInstruction_t *); - BX_SMF void IN_eAXDX(BxInstruction_t *); - BX_SMF void OUT_DXAL(BxInstruction_t *); - BX_SMF void OUT_DXeAX(BxInstruction_t *); + BX_SMF void LOOPNE_Jb(bxInstruction_c *); + BX_SMF void LOOPE_Jb(bxInstruction_c *); + BX_SMF void LOOP_Jb(bxInstruction_c *); + BX_SMF void JCXZ_Jb(bxInstruction_c *); + BX_SMF void IN_ALIb(bxInstruction_c *); + BX_SMF void IN_eAXIb(bxInstruction_c *); + BX_SMF void OUT_IbAL(bxInstruction_c *); + BX_SMF void OUT_IbeAX(bxInstruction_c *); + BX_SMF void CALL_Aw(bxInstruction_c *); + BX_SMF void CALL_Ad(bxInstruction_c *); + BX_SMF void JMP_Jd(bxInstruction_c *); + BX_SMF void JMP_Jw(bxInstruction_c *); + BX_SMF void JMP_Ap(bxInstruction_c *); + BX_SMF void IN_ALDX(bxInstruction_c *); + BX_SMF void IN_eAXDX(bxInstruction_c *); + BX_SMF void OUT_DXAL(bxInstruction_c *); + BX_SMF void OUT_DXeAX(bxInstruction_c *); - BX_SMF void HLT(BxInstruction_t *); - BX_SMF void CMC(BxInstruction_t *); - BX_SMF void CLC(BxInstruction_t *); - BX_SMF void STC(BxInstruction_t *); - BX_SMF void CLI(BxInstruction_t *); - BX_SMF void STI(BxInstruction_t *); - BX_SMF void CLD(BxInstruction_t *); - BX_SMF void STD(BxInstruction_t *); + BX_SMF void HLT(bxInstruction_c *); + BX_SMF void CMC(bxInstruction_c *); + BX_SMF void CLC(bxInstruction_c *); + BX_SMF void STC(bxInstruction_c *); + BX_SMF void CLI(bxInstruction_c *); + BX_SMF void STI(bxInstruction_c *); + BX_SMF void CLD(bxInstruction_c *); + BX_SMF void STD(bxInstruction_c *); - BX_SMF void LAR_GvEw(BxInstruction_t *); - BX_SMF void LSL_GvEw(BxInstruction_t *); - BX_SMF void CLTS(BxInstruction_t *); - BX_SMF void INVD(BxInstruction_t *); - BX_SMF void WBINVD(BxInstruction_t *); + BX_SMF void LAR_GvEw(bxInstruction_c *); + BX_SMF void LSL_GvEw(bxInstruction_c *); + BX_SMF void CLTS(bxInstruction_c *); + BX_SMF void INVD(bxInstruction_c *); + BX_SMF void WBINVD(bxInstruction_c *); - BX_SMF void MOV_CdRd(BxInstruction_t *); - BX_SMF void MOV_DdRd(BxInstruction_t *); - BX_SMF void MOV_RdCd(BxInstruction_t *); - BX_SMF void MOV_RdDd(BxInstruction_t *); - BX_SMF void MOV_TdRd(BxInstruction_t *); - BX_SMF void MOV_RdTd(BxInstruction_t *); + BX_SMF void MOV_CdRd(bxInstruction_c *); + BX_SMF void MOV_DdRd(bxInstruction_c *); + BX_SMF void MOV_RdCd(bxInstruction_c *); + BX_SMF void MOV_RdDd(bxInstruction_c *); + BX_SMF void MOV_TdRd(bxInstruction_c *); + BX_SMF void MOV_RdTd(bxInstruction_c *); - BX_SMF void JCC_Jd(BxInstruction_t *); - BX_SMF void JCC_Jw(BxInstruction_t *); + BX_SMF void JCC_Jd(bxInstruction_c *); + BX_SMF void JCC_Jw(bxInstruction_c *); - BX_SMF void SETO_Eb(BxInstruction_t *); - BX_SMF void SETNO_Eb(BxInstruction_t *); - BX_SMF void SETB_Eb(BxInstruction_t *); - BX_SMF void SETNB_Eb(BxInstruction_t *); - BX_SMF void SETZ_Eb(BxInstruction_t *); - BX_SMF void SETNZ_Eb(BxInstruction_t *); - BX_SMF void SETBE_Eb(BxInstruction_t *); - BX_SMF void SETNBE_Eb(BxInstruction_t *); - BX_SMF void SETS_Eb(BxInstruction_t *); - BX_SMF void SETNS_Eb(BxInstruction_t *); - BX_SMF void SETP_Eb(BxInstruction_t *); - BX_SMF void SETNP_Eb(BxInstruction_t *); - BX_SMF void SETL_Eb(BxInstruction_t *); - BX_SMF void SETNL_Eb(BxInstruction_t *); - BX_SMF void SETLE_Eb(BxInstruction_t *); - BX_SMF void SETNLE_Eb(BxInstruction_t *); + BX_SMF void SETO_Eb(bxInstruction_c *); + BX_SMF void SETNO_Eb(bxInstruction_c *); + BX_SMF void SETB_Eb(bxInstruction_c *); + BX_SMF void SETNB_Eb(bxInstruction_c *); + BX_SMF void SETZ_Eb(bxInstruction_c *); + BX_SMF void SETNZ_Eb(bxInstruction_c *); + BX_SMF void SETBE_Eb(bxInstruction_c *); + BX_SMF void SETNBE_Eb(bxInstruction_c *); + BX_SMF void SETS_Eb(bxInstruction_c *); + BX_SMF void SETNS_Eb(bxInstruction_c *); + BX_SMF void SETP_Eb(bxInstruction_c *); + BX_SMF void SETNP_Eb(bxInstruction_c *); + BX_SMF void SETL_Eb(bxInstruction_c *); + BX_SMF void SETNL_Eb(bxInstruction_c *); + BX_SMF void SETLE_Eb(bxInstruction_c *); + BX_SMF void SETNLE_Eb(bxInstruction_c *); - BX_SMF void CPUID(BxInstruction_t *); - BX_SMF void BT_EvGv(BxInstruction_t *); - BX_SMF void SHLD_EdGd(BxInstruction_t *); - BX_SMF void SHLD_EwGw(BxInstruction_t *); + BX_SMF void CPUID(bxInstruction_c *); + BX_SMF void BT_EvGv(bxInstruction_c *); + BX_SMF void SHLD_EdGd(bxInstruction_c *); + BX_SMF void SHLD_EwGw(bxInstruction_c *); - BX_SMF void BTS_EvGv(BxInstruction_t *); + BX_SMF void BTS_EvGv(bxInstruction_c *); - BX_SMF void SHRD_EwGw(BxInstruction_t *); - BX_SMF void SHRD_EdGd(BxInstruction_t *); + BX_SMF void SHRD_EwGw(bxInstruction_c *); + BX_SMF void SHRD_EdGd(bxInstruction_c *); - BX_SMF void IMUL_GdEd(BxInstruction_t *); + BX_SMF void IMUL_GdEd(bxInstruction_c *); - BX_SMF void LSS_GvMp(BxInstruction_t *); - BX_SMF void BTR_EvGv(BxInstruction_t *); - BX_SMF void LFS_GvMp(BxInstruction_t *); - BX_SMF void LGS_GvMp(BxInstruction_t *); - BX_SMF void MOVZX_GdEb(BxInstruction_t *); - BX_SMF void MOVZX_GwEb(BxInstruction_t *); - BX_SMF void MOVZX_GdEw(BxInstruction_t *); - BX_SMF void MOVZX_GwEw(BxInstruction_t *); - BX_SMF void BTC_EvGv(BxInstruction_t *); - BX_SMF void BSF_GvEv(BxInstruction_t *); - BX_SMF void BSR_GvEv(BxInstruction_t *); - BX_SMF void MOVSX_GdEb(BxInstruction_t *); - BX_SMF void MOVSX_GwEb(BxInstruction_t *); - BX_SMF void MOVSX_GdEw(BxInstruction_t *); - BX_SMF void MOVSX_GwEw(BxInstruction_t *); + BX_SMF void LSS_GvMp(bxInstruction_c *); + BX_SMF void BTR_EvGv(bxInstruction_c *); + BX_SMF void LFS_GvMp(bxInstruction_c *); + BX_SMF void LGS_GvMp(bxInstruction_c *); + BX_SMF void MOVZX_GdEb(bxInstruction_c *); + BX_SMF void MOVZX_GwEb(bxInstruction_c *); + BX_SMF void MOVZX_GdEw(bxInstruction_c *); + BX_SMF void MOVZX_GwEw(bxInstruction_c *); + BX_SMF void BTC_EvGv(bxInstruction_c *); + BX_SMF void BSF_GvEv(bxInstruction_c *); + BX_SMF void BSR_GvEv(bxInstruction_c *); + BX_SMF void MOVSX_GdEb(bxInstruction_c *); + BX_SMF void MOVSX_GwEb(bxInstruction_c *); + BX_SMF void MOVSX_GdEw(bxInstruction_c *); + BX_SMF void MOVSX_GwEw(bxInstruction_c *); - BX_SMF void BSWAP_EAX(BxInstruction_t *); - BX_SMF void BSWAP_ECX(BxInstruction_t *); - BX_SMF void BSWAP_EDX(BxInstruction_t *); - BX_SMF void BSWAP_EBX(BxInstruction_t *); - BX_SMF void BSWAP_ESP(BxInstruction_t *); - BX_SMF void BSWAP_EBP(BxInstruction_t *); - BX_SMF void BSWAP_ESI(BxInstruction_t *); - BX_SMF void BSWAP_EDI(BxInstruction_t *); + BX_SMF void BSWAP_EAX(bxInstruction_c *); + BX_SMF void BSWAP_ECX(bxInstruction_c *); + BX_SMF void BSWAP_EDX(bxInstruction_c *); + BX_SMF void BSWAP_EBX(bxInstruction_c *); + BX_SMF void BSWAP_ESP(bxInstruction_c *); + BX_SMF void BSWAP_EBP(bxInstruction_c *); + BX_SMF void BSWAP_ESI(bxInstruction_c *); + BX_SMF void BSWAP_EDI(bxInstruction_c *); - BX_SMF void ADD_EbIb(BxInstruction_t *); - BX_SMF void ADC_EbIb(BxInstruction_t *); - BX_SMF void SBB_EbIb(BxInstruction_t *); - BX_SMF void SUB_EbIb(BxInstruction_t *); - BX_SMF void CMP_EbIb(BxInstruction_t *); + BX_SMF void ADD_EbIb(bxInstruction_c *); + BX_SMF void ADC_EbIb(bxInstruction_c *); + BX_SMF void SBB_EbIb(bxInstruction_c *); + BX_SMF void SUB_EbIb(bxInstruction_c *); + BX_SMF void CMP_EbIb(bxInstruction_c *); - BX_SMF void XOR_EbIb(BxInstruction_t *); - BX_SMF void OR_EbIb(BxInstruction_t *); - BX_SMF void AND_EbIb(BxInstruction_t *); + BX_SMF void XOR_EbIb(bxInstruction_c *); + BX_SMF void OR_EbIb(bxInstruction_c *); + BX_SMF void AND_EbIb(bxInstruction_c *); - BX_SMF void ADD_EdId(BxInstruction_t *); - BX_SMF void OR_EdId(BxInstruction_t *); - BX_SMF void OR_EwIw(BxInstruction_t *); - BX_SMF void ADC_EdId(BxInstruction_t *); - BX_SMF void SBB_EdId(BxInstruction_t *); - BX_SMF void AND_EdId(BxInstruction_t *); - BX_SMF void AND_EwIw(BxInstruction_t *); - BX_SMF void SUB_EdId(BxInstruction_t *); - BX_SMF void XOR_EdId(BxInstruction_t *); - BX_SMF void XOR_EwIw(BxInstruction_t *); - BX_SMF void CMP_EdId(BxInstruction_t *); + BX_SMF void ADD_EdId(bxInstruction_c *); + BX_SMF void OR_EdId(bxInstruction_c *); + BX_SMF void OR_EwIw(bxInstruction_c *); + BX_SMF void ADC_EdId(bxInstruction_c *); + BX_SMF void SBB_EdId(bxInstruction_c *); + BX_SMF void AND_EdId(bxInstruction_c *); + BX_SMF void AND_EwIw(bxInstruction_c *); + BX_SMF void SUB_EdId(bxInstruction_c *); + BX_SMF void XOR_EdId(bxInstruction_c *); + BX_SMF void XOR_EwIw(bxInstruction_c *); + BX_SMF void CMP_EdId(bxInstruction_c *); - BX_SMF void ROL_Eb(BxInstruction_t *); - BX_SMF void ROR_Eb(BxInstruction_t *); - BX_SMF void RCL_Eb(BxInstruction_t *); - BX_SMF void RCR_Eb(BxInstruction_t *); - BX_SMF void SHL_Eb(BxInstruction_t *); - BX_SMF void SHR_Eb(BxInstruction_t *); - BX_SMF void SAR_Eb(BxInstruction_t *); + BX_SMF void ROL_Eb(bxInstruction_c *); + BX_SMF void ROR_Eb(bxInstruction_c *); + BX_SMF void RCL_Eb(bxInstruction_c *); + BX_SMF void RCR_Eb(bxInstruction_c *); + BX_SMF void SHL_Eb(bxInstruction_c *); + BX_SMF void SHR_Eb(bxInstruction_c *); + BX_SMF void SAR_Eb(bxInstruction_c *); - BX_SMF void ROL_Ed(BxInstruction_t *); - BX_SMF void ROL_Ew(BxInstruction_t *); - BX_SMF void ROR_Ed(BxInstruction_t *); - BX_SMF void ROR_Ew(BxInstruction_t *); - BX_SMF void RCL_Ed(BxInstruction_t *); - BX_SMF void RCL_Ew(BxInstruction_t *); - BX_SMF void RCR_Ed(BxInstruction_t *); - BX_SMF void RCR_Ew(BxInstruction_t *); - BX_SMF void SHL_Ed(BxInstruction_t *); - BX_SMF void SHL_Ew(BxInstruction_t *); - BX_SMF void SHR_Ed(BxInstruction_t *); - BX_SMF void SHR_Ew(BxInstruction_t *); - BX_SMF void SAR_Ed(BxInstruction_t *); - BX_SMF void SAR_Ew(BxInstruction_t *); + BX_SMF void ROL_Ed(bxInstruction_c *); + BX_SMF void ROL_Ew(bxInstruction_c *); + BX_SMF void ROR_Ed(bxInstruction_c *); + BX_SMF void ROR_Ew(bxInstruction_c *); + BX_SMF void RCL_Ed(bxInstruction_c *); + BX_SMF void RCL_Ew(bxInstruction_c *); + BX_SMF void RCR_Ed(bxInstruction_c *); + BX_SMF void RCR_Ew(bxInstruction_c *); + BX_SMF void SHL_Ed(bxInstruction_c *); + BX_SMF void SHL_Ew(bxInstruction_c *); + BX_SMF void SHR_Ed(bxInstruction_c *); + BX_SMF void SHR_Ew(bxInstruction_c *); + BX_SMF void SAR_Ed(bxInstruction_c *); + BX_SMF void SAR_Ew(bxInstruction_c *); - BX_SMF void TEST_EbIb(BxInstruction_t *); - BX_SMF void NOT_Eb(BxInstruction_t *); - BX_SMF void NEG_Eb(BxInstruction_t *); - BX_SMF void MUL_ALEb(BxInstruction_t *); - BX_SMF void IMUL_ALEb(BxInstruction_t *); - BX_SMF void DIV_ALEb(BxInstruction_t *); - BX_SMF void IDIV_ALEb(BxInstruction_t *); + BX_SMF void TEST_EbIb(bxInstruction_c *); + BX_SMF void NOT_Eb(bxInstruction_c *); + BX_SMF void NEG_Eb(bxInstruction_c *); + BX_SMF void MUL_ALEb(bxInstruction_c *); + BX_SMF void IMUL_ALEb(bxInstruction_c *); + BX_SMF void DIV_ALEb(bxInstruction_c *); + BX_SMF void IDIV_ALEb(bxInstruction_c *); - BX_SMF void TEST_EdId(BxInstruction_t *); - BX_SMF void TEST_EwIw(BxInstruction_t *); - BX_SMF void NOT_Ed(BxInstruction_t *); - BX_SMF void NOT_Ew(BxInstruction_t *); - BX_SMF void NEG_Ed(BxInstruction_t *); - BX_SMF void MUL_EAXEd(BxInstruction_t *); - BX_SMF void IMUL_EAXEd(BxInstruction_t *); - BX_SMF void DIV_EAXEd(BxInstruction_t *); - BX_SMF void IDIV_EAXEd(BxInstruction_t *); + BX_SMF void TEST_EdId(bxInstruction_c *); + BX_SMF void TEST_EwIw(bxInstruction_c *); + BX_SMF void NOT_Ed(bxInstruction_c *); + BX_SMF void NOT_Ew(bxInstruction_c *); + BX_SMF void NEG_Ed(bxInstruction_c *); + BX_SMF void MUL_EAXEd(bxInstruction_c *); + BX_SMF void IMUL_EAXEd(bxInstruction_c *); + BX_SMF void DIV_EAXEd(bxInstruction_c *); + BX_SMF void IDIV_EAXEd(bxInstruction_c *); - BX_SMF void INC_Eb(BxInstruction_t *); - BX_SMF void DEC_Eb(BxInstruction_t *); + BX_SMF void INC_Eb(bxInstruction_c *); + BX_SMF void DEC_Eb(bxInstruction_c *); - BX_SMF void INC_Ed(BxInstruction_t *); - BX_SMF void DEC_Ed(BxInstruction_t *); - BX_SMF void CALL_Ed(BxInstruction_t *); - BX_SMF void CALL_Ew(BxInstruction_t *); - BX_SMF void CALL32_Ep(BxInstruction_t *); - BX_SMF void CALL16_Ep(BxInstruction_t *); - BX_SMF void JMP_Ed(BxInstruction_t *); - BX_SMF void JMP_Ew(BxInstruction_t *); - BX_SMF void JMP32_Ep(BxInstruction_t *); - BX_SMF void JMP16_Ep(BxInstruction_t *); - BX_SMF void PUSH_Ed(BxInstruction_t *); - BX_SMF void PUSH_Ew(BxInstruction_t *); + BX_SMF void INC_Ed(bxInstruction_c *); + BX_SMF void DEC_Ed(bxInstruction_c *); + BX_SMF void CALL_Ed(bxInstruction_c *); + BX_SMF void CALL_Ew(bxInstruction_c *); + BX_SMF void CALL32_Ep(bxInstruction_c *); + BX_SMF void CALL16_Ep(bxInstruction_c *); + BX_SMF void JMP_Ed(bxInstruction_c *); + BX_SMF void JMP_Ew(bxInstruction_c *); + BX_SMF void JMP32_Ep(bxInstruction_c *); + BX_SMF void JMP16_Ep(bxInstruction_c *); + BX_SMF void PUSH_Ed(bxInstruction_c *); + BX_SMF void PUSH_Ew(bxInstruction_c *); - BX_SMF void SLDT_Ew(BxInstruction_t *); - BX_SMF void STR_Ew(BxInstruction_t *); - BX_SMF void LLDT_Ew(BxInstruction_t *); - BX_SMF void LTR_Ew(BxInstruction_t *); - BX_SMF void VERR_Ew(BxInstruction_t *); - BX_SMF void VERW_Ew(BxInstruction_t *); + BX_SMF void SLDT_Ew(bxInstruction_c *); + BX_SMF void STR_Ew(bxInstruction_c *); + BX_SMF void LLDT_Ew(bxInstruction_c *); + BX_SMF void LTR_Ew(bxInstruction_c *); + BX_SMF void VERR_Ew(bxInstruction_c *); + BX_SMF void VERW_Ew(bxInstruction_c *); - BX_SMF void SGDT_Ms(BxInstruction_t *); - BX_SMF void SIDT_Ms(BxInstruction_t *); - BX_SMF void LGDT_Ms(BxInstruction_t *); - BX_SMF void LIDT_Ms(BxInstruction_t *); - BX_SMF void SMSW_Ew(BxInstruction_t *); - BX_SMF void LMSW_Ew(BxInstruction_t *); + BX_SMF void SGDT_Ms(bxInstruction_c *); + BX_SMF void SIDT_Ms(bxInstruction_c *); + BX_SMF void LGDT_Ms(bxInstruction_c *); + BX_SMF void LIDT_Ms(bxInstruction_c *); + BX_SMF void SMSW_Ew(bxInstruction_c *); + BX_SMF void LMSW_Ew(bxInstruction_c *); - BX_SMF void BT_EvIb(BxInstruction_t *); - BX_SMF void BTS_EvIb(BxInstruction_t *); - BX_SMF void BTR_EvIb(BxInstruction_t *); - BX_SMF void BTC_EvIb(BxInstruction_t *); + BX_SMF void BT_EvIb(bxInstruction_c *); + BX_SMF void BTS_EvIb(bxInstruction_c *); + BX_SMF void BTR_EvIb(bxInstruction_c *); + BX_SMF void BTC_EvIb(bxInstruction_c *); - BX_SMF void ESC0(BxInstruction_t *); - BX_SMF void ESC1(BxInstruction_t *); - BX_SMF void ESC2(BxInstruction_t *); - BX_SMF void ESC3(BxInstruction_t *); - BX_SMF void ESC4(BxInstruction_t *); - BX_SMF void ESC5(BxInstruction_t *); - BX_SMF void ESC6(BxInstruction_t *); - BX_SMF void ESC7(BxInstruction_t *); + BX_SMF void ESC0(bxInstruction_c *); + BX_SMF void ESC1(bxInstruction_c *); + BX_SMF void ESC2(bxInstruction_c *); + BX_SMF void ESC3(bxInstruction_c *); + BX_SMF void ESC4(bxInstruction_c *); + BX_SMF void ESC5(bxInstruction_c *); + BX_SMF void ESC6(bxInstruction_c *); + BX_SMF void ESC7(bxInstruction_c *); /* MMX */ - BX_SMF void PUNPCKLBW_PqQd(BxInstruction_t *i); - BX_SMF void PUNPCKLWD_PqQd(BxInstruction_t *i); - BX_SMF void PUNPCKLDQ_PqQd(BxInstruction_t *i); - BX_SMF void PACKSSWB_PqQq(BxInstruction_t *i); - BX_SMF void PCMPGTB_PqQq(BxInstruction_t *i); - BX_SMF void PCMPGTW_PqQq(BxInstruction_t *i); - BX_SMF void PCMPGTD_PqQq(BxInstruction_t *i); - BX_SMF void PACKUSWB_PqQq(BxInstruction_t *i); - BX_SMF void PUNPCKHBW_PqQq(BxInstruction_t *i); - BX_SMF void PUNPCKHWD_PqQq(BxInstruction_t *i); - BX_SMF void PUNPCKHDQ_PqQq(BxInstruction_t *i); - BX_SMF void PACKSSDW_PqQq(BxInstruction_t *i); - BX_SMF void MOVD_PqEd(BxInstruction_t *i); - BX_SMF void MOVQ_PqQq(BxInstruction_t *i); - BX_SMF void PCMPEQB_PqQq(BxInstruction_t *i); - BX_SMF void PCMPEQW_PqQq(BxInstruction_t *i); - BX_SMF void PCMPEQD_PqQq(BxInstruction_t *i); - BX_SMF void EMMS(BxInstruction_t *i); - BX_SMF void MOVD_EdPd(BxInstruction_t *i); - BX_SMF void MOVQ_QqPq(BxInstruction_t *i); - BX_SMF void PSRLW_PqQq(BxInstruction_t *i); - BX_SMF void PSRLD_PqQq(BxInstruction_t *i); - BX_SMF void PSRLQ_PqQq(BxInstruction_t *i); - BX_SMF void PMULLW_PqQq(BxInstruction_t *i); - BX_SMF void PSUBUSB_PqQq(BxInstruction_t *i); - BX_SMF void PSUBUSW_PqQq(BxInstruction_t *i); - BX_SMF void PAND_PqQq(BxInstruction_t *i); - BX_SMF void PADDUSB_PqQq(BxInstruction_t *i); - BX_SMF void PADDUSW_PqQq(BxInstruction_t *i); - BX_SMF void PANDN_PqQq(BxInstruction_t *i); - BX_SMF void PSRAW_PqQq(BxInstruction_t *i); - BX_SMF void PSRAD_PqQq(BxInstruction_t *i); - BX_SMF void PMULHW_PqQq(BxInstruction_t *i); - BX_SMF void PSUBSB_PqQq(BxInstruction_t *i); - BX_SMF void PSUBSW_PqQq(BxInstruction_t *i); - BX_SMF void POR_PqQq(BxInstruction_t *i); - BX_SMF void PADDSB_PqQq(BxInstruction_t *i); - BX_SMF void PADDSW_PqQq(BxInstruction_t *i); - BX_SMF void PXOR_PqQq(BxInstruction_t *i); - BX_SMF void PSLLW_PqQq(BxInstruction_t *i); - BX_SMF void PSLLD_PqQq(BxInstruction_t *i); - BX_SMF void PSLLQ_PqQq(BxInstruction_t *i); - BX_SMF void PMADDWD_PqQq(BxInstruction_t *i); - BX_SMF void PSUBB_PqQq(BxInstruction_t *i); - BX_SMF void PSUBW_PqQq(BxInstruction_t *i); - BX_SMF void PSUBD_PqQq(BxInstruction_t *i); - BX_SMF void PADDB_PqQq(BxInstruction_t *i); - BX_SMF void PADDW_PqQq(BxInstruction_t *i); - BX_SMF void PADDD_PqQq(BxInstruction_t *i); - BX_SMF void PSRLW_PqIb(BxInstruction_t *i); - BX_SMF void PSRAW_PqIb(BxInstruction_t *i); - BX_SMF void PSLLW_PqIb(BxInstruction_t *i); - BX_SMF void PSRLD_PqIb(BxInstruction_t *i); - BX_SMF void PSRAD_PqIb(BxInstruction_t *i); - BX_SMF void PSLLD_PqIb(BxInstruction_t *i); - BX_SMF void PSRLQ_PqIb(BxInstruction_t *i); - BX_SMF void PSLLQ_PqIb(BxInstruction_t *i); + BX_SMF void PUNPCKLBW_PqQd(bxInstruction_c *i); + BX_SMF void PUNPCKLWD_PqQd(bxInstruction_c *i); + BX_SMF void PUNPCKLDQ_PqQd(bxInstruction_c *i); + BX_SMF void PACKSSWB_PqQq(bxInstruction_c *i); + BX_SMF void PCMPGTB_PqQq(bxInstruction_c *i); + BX_SMF void PCMPGTW_PqQq(bxInstruction_c *i); + BX_SMF void PCMPGTD_PqQq(bxInstruction_c *i); + BX_SMF void PACKUSWB_PqQq(bxInstruction_c *i); + BX_SMF void PUNPCKHBW_PqQq(bxInstruction_c *i); + BX_SMF void PUNPCKHWD_PqQq(bxInstruction_c *i); + BX_SMF void PUNPCKHDQ_PqQq(bxInstruction_c *i); + BX_SMF void PACKSSDW_PqQq(bxInstruction_c *i); + BX_SMF void MOVD_PqEd(bxInstruction_c *i); + BX_SMF void MOVQ_PqQq(bxInstruction_c *i); + BX_SMF void PCMPEQB_PqQq(bxInstruction_c *i); + BX_SMF void PCMPEQW_PqQq(bxInstruction_c *i); + BX_SMF void PCMPEQD_PqQq(bxInstruction_c *i); + BX_SMF void EMMS(bxInstruction_c *i); + BX_SMF void MOVD_EdPd(bxInstruction_c *i); + BX_SMF void MOVQ_QqPq(bxInstruction_c *i); + BX_SMF void PSRLW_PqQq(bxInstruction_c *i); + BX_SMF void PSRLD_PqQq(bxInstruction_c *i); + BX_SMF void PSRLQ_PqQq(bxInstruction_c *i); + BX_SMF void PMULLW_PqQq(bxInstruction_c *i); + BX_SMF void PSUBUSB_PqQq(bxInstruction_c *i); + BX_SMF void PSUBUSW_PqQq(bxInstruction_c *i); + BX_SMF void PAND_PqQq(bxInstruction_c *i); + BX_SMF void PADDUSB_PqQq(bxInstruction_c *i); + BX_SMF void PADDUSW_PqQq(bxInstruction_c *i); + BX_SMF void PANDN_PqQq(bxInstruction_c *i); + BX_SMF void PSRAW_PqQq(bxInstruction_c *i); + BX_SMF void PSRAD_PqQq(bxInstruction_c *i); + BX_SMF void PMULHW_PqQq(bxInstruction_c *i); + BX_SMF void PSUBSB_PqQq(bxInstruction_c *i); + BX_SMF void PSUBSW_PqQq(bxInstruction_c *i); + BX_SMF void POR_PqQq(bxInstruction_c *i); + BX_SMF void PADDSB_PqQq(bxInstruction_c *i); + BX_SMF void PADDSW_PqQq(bxInstruction_c *i); + BX_SMF void PXOR_PqQq(bxInstruction_c *i); + BX_SMF void PSLLW_PqQq(bxInstruction_c *i); + BX_SMF void PSLLD_PqQq(bxInstruction_c *i); + BX_SMF void PSLLQ_PqQq(bxInstruction_c *i); + BX_SMF void PMADDWD_PqQq(bxInstruction_c *i); + BX_SMF void PSUBB_PqQq(bxInstruction_c *i); + BX_SMF void PSUBW_PqQq(bxInstruction_c *i); + BX_SMF void PSUBD_PqQq(bxInstruction_c *i); + BX_SMF void PADDB_PqQq(bxInstruction_c *i); + BX_SMF void PADDW_PqQq(bxInstruction_c *i); + BX_SMF void PADDD_PqQq(bxInstruction_c *i); + BX_SMF void PSRLW_PqIb(bxInstruction_c *i); + BX_SMF void PSRAW_PqIb(bxInstruction_c *i); + BX_SMF void PSLLW_PqIb(bxInstruction_c *i); + BX_SMF void PSRLD_PqIb(bxInstruction_c *i); + BX_SMF void PSRAD_PqIb(bxInstruction_c *i); + BX_SMF void PSLLD_PqIb(bxInstruction_c *i); + BX_SMF void PSRLQ_PqIb(bxInstruction_c *i); + BX_SMF void PSLLQ_PqIb(bxInstruction_c *i); /* MMX */ #if BX_SUPPORT_MMX @@ -1661,383 +1692,383 @@ union { BX_SMF void PrintMmxRegisters(void); #endif - BX_SMF void fpu_execute(BxInstruction_t *i); + BX_SMF void fpu_execute(bxInstruction_c *i); BX_SMF void fpu_init(void); BX_SMF void fpu_print_regs (void); - BX_SMF void CMPXCHG_XBTS(BxInstruction_t *); - BX_SMF void CMPXCHG_IBTS(BxInstruction_t *); - BX_SMF void CMPXCHG_EbGb(BxInstruction_t *); - BX_SMF void CMPXCHG_EdGd(BxInstruction_t *); - BX_SMF void CMPXCHG8B(BxInstruction_t *); - BX_SMF void XADD_EbGb(BxInstruction_t *); - BX_SMF void XADD_EdGd(BxInstruction_t *); - BX_SMF void RETnear32_Iw(BxInstruction_t *); - BX_SMF void RETnear16_Iw(BxInstruction_t *); - BX_SMF void RETfar32_Iw(BxInstruction_t *); - BX_SMF void RETfar16_Iw(BxInstruction_t *); + BX_SMF void CMPXCHG_XBTS(bxInstruction_c *); + BX_SMF void CMPXCHG_IBTS(bxInstruction_c *); + BX_SMF void CMPXCHG_EbGb(bxInstruction_c *); + BX_SMF void CMPXCHG_EdGd(bxInstruction_c *); + BX_SMF void CMPXCHG8B(bxInstruction_c *); + BX_SMF void XADD_EbGb(bxInstruction_c *); + BX_SMF void XADD_EdGd(bxInstruction_c *); + BX_SMF void RETnear32_Iw(bxInstruction_c *); + BX_SMF void RETnear16_Iw(bxInstruction_c *); + BX_SMF void RETfar32_Iw(bxInstruction_c *); + BX_SMF void RETfar16_Iw(bxInstruction_c *); - BX_SMF void LOADALL(BxInstruction_t *); - BX_SMF void CMOV_GdEd(BxInstruction_t *); - BX_SMF void CMOV_GwEw(BxInstruction_t *); + BX_SMF void LOADALL(bxInstruction_c *); + BX_SMF void CMOV_GdEd(bxInstruction_c *); + BX_SMF void CMOV_GwEw(bxInstruction_c *); - BX_SMF void ADD_EwGw(BxInstruction_t *); - BX_SMF void ADD_GwEw(BxInstruction_t *); - BX_SMF void ADD_AXIw(BxInstruction_t *); - BX_SMF void ADC_EwGw(BxInstruction_t *); - BX_SMF void ADC_GwEw(BxInstruction_t *); - BX_SMF void ADC_AXIw(BxInstruction_t *); - BX_SMF void SBB_EwGw(BxInstruction_t *); - BX_SMF void SBB_GwEw(BxInstruction_t *); - BX_SMF void SBB_AXIw(BxInstruction_t *); - BX_SMF void SBB_EwIw(BxInstruction_t *); - BX_SMF void SUB_EwGw(BxInstruction_t *); - BX_SMF void SUB_GwEw(BxInstruction_t *); - BX_SMF void SUB_AXIw(BxInstruction_t *); - BX_SMF void CMP_EwGw(BxInstruction_t *); - BX_SMF void CMP_GwEw(BxInstruction_t *); - BX_SMF void CMP_AXIw(BxInstruction_t *); - BX_SMF void CWDE(BxInstruction_t *); - BX_SMF void CDQ(BxInstruction_t *); - BX_SMF void XADD_EwGw(BxInstruction_t *); - BX_SMF void ADD_EwIw(BxInstruction_t *); - BX_SMF void ADC_EwIw(BxInstruction_t *); - BX_SMF void SUB_EwIw(BxInstruction_t *); - BX_SMF void CMP_EwIw(BxInstruction_t *); - BX_SMF void NEG_Ew(BxInstruction_t *); - BX_SMF void INC_Ew(BxInstruction_t *); - BX_SMF void DEC_Ew(BxInstruction_t *); - BX_SMF void CMPXCHG_EwGw(BxInstruction_t *); - BX_SMF void MUL_AXEw(BxInstruction_t *); - BX_SMF void IMUL_AXEw(BxInstruction_t *); - BX_SMF void DIV_AXEw(BxInstruction_t *); - BX_SMF void IDIV_AXEw(BxInstruction_t *); - BX_SMF void IMUL_GwEwIw(BxInstruction_t *); - BX_SMF void IMUL_GwEw(BxInstruction_t *); - BX_SMF void NOP(BxInstruction_t *); - BX_SMF void MOV_RLIb(BxInstruction_t *); - BX_SMF void MOV_RHIb(BxInstruction_t *); - BX_SMF void MOV_RXIw(BxInstruction_t *); - BX_SMF void MOV_ERXId(BxInstruction_t *); - BX_SMF void INC_RX(BxInstruction_t *); - BX_SMF void DEC_RX(BxInstruction_t *); - BX_SMF void INC_ERX(BxInstruction_t *); - BX_SMF void DEC_ERX(BxInstruction_t *); - BX_SMF void PUSH_RX(BxInstruction_t *); - BX_SMF void POP_RX(BxInstruction_t *); - BX_SMF void PUSH_ERX(BxInstruction_t *); - BX_SMF void POP_ERX(BxInstruction_t *); - BX_SMF void POP_Ew(BxInstruction_t *); - BX_SMF void POP_Ed(BxInstruction_t *); - BX_SMF void XCHG_RXAX(BxInstruction_t *); - BX_SMF void XCHG_ERXEAX(BxInstruction_t *); + BX_SMF void ADD_EwGw(bxInstruction_c *); + BX_SMF void ADD_GwEw(bxInstruction_c *); + BX_SMF void ADD_AXIw(bxInstruction_c *); + BX_SMF void ADC_EwGw(bxInstruction_c *); + BX_SMF void ADC_GwEw(bxInstruction_c *); + BX_SMF void ADC_AXIw(bxInstruction_c *); + BX_SMF void SBB_EwGw(bxInstruction_c *); + BX_SMF void SBB_GwEw(bxInstruction_c *); + BX_SMF void SBB_AXIw(bxInstruction_c *); + BX_SMF void SBB_EwIw(bxInstruction_c *); + BX_SMF void SUB_EwGw(bxInstruction_c *); + BX_SMF void SUB_GwEw(bxInstruction_c *); + BX_SMF void SUB_AXIw(bxInstruction_c *); + BX_SMF void CMP_EwGw(bxInstruction_c *); + BX_SMF void CMP_GwEw(bxInstruction_c *); + BX_SMF void CMP_AXIw(bxInstruction_c *); + BX_SMF void CWDE(bxInstruction_c *); + BX_SMF void CDQ(bxInstruction_c *); + BX_SMF void XADD_EwGw(bxInstruction_c *); + BX_SMF void ADD_EwIw(bxInstruction_c *); + BX_SMF void ADC_EwIw(bxInstruction_c *); + BX_SMF void SUB_EwIw(bxInstruction_c *); + BX_SMF void CMP_EwIw(bxInstruction_c *); + BX_SMF void NEG_Ew(bxInstruction_c *); + BX_SMF void INC_Ew(bxInstruction_c *); + BX_SMF void DEC_Ew(bxInstruction_c *); + BX_SMF void CMPXCHG_EwGw(bxInstruction_c *); + BX_SMF void MUL_AXEw(bxInstruction_c *); + BX_SMF void IMUL_AXEw(bxInstruction_c *); + BX_SMF void DIV_AXEw(bxInstruction_c *); + BX_SMF void IDIV_AXEw(bxInstruction_c *); + BX_SMF void IMUL_GwEwIw(bxInstruction_c *); + BX_SMF void IMUL_GwEw(bxInstruction_c *); + BX_SMF void NOP(bxInstruction_c *); + BX_SMF void MOV_RLIb(bxInstruction_c *); + BX_SMF void MOV_RHIb(bxInstruction_c *); + BX_SMF void MOV_RXIw(bxInstruction_c *); + BX_SMF void MOV_ERXId(bxInstruction_c *); + BX_SMF void INC_RX(bxInstruction_c *); + BX_SMF void DEC_RX(bxInstruction_c *); + BX_SMF void INC_ERX(bxInstruction_c *); + BX_SMF void DEC_ERX(bxInstruction_c *); + BX_SMF void PUSH_RX(bxInstruction_c *); + BX_SMF void POP_RX(bxInstruction_c *); + BX_SMF void PUSH_ERX(bxInstruction_c *); + BX_SMF void POP_ERX(bxInstruction_c *); + BX_SMF void POP_Ew(bxInstruction_c *); + BX_SMF void POP_Ed(bxInstruction_c *); + BX_SMF void XCHG_RXAX(bxInstruction_c *); + BX_SMF void XCHG_ERXEAX(bxInstruction_c *); #if BX_SUPPORT_X86_64 // 64 bit extensions - BX_SMF void ADD_EqGq(BxInstruction_t *); - BX_SMF void ADD_GqEq(BxInstruction_t *); - BX_SMF void ADD_RAXId(BxInstruction_t *); - BX_SMF void OR_EqGq(BxInstruction_t *); - BX_SMF void OR_GqEq(BxInstruction_t *); - BX_SMF void OR_RAXId(BxInstruction_t *); + BX_SMF void ADD_EqGq(bxInstruction_c *); + BX_SMF void ADD_GqEq(bxInstruction_c *); + BX_SMF void ADD_RAXId(bxInstruction_c *); + BX_SMF void OR_EqGq(bxInstruction_c *); + BX_SMF void OR_GqEq(bxInstruction_c *); + BX_SMF void OR_RAXId(bxInstruction_c *); - BX_SMF void ADC_EqGq(BxInstruction_t *); - BX_SMF void ADC_GqEq(BxInstruction_t *); - BX_SMF void ADC_RAXId(BxInstruction_t *); - BX_SMF void SBB_EqGq(BxInstruction_t *); - BX_SMF void SBB_GqEq(BxInstruction_t *); - BX_SMF void SBB_RAXId(BxInstruction_t *); + BX_SMF void ADC_EqGq(bxInstruction_c *); + BX_SMF void ADC_GqEq(bxInstruction_c *); + BX_SMF void ADC_RAXId(bxInstruction_c *); + BX_SMF void SBB_EqGq(bxInstruction_c *); + BX_SMF void SBB_GqEq(bxInstruction_c *); + BX_SMF void SBB_RAXId(bxInstruction_c *); - BX_SMF void AND_EqGq(BxInstruction_t *); - BX_SMF void AND_GqEq(BxInstruction_t *); - BX_SMF void AND_RAXId(BxInstruction_t *); - BX_SMF void SUB_EqGq(BxInstruction_t *); - BX_SMF void SUB_GqEq(BxInstruction_t *); - BX_SMF void SUB_RAXId(BxInstruction_t *); + BX_SMF void AND_EqGq(bxInstruction_c *); + BX_SMF void AND_GqEq(bxInstruction_c *); + BX_SMF void AND_RAXId(bxInstruction_c *); + BX_SMF void SUB_EqGq(bxInstruction_c *); + BX_SMF void SUB_GqEq(bxInstruction_c *); + BX_SMF void SUB_RAXId(bxInstruction_c *); - BX_SMF void XOR_EqGq(BxInstruction_t *); - BX_SMF void XOR_GqEq(BxInstruction_t *); - BX_SMF void XOR_RAXId(BxInstruction_t *); - BX_SMF void CMP_EqGq(BxInstruction_t *); - BX_SMF void CMP_GqEq(BxInstruction_t *); - BX_SMF void CMP_RAXId(BxInstruction_t *); + BX_SMF void XOR_EqGq(bxInstruction_c *); + BX_SMF void XOR_GqEq(bxInstruction_c *); + BX_SMF void XOR_RAXId(bxInstruction_c *); + BX_SMF void CMP_EqGq(bxInstruction_c *); + BX_SMF void CMP_GqEq(bxInstruction_c *); + BX_SMF void CMP_RAXId(bxInstruction_c *); - BX_SMF void PUSHAD64(BxInstruction_t *); - BX_SMF void POPAD64(BxInstruction_t *); - BX_SMF void PUSH64_Id(BxInstruction_t *); - BX_SMF void IMUL_GqEqId(BxInstruction_t *); + BX_SMF void PUSHAD64(bxInstruction_c *); + BX_SMF void POPAD64(bxInstruction_c *); + BX_SMF void PUSH64_Id(bxInstruction_c *); + BX_SMF void IMUL_GqEqId(bxInstruction_c *); - BX_SMF void TEST_EqGq(BxInstruction_t *); - BX_SMF void XCHG_EqGq(BxInstruction_t *); - BX_SMF void MOV_EqGq(BxInstruction_t *); - BX_SMF void MOV_GqEq(BxInstruction_t *); - BX_SMF void LEA_GqM(BxInstruction_t *); + BX_SMF void TEST_EqGq(bxInstruction_c *); + BX_SMF void XCHG_EqGq(bxInstruction_c *); + BX_SMF void MOV_EqGq(bxInstruction_c *); + BX_SMF void MOV_GqEq(bxInstruction_c *); + BX_SMF void LEA_GqM(bxInstruction_c *); - BX_SMF void CALL64_Ap(BxInstruction_t *); + BX_SMF void CALL64_Ap(bxInstruction_c *); - BX_SMF void MOV_RAXOq(BxInstruction_t *); - BX_SMF void MOV_OqRAX(BxInstruction_t *); - BX_SMF void MOV_EAXOq(BxInstruction_t *); - BX_SMF void MOV_OqEAX(BxInstruction_t *); - BX_SMF void MOV_AXOq(BxInstruction_t *); - BX_SMF void MOV_OqAX(BxInstruction_t *); - BX_SMF void MOV_ALOq(BxInstruction_t *); - BX_SMF void MOV_OqAL(BxInstruction_t *); + BX_SMF void MOV_RAXOq(bxInstruction_c *); + BX_SMF void MOV_OqRAX(bxInstruction_c *); + BX_SMF void MOV_EAXOq(bxInstruction_c *); + BX_SMF void MOV_OqEAX(bxInstruction_c *); + BX_SMF void MOV_AXOq(bxInstruction_c *); + BX_SMF void MOV_OqAX(bxInstruction_c *); + BX_SMF void MOV_ALOq(bxInstruction_c *); + BX_SMF void MOV_OqAL(bxInstruction_c *); - BX_SMF void TEST_RAXId(BxInstruction_t *); + BX_SMF void TEST_RAXId(bxInstruction_c *); - BX_SMF void RETnear64(BxInstruction_t *); - BX_SMF void MOV_EqId(BxInstruction_t *); - BX_SMF void ENTER64_IwIb(BxInstruction_t *); - BX_SMF void LEAVE64(BxInstruction_t *); - BX_SMF void RETfar64(BxInstruction_t *); + BX_SMF void RETnear64(bxInstruction_c *); + BX_SMF void MOV_EqId(bxInstruction_c *); + BX_SMF void ENTER64_IwIb(bxInstruction_c *); + BX_SMF void LEAVE64(bxInstruction_c *); + BX_SMF void RETfar64(bxInstruction_c *); - BX_SMF void IRET64(BxInstruction_t *); + BX_SMF void IRET64(bxInstruction_c *); - //BX_SMF void IN_eAXIb(BxInstruction_t *); - //BX_SMF void OUT_IbeAX(BxInstruction_t *); - BX_SMF void CALL_Aq(BxInstruction_t *); - BX_SMF void JMP_Jq(BxInstruction_t *); - //BX_SMF void IN_eAXDX(BxInstruction_t *); - //BX_SMF void OUT_DXeAX(BxInstruction_t *); + //BX_SMF void IN_eAXIb(bxInstruction_c *); + //BX_SMF void OUT_IbeAX(bxInstruction_c *); + BX_SMF void CALL_Aq(bxInstruction_c *); + BX_SMF void JMP_Jq(bxInstruction_c *); + //BX_SMF void IN_eAXDX(bxInstruction_c *); + //BX_SMF void OUT_DXeAX(bxInstruction_c *); - BX_SMF void MOV_CqRq(BxInstruction_t *); - BX_SMF void MOV_DqRq(BxInstruction_t *); - BX_SMF void MOV_RqCq(BxInstruction_t *); - BX_SMF void MOV_RqDq(BxInstruction_t *); - BX_SMF void MOV_TqRq(BxInstruction_t *); - BX_SMF void MOV_RqTq(BxInstruction_t *); + BX_SMF void MOV_CqRq(bxInstruction_c *); + BX_SMF void MOV_DqRq(bxInstruction_c *); + BX_SMF void MOV_RqCq(bxInstruction_c *); + BX_SMF void MOV_RqDq(bxInstruction_c *); + BX_SMF void MOV_TqRq(bxInstruction_c *); + BX_SMF void MOV_RqTq(bxInstruction_c *); - BX_SMF void JCC_Jq(BxInstruction_t *); + BX_SMF void JCC_Jq(bxInstruction_c *); - BX_SMF void SHLD_EqGq(BxInstruction_t *); + BX_SMF void SHLD_EqGq(bxInstruction_c *); - BX_SMF void SHRD_EqGq(BxInstruction_t *); + BX_SMF void SHRD_EqGq(bxInstruction_c *); - BX_SMF void IMUL_GqEq(BxInstruction_t *); + BX_SMF void IMUL_GqEq(bxInstruction_c *); - BX_SMF void MOVZX_GqEb(BxInstruction_t *); - BX_SMF void MOVZX_GqEw(BxInstruction_t *); - BX_SMF void MOVSX_GqEb(BxInstruction_t *); - BX_SMF void MOVSX_GqEw(BxInstruction_t *); - BX_SMF void MOVSX_GqEd(BxInstruction_t *); + BX_SMF void MOVZX_GqEb(bxInstruction_c *); + BX_SMF void MOVZX_GqEw(bxInstruction_c *); + BX_SMF void MOVSX_GqEb(bxInstruction_c *); + BX_SMF void MOVSX_GqEw(bxInstruction_c *); + BX_SMF void MOVSX_GqEd(bxInstruction_c *); - BX_SMF void BSWAP_RAX(BxInstruction_t *); - BX_SMF void BSWAP_RCX(BxInstruction_t *); - BX_SMF void BSWAP_RDX(BxInstruction_t *); - BX_SMF void BSWAP_RBX(BxInstruction_t *); - BX_SMF void BSWAP_RSP(BxInstruction_t *); - BX_SMF void BSWAP_RBP(BxInstruction_t *); - BX_SMF void BSWAP_RSI(BxInstruction_t *); - BX_SMF void BSWAP_RDI(BxInstruction_t *); + BX_SMF void BSWAP_RAX(bxInstruction_c *); + BX_SMF void BSWAP_RCX(bxInstruction_c *); + BX_SMF void BSWAP_RDX(bxInstruction_c *); + BX_SMF void BSWAP_RBX(bxInstruction_c *); + BX_SMF void BSWAP_RSP(bxInstruction_c *); + BX_SMF void BSWAP_RBP(bxInstruction_c *); + BX_SMF void BSWAP_RSI(bxInstruction_c *); + BX_SMF void BSWAP_RDI(bxInstruction_c *); - BX_SMF void ADD_EqId(BxInstruction_t *); - BX_SMF void OR_EqId(BxInstruction_t *); - BX_SMF void ADC_EqId(BxInstruction_t *); - BX_SMF void SBB_EqId(BxInstruction_t *); - BX_SMF void AND_EqId(BxInstruction_t *); - BX_SMF void SUB_EqId(BxInstruction_t *); - BX_SMF void XOR_EqId(BxInstruction_t *); - BX_SMF void CMP_EqId(BxInstruction_t *); + BX_SMF void ADD_EqId(bxInstruction_c *); + BX_SMF void OR_EqId(bxInstruction_c *); + BX_SMF void ADC_EqId(bxInstruction_c *); + BX_SMF void SBB_EqId(bxInstruction_c *); + BX_SMF void AND_EqId(bxInstruction_c *); + BX_SMF void SUB_EqId(bxInstruction_c *); + BX_SMF void XOR_EqId(bxInstruction_c *); + BX_SMF void CMP_EqId(bxInstruction_c *); - BX_SMF void ROL_Eq(BxInstruction_t *); - BX_SMF void ROR_Eq(BxInstruction_t *); - BX_SMF void RCL_Eq(BxInstruction_t *); - BX_SMF void RCR_Eq(BxInstruction_t *); - BX_SMF void SHL_Eq(BxInstruction_t *); - BX_SMF void SHR_Eq(BxInstruction_t *); - BX_SMF void SAR_Eq(BxInstruction_t *); + BX_SMF void ROL_Eq(bxInstruction_c *); + BX_SMF void ROR_Eq(bxInstruction_c *); + BX_SMF void RCL_Eq(bxInstruction_c *); + BX_SMF void RCR_Eq(bxInstruction_c *); + BX_SMF void SHL_Eq(bxInstruction_c *); + BX_SMF void SHR_Eq(bxInstruction_c *); + BX_SMF void SAR_Eq(bxInstruction_c *); - BX_SMF void TEST_EqId(BxInstruction_t *); - BX_SMF void NOT_Eq(BxInstruction_t *); - BX_SMF void NEG_Eq(BxInstruction_t *); - BX_SMF void MUL_RAXEq(BxInstruction_t *); - BX_SMF void IMUL_RAXEq(BxInstruction_t *); - BX_SMF void DIV_RAXEq(BxInstruction_t *); - BX_SMF void IDIV_RAXEq(BxInstruction_t *); + BX_SMF void TEST_EqId(bxInstruction_c *); + BX_SMF void NOT_Eq(bxInstruction_c *); + BX_SMF void NEG_Eq(bxInstruction_c *); + BX_SMF void MUL_RAXEq(bxInstruction_c *); + BX_SMF void IMUL_RAXEq(bxInstruction_c *); + BX_SMF void DIV_RAXEq(bxInstruction_c *); + BX_SMF void IDIV_RAXEq(bxInstruction_c *); - BX_SMF void INC_Eq(BxInstruction_t *); - BX_SMF void DEC_Eq(BxInstruction_t *); - BX_SMF void CALL_Eq(BxInstruction_t *); - BX_SMF void CALL64_Ep(BxInstruction_t *); - BX_SMF void JMP_Eq(BxInstruction_t *); - BX_SMF void JMP64_Ep(BxInstruction_t *); - BX_SMF void PUSH_Eq(BxInstruction_t *); + BX_SMF void INC_Eq(bxInstruction_c *); + BX_SMF void DEC_Eq(bxInstruction_c *); + BX_SMF void CALL_Eq(bxInstruction_c *); + BX_SMF void CALL64_Ep(bxInstruction_c *); + BX_SMF void JMP_Eq(bxInstruction_c *); + BX_SMF void JMP64_Ep(bxInstruction_c *); + BX_SMF void PUSH_Eq(bxInstruction_c *); - BX_SMF void CMPXCHG_EqGq(BxInstruction_t *); - BX_SMF void CDQE(BxInstruction_t *); - BX_SMF void CQO(BxInstruction_t *); - BX_SMF void XADD_EqGq(BxInstruction_t *); - BX_SMF void RETnear64_Iw(BxInstruction_t *); - BX_SMF void RETfar64_Iw(BxInstruction_t *); + BX_SMF void CMPXCHG_EqGq(bxInstruction_c *); + BX_SMF void CDQE(bxInstruction_c *); + BX_SMF void CQO(bxInstruction_c *); + BX_SMF void XADD_EqGq(bxInstruction_c *); + BX_SMF void RETnear64_Iw(bxInstruction_c *); + BX_SMF void RETfar64_Iw(bxInstruction_c *); - BX_SMF void CMOV_GqEq(BxInstruction_t *); + BX_SMF void CMOV_GqEq(bxInstruction_c *); - BX_SMF void MOV_RRXIq(BxInstruction_t *); - BX_SMF void INC_RRX(BxInstruction_t *); - BX_SMF void DEC_RRX(BxInstruction_t *); - BX_SMF void PUSH_RRX(BxInstruction_t *); - BX_SMF void POP_RRX(BxInstruction_t *); - BX_SMF void POP_Eq(BxInstruction_t *); - BX_SMF void XCHG_RRXRAX(BxInstruction_t *); + BX_SMF void MOV_RRXIq(bxInstruction_c *); + BX_SMF void INC_RRX(bxInstruction_c *); + BX_SMF void DEC_RRX(bxInstruction_c *); + BX_SMF void PUSH_RRX(bxInstruction_c *); + BX_SMF void POP_RRX(bxInstruction_c *); + BX_SMF void POP_Eq(bxInstruction_c *); + BX_SMF void XCHG_RRXRAX(bxInstruction_c *); - BX_SMF void PUSH64_CS(BxInstruction_t *); - BX_SMF void PUSH64_DS(BxInstruction_t *); - BX_SMF void POP64_DS(BxInstruction_t *); - BX_SMF void PUSH64_ES(BxInstruction_t *); - BX_SMF void POP64_ES(BxInstruction_t *); - BX_SMF void PUSH64_FS(BxInstruction_t *); - BX_SMF void POP64_FS(BxInstruction_t *); - BX_SMF void PUSH64_GS(BxInstruction_t *); - BX_SMF void POP64_GS(BxInstruction_t *); - BX_SMF void PUSH64_SS(BxInstruction_t *); - BX_SMF void POP64_SS(BxInstruction_t *); + BX_SMF void PUSH64_CS(bxInstruction_c *); + BX_SMF void PUSH64_DS(bxInstruction_c *); + BX_SMF void POP64_DS(bxInstruction_c *); + BX_SMF void PUSH64_ES(bxInstruction_c *); + BX_SMF void POP64_ES(bxInstruction_c *); + BX_SMF void PUSH64_FS(bxInstruction_c *); + BX_SMF void POP64_FS(bxInstruction_c *); + BX_SMF void PUSH64_GS(bxInstruction_c *); + BX_SMF void POP64_GS(bxInstruction_c *); + BX_SMF void PUSH64_SS(bxInstruction_c *); + BX_SMF void POP64_SS(bxInstruction_c *); #endif // #if BX_SUPPORT_X86_64 // mch added - BX_SMF void INVLPG(BxInstruction_t *); + BX_SMF void INVLPG(bxInstruction_c *); BX_SMF void wait_for_interrupt(); - BX_SMF void RSM(BxInstruction_t *); + BX_SMF void RSM(bxInstruction_c *); - BX_SMF void WRMSR(BxInstruction_t *); - BX_SMF void RDTSC(BxInstruction_t *); - BX_SMF void RDMSR(BxInstruction_t *); + BX_SMF void WRMSR(bxInstruction_c *); + BX_SMF void RDTSC(bxInstruction_c *); + BX_SMF void RDMSR(bxInstruction_c *); BX_SMF void SetCR0(Bit32u val_32); #if BX_CPU_LEVEL >= 4 BX_SMF void SetCR4(Bit32u val_32); #endif BX_SMF void dynamic_translate(void); BX_SMF void dynamic_init(void); - BX_SMF unsigned FetchDecode(Bit8u *, BxInstruction_t *, unsigned, Boolean); + BX_SMF unsigned FetchDecode(Bit8u *, bxInstruction_c *, unsigned, Boolean); #if BX_SUPPORT_X86_64 - BX_SMF unsigned FetchDecode64(Bit8u *, BxInstruction_t *, unsigned); + BX_SMF unsigned FetchDecode64(Bit8u *, bxInstruction_c *, unsigned); #endif - BX_SMF void UndefinedOpcode(BxInstruction_t *); - BX_SMF void BxError(BxInstruction_t *i); - BX_SMF void BxResolveError(BxInstruction_t *i); + BX_SMF void UndefinedOpcode(bxInstruction_c *); + BX_SMF void BxError(bxInstruction_c *i); + BX_SMF void BxResolveError(bxInstruction_c *i); - BX_SMF void Resolve16Mod0Rm0(BxInstruction_t *); - BX_SMF void Resolve16Mod0Rm1(BxInstruction_t *); - BX_SMF void Resolve16Mod0Rm2(BxInstruction_t *); - BX_SMF void Resolve16Mod0Rm3(BxInstruction_t *); - BX_SMF void Resolve16Mod0Rm4(BxInstruction_t *); - BX_SMF void Resolve16Mod0Rm5(BxInstruction_t *); - BX_SMF void Resolve16Mod0Rm7(BxInstruction_t *); + BX_SMF void Resolve16Mod0Rm0(bxInstruction_c *); + BX_SMF void Resolve16Mod0Rm1(bxInstruction_c *); + BX_SMF void Resolve16Mod0Rm2(bxInstruction_c *); + BX_SMF void Resolve16Mod0Rm3(bxInstruction_c *); + BX_SMF void Resolve16Mod0Rm4(bxInstruction_c *); + BX_SMF void Resolve16Mod0Rm5(bxInstruction_c *); + BX_SMF void Resolve16Mod0Rm7(bxInstruction_c *); - BX_SMF void Resolve16Mod1or2Rm0(BxInstruction_t *); - BX_SMF void Resolve16Mod1or2Rm1(BxInstruction_t *); - BX_SMF void Resolve16Mod1or2Rm2(BxInstruction_t *); - BX_SMF void Resolve16Mod1or2Rm3(BxInstruction_t *); - BX_SMF void Resolve16Mod1or2Rm4(BxInstruction_t *); - BX_SMF void Resolve16Mod1or2Rm5(BxInstruction_t *); - BX_SMF void Resolve16Mod1or2Rm6(BxInstruction_t *); - BX_SMF void Resolve16Mod1or2Rm7(BxInstruction_t *); + BX_SMF void Resolve16Mod1or2Rm0(bxInstruction_c *); + BX_SMF void Resolve16Mod1or2Rm1(bxInstruction_c *); + BX_SMF void Resolve16Mod1or2Rm2(bxInstruction_c *); + BX_SMF void Resolve16Mod1or2Rm3(bxInstruction_c *); + BX_SMF void Resolve16Mod1or2Rm4(bxInstruction_c *); + BX_SMF void Resolve16Mod1or2Rm5(bxInstruction_c *); + BX_SMF void Resolve16Mod1or2Rm6(bxInstruction_c *); + BX_SMF void Resolve16Mod1or2Rm7(bxInstruction_c *); - BX_SMF void Resolve32Mod0Rm0(BxInstruction_t *); - BX_SMF void Resolve32Mod0Rm1(BxInstruction_t *); - BX_SMF void Resolve32Mod0Rm2(BxInstruction_t *); - BX_SMF void Resolve32Mod0Rm3(BxInstruction_t *); - BX_SMF void Resolve32Mod0Rm6(BxInstruction_t *); - BX_SMF void Resolve32Mod0Rm7(BxInstruction_t *); + BX_SMF void Resolve32Mod0Rm0(bxInstruction_c *); + BX_SMF void Resolve32Mod0Rm1(bxInstruction_c *); + BX_SMF void Resolve32Mod0Rm2(bxInstruction_c *); + BX_SMF void Resolve32Mod0Rm3(bxInstruction_c *); + BX_SMF void Resolve32Mod0Rm6(bxInstruction_c *); + BX_SMF void Resolve32Mod0Rm7(bxInstruction_c *); - BX_SMF void Resolve32Mod1or2Rm0(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Rm1(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Rm2(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Rm3(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Rm5(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Rm6(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Rm7(BxInstruction_t *); + BX_SMF void Resolve32Mod1or2Rm0(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Rm1(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Rm2(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Rm3(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Rm5(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Rm6(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Rm7(bxInstruction_c *); - BX_SMF void Resolve32Mod0Base0(BxInstruction_t *); - BX_SMF void Resolve32Mod0Base1(BxInstruction_t *); - BX_SMF void Resolve32Mod0Base2(BxInstruction_t *); - BX_SMF void Resolve32Mod0Base3(BxInstruction_t *); - BX_SMF void Resolve32Mod0Base4(BxInstruction_t *); - BX_SMF void Resolve32Mod0Base5(BxInstruction_t *); - BX_SMF void Resolve32Mod0Base6(BxInstruction_t *); - BX_SMF void Resolve32Mod0Base7(BxInstruction_t *); + BX_SMF void Resolve32Mod0Base0(bxInstruction_c *); + BX_SMF void Resolve32Mod0Base1(bxInstruction_c *); + BX_SMF void Resolve32Mod0Base2(bxInstruction_c *); + BX_SMF void Resolve32Mod0Base3(bxInstruction_c *); + BX_SMF void Resolve32Mod0Base4(bxInstruction_c *); + BX_SMF void Resolve32Mod0Base5(bxInstruction_c *); + BX_SMF void Resolve32Mod0Base6(bxInstruction_c *); + BX_SMF void Resolve32Mod0Base7(bxInstruction_c *); - BX_SMF void Resolve32Mod1or2Base0(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Base1(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Base2(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Base3(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Base4(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Base5(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Base6(BxInstruction_t *); - BX_SMF void Resolve32Mod1or2Base7(BxInstruction_t *); + BX_SMF void Resolve32Mod1or2Base0(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Base1(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Base2(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Base3(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Base4(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Base5(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Base6(bxInstruction_c *); + BX_SMF void Resolve32Mod1or2Base7(bxInstruction_c *); #if BX_SUPPORT_X86_64 // 64 bit addressing - BX_SMF void Resolve64Mod0Rm0(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm1(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm2(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm3(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm5(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm6(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm7(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm8(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm9(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm10(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm11(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm12(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm13(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm14(BxInstruction_t *); - BX_SMF void Resolve64Mod0Rm15(BxInstruction_t *); + BX_SMF void Resolve64Mod0Rm0(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm1(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm2(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm3(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm5(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm6(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm7(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm8(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm9(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm10(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm11(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm12(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm13(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm14(bxInstruction_c *); + BX_SMF void Resolve64Mod0Rm15(bxInstruction_c *); - BX_SMF void Resolve64Mod1or2Rm0(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm1(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm2(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm3(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm5(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm6(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm7(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm8(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm9(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm10(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm11(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm12(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm13(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm14(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Rm15(BxInstruction_t *); + BX_SMF void Resolve64Mod1or2Rm0(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm1(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm2(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm3(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm5(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm6(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm7(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm8(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm9(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm10(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm11(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm12(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm13(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm14(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Rm15(bxInstruction_c *); - BX_SMF void Resolve64Mod0Base0(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base1(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base2(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base3(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base4(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base5(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base6(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base7(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base8(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base9(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base10(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base11(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base12(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base13(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base14(BxInstruction_t *); - BX_SMF void Resolve64Mod0Base15(BxInstruction_t *); + BX_SMF void Resolve64Mod0Base0(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base1(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base2(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base3(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base4(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base5(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base6(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base7(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base8(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base9(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base10(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base11(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base12(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base13(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base14(bxInstruction_c *); + BX_SMF void Resolve64Mod0Base15(bxInstruction_c *); - BX_SMF void Resolve64Mod1or2Base0(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base1(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base2(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base3(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base4(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base5(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base6(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base7(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base8(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base9(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base10(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base11(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base12(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base13(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base14(BxInstruction_t *); - BX_SMF void Resolve64Mod1or2Base15(BxInstruction_t *); + BX_SMF void Resolve64Mod1or2Base0(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base1(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base2(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base3(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base4(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base5(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base6(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base7(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base8(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base9(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base10(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base11(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base12(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base13(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base14(bxInstruction_c *); + BX_SMF void Resolve64Mod1or2Base15(bxInstruction_c *); #endif // #if BX_SUPPORT_X86_64 @@ -2122,14 +2153,14 @@ union { BX_SMF void reset(unsigned source); - BX_SMF void jump_protected(BxInstruction_t *, Bit16u cs, bx_address disp); - BX_SMF void call_protected(BxInstruction_t *, Bit16u cs, bx_address disp); - BX_SMF void return_protected(BxInstruction_t *, Bit16u pop_bytes); - BX_SMF void iret_protected(BxInstruction_t *); + BX_SMF void jump_protected(bxInstruction_c *, Bit16u cs, bx_address disp); + BX_SMF void call_protected(bxInstruction_c *, Bit16u cs, bx_address disp); + BX_SMF void return_protected(bxInstruction_c *, Bit16u pop_bytes); + BX_SMF void iret_protected(bxInstruction_c *); BX_SMF void validate_seg_regs(void); BX_SMF void stack_return_to_v86(Bit32u new_eip, Bit32u raw_cs_selector, Bit32u flags32); - BX_SMF void stack_return_from_v86(BxInstruction_t *); + BX_SMF void stack_return_from_v86(bxInstruction_c *); BX_SMF void init_v8086_mode(void); BX_SMF void v8086_message(void); BX_SMF void task_switch(bx_selector_t *selector, @@ -2318,6 +2349,7 @@ BX_SMF BX_CPP_INLINE Bit32u BX_CPU_C_PREFIX get_segment_base(unsigned seg) { return (BX_CPU_THIS_PTR sregs[seg].cache.u.segment.base); } + #if BX_CPU_LEVEL >= 2 BX_CPP_INLINE Boolean BX_CPU_C::real_mode(void) { return( !BX_CPU_THIS_PTR cr0.pe ); }; #endif diff --git a/bochs/cpu/ctrl_xfer16.cc b/bochs/cpu/ctrl_xfer16.cc index 3f984731a..dd5779f5e 100644 --- a/bochs/cpu/ctrl_xfer16.cc +++ b/bochs/cpu/ctrl_xfer16.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: ctrl_xfer16.cc,v 1.8 2002-09-17 14:36:39 sshwarts Exp $ +// $Id: ctrl_xfer16.cc,v 1.9 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -36,7 +36,7 @@ void -BX_CPU_C::RETnear16_Iw(BxInstruction_t *i) +BX_CPU_C::RETnear16_Iw(bxInstruction_c *i) { Bit16u imm16; Bit32u temp_ESP; @@ -51,7 +51,7 @@ BX_CPU_C::RETnear16_Iw(BxInstruction_t *i) else temp_ESP = SP; - imm16 = i->Iw; + imm16 = i->Iw(); invalidate_prefetch_q(); @@ -93,7 +93,7 @@ BX_CPU_C::RETnear16_Iw(BxInstruction_t *i) } void -BX_CPU_C::RETnear16(BxInstruction_t *i) +BX_CPU_C::RETnear16(bxInstruction_c *i) { Bit32u temp_ESP; Bit16u return_IP; @@ -138,7 +138,7 @@ BX_CPU_C::RETnear16(BxInstruction_t *i) } void -BX_CPU_C::RETfar16_Iw(BxInstruction_t *i) +BX_CPU_C::RETfar16_Iw(bxInstruction_c *i) { Bit16s imm16; Bit16u ip, cs_raw; @@ -149,7 +149,7 @@ BX_CPU_C::RETfar16_Iw(BxInstruction_t *i) /* ??? is imm16, number of bytes/words depending on operandsize ? */ - imm16 = i->Iw; + imm16 = i->Iw(); invalidate_prefetch_q(); @@ -176,7 +176,7 @@ done: } void -BX_CPU_C::RETfar16(BxInstruction_t *i) +BX_CPU_C::RETfar16(bxInstruction_c *i) { Bit16u ip, cs_raw; @@ -206,7 +206,7 @@ done: void -BX_CPU_C::CALL_Aw(BxInstruction_t *i) +BX_CPU_C::CALL_Aw(bxInstruction_c *i) { Bit32u new_EIP; @@ -216,7 +216,7 @@ BX_CPU_C::CALL_Aw(BxInstruction_t *i) invalidate_prefetch_q(); - new_EIP = EIP + (Bit32s) i->Id; + new_EIP = EIP + (Bit32s) i->Id(); new_EIP &= 0x0000ffff; #if BX_CPU_LEVEL >= 2 if ( protected_mode() && @@ -235,7 +235,7 @@ BX_CPU_C::CALL_Aw(BxInstruction_t *i) } void -BX_CPU_C::CALL16_Ap(BxInstruction_t *i) +BX_CPU_C::CALL16_Ap(bxInstruction_c *i) { Bit16u cs_raw; Bit16u disp16; @@ -244,8 +244,8 @@ BX_CPU_C::CALL16_Ap(BxInstruction_t *i) BX_CPU_THIS_PTR show_flag |= Flag_call; #endif - disp16 = i->Iw; - cs_raw = i->Iw2; + disp16 = i->Iw(); + cs_raw = i->Iw2(); invalidate_prefetch_q(); #if BX_CPU_LEVEL >= 2 @@ -265,7 +265,7 @@ done: } void -BX_CPU_C::CALL_Ew(BxInstruction_t *i) +BX_CPU_C::CALL_Ew(bxInstruction_c *i) { Bit32u temp_ESP; Bit16u op1_16; @@ -281,8 +281,8 @@ BX_CPU_C::CALL_Ew(BxInstruction_t *i) /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -310,7 +310,7 @@ BX_CPU_C::CALL_Ew(BxInstruction_t *i) } void -BX_CPU_C::CALL16_Ep(BxInstruction_t *i) +BX_CPU_C::CALL16_Ep(bxInstruction_c *i) { Bit16u cs_raw; Bit16u op1_16; @@ -320,7 +320,7 @@ BX_CPU_C::CALL16_Ep(BxInstruction_t *i) #endif /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_PANIC(("CALL_Ep: op1 is a register")); } @@ -347,14 +347,14 @@ done: void -BX_CPU_C::JMP_Jw(BxInstruction_t *i) +BX_CPU_C::JMP_Jw(bxInstruction_c *i) { Bit32u new_EIP; invalidate_prefetch_q(); - new_EIP = EIP + (Bit32s) i->Id; + new_EIP = EIP + (Bit32s) i->Id(); new_EIP &= 0x0000ffff; #if BX_CPU_LEVEL >= 2 @@ -371,7 +371,7 @@ BX_CPU_C::JMP_Jw(BxInstruction_t *i) } void -BX_CPU_C::JCC_Jw(BxInstruction_t *i) +BX_CPU_C::JCC_Jw(bxInstruction_c *i) { Boolean condition = 0; @@ -400,7 +400,7 @@ BX_CPU_C::JCC_Jw(BxInstruction_t *i) if (condition) { Bit32u new_EIP; - new_EIP = EIP + (Bit32s) i->Id; + new_EIP = EIP + (Bit32s) i->Id(); new_EIP &= 0x0000ffff; #if BX_CPU_LEVEL >= 2 if (protected_mode()) { @@ -424,15 +424,15 @@ BX_CPU_C::JCC_Jw(BxInstruction_t *i) void -BX_CPU_C::JMP_Ew(BxInstruction_t *i) +BX_CPU_C::JMP_Ew(bxInstruction_c *i) { Bit32u new_EIP; Bit16u op1_16; /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -459,13 +459,13 @@ BX_CPU_C::JMP_Ew(BxInstruction_t *i) /* Far indirect jump */ void -BX_CPU_C::JMP16_Ep(BxInstruction_t *i) +BX_CPU_C::JMP16_Ep(bxInstruction_c *i) { Bit16u cs_raw; Bit16u op1_16; /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { /* far indirect must specify a memory address */ BX_PANIC(("JMP_Ep(): op1 is a register")); } @@ -491,7 +491,7 @@ done: } void -BX_CPU_C::IRET16(BxInstruction_t *i) +BX_CPU_C::IRET16(bxInstruction_c *i) { Bit16u ip, cs_raw, flags; diff --git a/bochs/cpu/ctrl_xfer32.cc b/bochs/cpu/ctrl_xfer32.cc index 4c40ec5f0..e67258593 100644 --- a/bochs/cpu/ctrl_xfer32.cc +++ b/bochs/cpu/ctrl_xfer32.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: ctrl_xfer32.cc,v 1.11 2002-09-17 14:36:39 sshwarts Exp $ +// $Id: ctrl_xfer32.cc,v 1.12 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -36,7 +36,7 @@ void -BX_CPU_C::RETnear32_Iw(BxInstruction_t *i) +BX_CPU_C::RETnear32_Iw(bxInstruction_c *i) { Bit16u imm16; Bit32u temp_ESP; @@ -51,7 +51,7 @@ BX_CPU_C::RETnear32_Iw(BxInstruction_t *i) else temp_ESP = SP; - imm16 = i->Iw; + imm16 = i->Iw(); invalidate_prefetch_q(); @@ -96,7 +96,7 @@ BX_CPU_C::RETnear32_Iw(BxInstruction_t *i) } void -BX_CPU_C::RETnear32(BxInstruction_t *i) +BX_CPU_C::RETnear32(bxInstruction_c *i) { Bit32u temp_ESP; Bit32u return_EIP; @@ -141,7 +141,7 @@ BX_CPU_C::RETnear32(BxInstruction_t *i) } void -BX_CPU_C::RETfar32_Iw(BxInstruction_t *i) +BX_CPU_C::RETfar32_Iw(bxInstruction_c *i) { Bit32u eip, ecs_raw; Bit16s imm16; @@ -151,7 +151,7 @@ BX_CPU_C::RETfar32_Iw(BxInstruction_t *i) #endif /* ??? is imm16, number of bytes/words depending on operandsize ? */ - imm16 = i->Iw; + imm16 = i->Iw(); invalidate_prefetch_q(); @@ -178,7 +178,7 @@ done: } void -BX_CPU_C::RETfar32(BxInstruction_t *i) +BX_CPU_C::RETfar32(bxInstruction_c *i) { Bit32u eip, ecs_raw; @@ -209,7 +209,7 @@ done: void -BX_CPU_C::CALL_Ad(BxInstruction_t *i) +BX_CPU_C::CALL_Ad(bxInstruction_c *i) { Bit32u new_EIP; Bit32s disp32; @@ -218,7 +218,7 @@ BX_CPU_C::CALL_Ad(BxInstruction_t *i) BX_CPU_THIS_PTR show_flag |= Flag_call; #endif - disp32 = i->Id; + disp32 = i->Id(); invalidate_prefetch_q(); new_EIP = EIP + disp32; @@ -238,7 +238,7 @@ BX_CPU_C::CALL_Ad(BxInstruction_t *i) } void -BX_CPU_C::CALL32_Ap(BxInstruction_t *i) +BX_CPU_C::CALL32_Ap(bxInstruction_c *i) { Bit16u cs_raw; Bit32u disp32; @@ -247,8 +247,8 @@ BX_CPU_C::CALL32_Ap(BxInstruction_t *i) BX_CPU_THIS_PTR show_flag |= Flag_call; #endif - disp32 = i->Id; - cs_raw = i->Iw2; + disp32 = i->Id(); + cs_raw = i->Iw2(); invalidate_prefetch_q(); if (protected_mode()) { @@ -266,7 +266,7 @@ done: } void -BX_CPU_C::CALL_Ed(BxInstruction_t *i) +BX_CPU_C::CALL_Ed(bxInstruction_c *i) { Bit32u temp_ESP; Bit32u op1_32; @@ -282,8 +282,8 @@ BX_CPU_C::CALL_Ed(BxInstruction_t *i) /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { read_virtual_dword(i->seg, i->rm_addr, &op1_32); @@ -308,7 +308,7 @@ BX_CPU_C::CALL_Ed(BxInstruction_t *i) } void -BX_CPU_C::CALL32_Ep(BxInstruction_t *i) +BX_CPU_C::CALL32_Ep(bxInstruction_c *i) { Bit16u cs_raw; Bit32u op1_32; @@ -318,7 +318,7 @@ BX_CPU_C::CALL32_Ep(BxInstruction_t *i) #endif /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_PANIC(("CALL_Ep: op1 is a register")); } @@ -345,13 +345,13 @@ done: void -BX_CPU_C::JMP_Jd(BxInstruction_t *i) +BX_CPU_C::JMP_Jd(bxInstruction_c *i) { Bit32u new_EIP; invalidate_prefetch_q(); - new_EIP = EIP + (Bit32s) i->Id; + new_EIP = EIP + (Bit32s) i->Id(); #if BX_CPU_LEVEL >= 2 if (protected_mode()) { @@ -367,7 +367,7 @@ BX_CPU_C::JMP_Jd(BxInstruction_t *i) } void -BX_CPU_C::JCC_Jd(BxInstruction_t *i) +BX_CPU_C::JCC_Jd(bxInstruction_c *i) { Boolean condition = 0; @@ -396,7 +396,7 @@ BX_CPU_C::JCC_Jd(BxInstruction_t *i) if (condition) { Bit32u new_EIP; - new_EIP = EIP + (Bit32s) i->Id; + new_EIP = EIP + (Bit32s) i->Id(); #if BX_CPU_LEVEL >= 2 if (protected_mode()) { if ( new_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) { @@ -417,7 +417,7 @@ BX_CPU_C::JCC_Jd(BxInstruction_t *i) } void -BX_CPU_C::JMP_Ap(BxInstruction_t *i) +BX_CPU_C::JMP_Ap(bxInstruction_c *i) { Bit32u disp32; Bit16u cs_raw; @@ -425,12 +425,12 @@ BX_CPU_C::JMP_Ap(BxInstruction_t *i) invalidate_prefetch_q(); if (i->os_32) { - disp32 = i->Id; + disp32 = i->Id(); } else { - disp32 = i->Iw; + disp32 = i->Iw(); } - cs_raw = i->Iw2; + cs_raw = i->Iw2(); #if BX_CPU_LEVEL >= 2 if (protected_mode()) { @@ -451,14 +451,14 @@ done: void -BX_CPU_C::JMP_Ed(BxInstruction_t *i) +BX_CPU_C::JMP_Ed(bxInstruction_c *i) { Bit32u new_EIP; Bit32u op1_32; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -485,13 +485,13 @@ BX_CPU_C::JMP_Ed(BxInstruction_t *i) /* Far indirect jump */ void -BX_CPU_C::JMP32_Ep(BxInstruction_t *i) +BX_CPU_C::JMP32_Ep(bxInstruction_c *i) { Bit16u cs_raw; Bit32u op1_32; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { /* far indirect must specify a memory address */ BX_PANIC(("JMP_Ep(): op1 is a register")); } @@ -515,7 +515,7 @@ done: } void -BX_CPU_C::IRET32(BxInstruction_t *i) +BX_CPU_C::IRET32(bxInstruction_c *i) { Bit32u eip, ecs_raw, eflags; diff --git a/bochs/cpu/ctrl_xfer64.cc b/bochs/cpu/ctrl_xfer64.cc index f45468088..532cbe1c1 100644 --- a/bochs/cpu/ctrl_xfer64.cc +++ b/bochs/cpu/ctrl_xfer64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: ctrl_xfer64.cc,v 1.4 2002-09-17 14:36:39 sshwarts Exp $ +// $Id: ctrl_xfer64.cc,v 1.5 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -36,7 +36,7 @@ void -BX_CPU_C::RETnear64_Iw(BxInstruction_t *i) +BX_CPU_C::RETnear64_Iw(bxInstruction_c *i) { Bit16u imm16; Bit64u temp_RSP; @@ -48,7 +48,7 @@ BX_CPU_C::RETnear64_Iw(BxInstruction_t *i) temp_RSP = RSP; - imm16 = i->Iw; + imm16 = i->Iw(); invalidate_prefetch_q(); @@ -74,7 +74,7 @@ BX_CPU_C::RETnear64_Iw(BxInstruction_t *i) } void -BX_CPU_C::RETnear64(BxInstruction_t *i) +BX_CPU_C::RETnear64(bxInstruction_c *i) { Bit64u temp_RSP; Bit64u return_RIP; @@ -102,7 +102,7 @@ BX_CPU_C::RETnear64(BxInstruction_t *i) } void -BX_CPU_C::RETfar64_Iw(BxInstruction_t *i) +BX_CPU_C::RETfar64_Iw(bxInstruction_c *i) { Bit64u rip, rcs_raw; Bit16s imm16; @@ -112,7 +112,7 @@ BX_CPU_C::RETfar64_Iw(BxInstruction_t *i) #endif /* ??? is imm16, number of bytes/words depending on operandsize ? */ - imm16 = i->Iw; + imm16 = i->Iw(); invalidate_prefetch_q(); @@ -135,7 +135,7 @@ done: } void -BX_CPU_C::RETfar64(BxInstruction_t *i) +BX_CPU_C::RETfar64(bxInstruction_c *i) { Bit64u rip, rcs_raw; @@ -166,7 +166,7 @@ done: void -BX_CPU_C::CALL_Aq(BxInstruction_t *i) +BX_CPU_C::CALL_Aq(bxInstruction_c *i) { Bit64u new_RIP; Bit32s disp32; @@ -175,7 +175,7 @@ BX_CPU_C::CALL_Aq(BxInstruction_t *i) BX_CPU_THIS_PTR show_flag |= Flag_call; #endif - disp32 = i->Id; + disp32 = i->Id(); invalidate_prefetch_q(); new_RIP = RIP + disp32; @@ -188,7 +188,7 @@ BX_CPU_C::CALL_Aq(BxInstruction_t *i) } void -BX_CPU_C::CALL64_Ap(BxInstruction_t *i) +BX_CPU_C::CALL64_Ap(bxInstruction_c *i) { Bit16u cs_raw; Bit32u disp32; @@ -197,8 +197,8 @@ BX_CPU_C::CALL64_Ap(BxInstruction_t *i) BX_CPU_THIS_PTR show_flag |= Flag_call; #endif - disp32 = i->Id; - cs_raw = i->Iw2; + disp32 = i->Id(); + cs_raw = i->Iw2(); invalidate_prefetch_q(); if (protected_mode()) { @@ -216,7 +216,7 @@ done: } void -BX_CPU_C::CALL_Eq(BxInstruction_t *i) +BX_CPU_C::CALL_Eq(bxInstruction_c *i) { Bit64u temp_RSP; Bit64u op1_64; @@ -229,8 +229,8 @@ BX_CPU_C::CALL_Eq(BxInstruction_t *i) /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { read_virtual_qword(i->seg, i->rm_addr, &op1_64); @@ -249,7 +249,7 @@ BX_CPU_C::CALL_Eq(BxInstruction_t *i) } void -BX_CPU_C::CALL64_Ep(BxInstruction_t *i) +BX_CPU_C::CALL64_Ep(bxInstruction_c *i) { Bit16u cs_raw; Bit64u op1_64; @@ -259,7 +259,7 @@ BX_CPU_C::CALL64_Ep(BxInstruction_t *i) #endif /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_PANIC(("CALL_Ep: op1 is a register")); } @@ -286,18 +286,18 @@ done: void -BX_CPU_C::JMP_Jq(BxInstruction_t *i) +BX_CPU_C::JMP_Jq(bxInstruction_c *i) { Bit64u new_RIP; invalidate_prefetch_q(); - RIP += (Bit32s) i->Id; + RIP += (Bit32s) i->Id(); BX_INSTR_UCNEAR_BRANCH(BX_INSTR_IS_JMP, new_RIP); } void -BX_CPU_C::JCC_Jq(BxInstruction_t *i) +BX_CPU_C::JCC_Jq(bxInstruction_c *i) { Boolean condition = 0; @@ -325,7 +325,7 @@ BX_CPU_C::JCC_Jq(BxInstruction_t *i) if (condition) { - RIP += (Bit32s) i->Id; + RIP += (Bit32s) i->Id(); BX_INSTR_CNEAR_BRANCH_TAKEN(RIP); revalidate_prefetch_q(); } @@ -338,7 +338,7 @@ BX_CPU_C::JCC_Jq(BxInstruction_t *i) #ifdef ignore void -BX_CPU_C::JMP64_Ap(BxInstruction_t *i) +BX_CPU_C::JMP64_Ap(bxInstruction_c *i) { Bit64u disp64; Bit16u cs_raw; @@ -346,12 +346,12 @@ BX_CPU_C::JMP64_Ap(BxInstruction_t *i) invalidate_prefetch_q(); if (i->os_32) { - disp64 = (Bit32s) i->Id; + disp64 = (Bit32s) i->Id(); } else { - disp64 = (Bit16s) i->Iw; + disp64 = (Bit16s) i->Iw(); } - cs_raw = i->Iw2; + cs_raw = i->Iw2(); #if BX_CPU_LEVEL >= 2 if (protected_mode()) { @@ -373,14 +373,14 @@ done: void -BX_CPU_C::JMP_Eq(BxInstruction_t *i) +BX_CPU_C::JMP_Eq(bxInstruction_c *i) { Bit64u new_RIP; Bit64u op1_64; /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -397,13 +397,13 @@ BX_CPU_C::JMP_Eq(BxInstruction_t *i) /* Far indirect jump */ void -BX_CPU_C::JMP64_Ep(BxInstruction_t *i) +BX_CPU_C::JMP64_Ep(bxInstruction_c *i) { Bit16u cs_raw; Bit64u op1_64; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { /* far indirect must specify a memory address */ BX_PANIC(("JMP_Ep(): op1 is a register")); } @@ -427,7 +427,7 @@ done: } void -BX_CPU_C::IRET64(BxInstruction_t *i) +BX_CPU_C::IRET64(bxInstruction_c *i) { Bit32u rip, ecs_raw, eflags; diff --git a/bochs/cpu/ctrl_xfer8.cc b/bochs/cpu/ctrl_xfer8.cc index fbe8975ed..59abdfc38 100644 --- a/bochs/cpu/ctrl_xfer8.cc +++ b/bochs/cpu/ctrl_xfer8.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: ctrl_xfer8.cc,v 1.8 2002-09-14 17:29:47 kevinlawton Exp $ +// $Id: ctrl_xfer8.cc,v 1.9 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -40,12 +40,12 @@ void -BX_CPU_C::JCXZ_Jb(BxInstruction_t *i) +BX_CPU_C::JCXZ_Jb(bxInstruction_c *i) { if (i->as_64) { if ( RCX == 0 ) { - RIP += (Bit32s) i->Id; + RIP += (Bit32s) i->Id(); BX_INSTR_CNEAR_BRANCH_TAKEN(new_RIP); revalidate_prefetch_q(); } @@ -66,7 +66,7 @@ BX_CPU_C::JCXZ_Jb(BxInstruction_t *i) if ( temp_ECX == 0 ) { Bit32u new_EIP; - new_EIP = EIP + (Bit32s) i->Id; + new_EIP = EIP + (Bit32s) i->Id(); if (i->os_32==0) new_EIP &= 0x0000ffff; #if BX_CPU_LEVEL >= 2 @@ -92,13 +92,13 @@ BX_CPU_C::JCXZ_Jb(BxInstruction_t *i) void -BX_CPU_C::LOOPNE_Jb(BxInstruction_t *i) +BX_CPU_C::LOOPNE_Jb(bxInstruction_c *i) { if (i->as_64) { if ( ((--RCX)!=0) && (get_ZF()==0) ) { - RIP += (Bit32s) i->Id; + RIP += (Bit32s) i->Id(); BX_INSTR_CNEAR_BRANCH_TAKEN(RIP); revalidate_prefetch_q(); } @@ -121,7 +121,7 @@ BX_CPU_C::LOOPNE_Jb(BxInstruction_t *i) count--; if ( (count!=0) && (get_ZF()==0) ) { - new_EIP = EIP + (Bit32s) i->Id; + new_EIP = EIP + (Bit32s) i->Id(); if (i->os_32==0) new_EIP &= 0x0000ffff; if (protected_mode()) { @@ -148,13 +148,13 @@ BX_CPU_C::LOOPNE_Jb(BxInstruction_t *i) } void -BX_CPU_C::LOOPE_Jb(BxInstruction_t *i) +BX_CPU_C::LOOPE_Jb(bxInstruction_c *i) { if (i->as_64) { if ( ((--RCX)!=0) && (get_ZF()) ) { - RIP += (Bit32s) i->Id; + RIP += (Bit32s) i->Id(); BX_INSTR_CNEAR_BRANCH_TAKEN(RIP); revalidate_prefetch_q(); } @@ -177,7 +177,7 @@ BX_CPU_C::LOOPE_Jb(BxInstruction_t *i) count--; if ( (count!=0) && get_ZF()) { - new_EIP = EIP + (Bit32s) i->Id; + new_EIP = EIP + (Bit32s) i->Id(); if (i->os_32==0) new_EIP &= 0x0000ffff; if (protected_mode()) { @@ -204,13 +204,13 @@ BX_CPU_C::LOOPE_Jb(BxInstruction_t *i) } void -BX_CPU_C::LOOP_Jb(BxInstruction_t *i) +BX_CPU_C::LOOP_Jb(bxInstruction_c *i) { if (i->as_64) { if ( ((--RCX)!=0) ) { - RIP += (Bit32s) i->Id; + RIP += (Bit32s) i->Id(); BX_INSTR_CNEAR_BRANCH_TAKEN(RIP); revalidate_prefetch_q(); } @@ -233,7 +233,7 @@ BX_CPU_C::LOOP_Jb(BxInstruction_t *i) count--; if (count != 0) { - new_EIP = EIP + (Bit32s) i->Id; + new_EIP = EIP + (Bit32s) i->Id(); if (i->os_32==0) new_EIP &= 0x0000ffff; if (protected_mode()) { diff --git a/bochs/cpu/ctrl_xfer_pro.cc b/bochs/cpu/ctrl_xfer_pro.cc index 4f3c8dbd6..1866aab52 100644 --- a/bochs/cpu/ctrl_xfer_pro.cc +++ b/bochs/cpu/ctrl_xfer_pro.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: ctrl_xfer_pro.cc,v 1.14 2002-09-15 02:23:12 kevinlawton Exp $ +// $Id: ctrl_xfer_pro.cc,v 1.15 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -40,7 +40,7 @@ #if BX_CPU_LEVEL >= 2 void -BX_CPU_C::jump_protected(BxInstruction_t *i, Bit16u cs_raw, bx_address dispBig) +BX_CPU_C::jump_protected(bxInstruction_c *i, Bit16u cs_raw, bx_address dispBig) { bx_descriptor_t descriptor; bx_selector_t selector; @@ -455,7 +455,7 @@ BX_CPU_C::jump_protected(BxInstruction_t *i, Bit16u cs_raw, bx_address dispBig) #if BX_CPU_LEVEL >= 2 void -BX_CPU_C::call_protected(BxInstruction_t *i, Bit16u cs_raw, bx_address dispBig) +BX_CPU_C::call_protected(bxInstruction_c *i, Bit16u cs_raw, bx_address dispBig) { bx_selector_t cs_selector; Bit32u dword1, dword2; @@ -1040,7 +1040,7 @@ BX_CPU_C::call_protected(BxInstruction_t *i, Bit16u cs_raw, bx_address dispBig) #if BX_CPU_LEVEL >= 2 void -BX_CPU_C::return_protected(BxInstruction_t *i, Bit16u pop_bytes) +BX_CPU_C::return_protected(bxInstruction_c *i, Bit16u pop_bytes) { Bit16u raw_cs_selector, raw_ss_selector; bx_selector_t cs_selector, ss_selector; @@ -1378,7 +1378,7 @@ BX_CPU_C::return_protected(BxInstruction_t *i, Bit16u pop_bytes) #if BX_CPU_LEVEL >= 2 void -BX_CPU_C::iret_protected(BxInstruction_t *i) +BX_CPU_C::iret_protected(bxInstruction_c *i) { Bit16u raw_cs_selector, raw_ss_selector; bx_selector_t cs_selector, ss_selector; diff --git a/bochs/cpu/data_xfer16.cc b/bochs/cpu/data_xfer16.cc index 4c86a2c1e..dc508a4b4 100644 --- a/bochs/cpu/data_xfer16.cc +++ b/bochs/cpu/data_xfer16.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: data_xfer16.cc,v 1.9 2002-09-14 17:29:47 kevinlawton Exp $ +// $Id: data_xfer16.cc,v 1.10 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -35,43 +35,46 @@ void -BX_CPU_C::MOV_RXIw(BxInstruction_t *i) +BX_CPU_C::MOV_RXIw(bxInstruction_c *i) { -#if BX_SUPPORT_X86_64 - BX_CPU_THIS_PTR gen_reg[i->nnn].word.rx = i->Iw; -#else - BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx = i->Iw; -#endif + BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].word.rx = i->Iw(); +//#if BX_SUPPORT_X86_64 +// BX_CPU_THIS_PTR gen_reg[i->nnn()].word.rx = i->Iw(); +//#else +// BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx = i->Iw(); +//#endif } void -BX_CPU_C::XCHG_RXAX(BxInstruction_t *i) +BX_CPU_C::XCHG_RXAX(bxInstruction_c *i) { Bit16u temp16; temp16 = AX; -#if BX_SUPPORT_X86_64 - AX = BX_CPU_THIS_PTR gen_reg[i->nnn].word.rx; - BX_CPU_THIS_PTR gen_reg[i->nnn].word.rx = temp16; -#else - AX = BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx; - BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx = temp16; -#endif + AX = BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].word.rx; + BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].word.rx = temp16; +//#if BX_SUPPORT_X86_64 +// AX = BX_CPU_THIS_PTR gen_reg[i->nnn()].word.rx; +// BX_CPU_THIS_PTR gen_reg[i->nnn()].word.rx = temp16; +//#else +// AX = BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx; +// BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx = temp16; +//#endif } void -BX_CPU_C::MOV_EwGw(BxInstruction_t *i) +BX_CPU_C::MOV_EwGw(bxInstruction_c *i) { Bit16u op2_16; /* op2_16 is a register, op2_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ /* now write op2 to op1 */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, op2_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), op2_16); } else { write_virtual_word(i->seg, i->rm_addr, &op2_16); @@ -80,23 +83,23 @@ BX_CPU_C::MOV_EwGw(BxInstruction_t *i) void -BX_CPU_C::MOV_GwEw(BxInstruction_t *i) +BX_CPU_C::MOV_GwEw(bxInstruction_c *i) { Bit16u op2_16; - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_virtual_word(i->seg, i->rm_addr, &op2_16); } - BX_WRITE_16BIT_REG(i->nnn, op2_16); + BX_WRITE_16BIT_REG(i->nnn(), op2_16); } void -BX_CPU_C::MOV_EwSw(BxInstruction_t *i) +BX_CPU_C::MOV_EwSw(bxInstruction_c *i) { Bit16u seg_reg; @@ -104,15 +107,15 @@ BX_CPU_C::MOV_EwSw(BxInstruction_t *i) BX_PANIC(("MOV_EwSw: incomplete for CPU < 3")); #endif - seg_reg = BX_CPU_THIS_PTR sregs[i->nnn].selector.value; + seg_reg = BX_CPU_THIS_PTR sregs[i->nnn()].selector.value; - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { // ??? BX_WRITE_16BIT_REG(mem_addr, seg_reg); if ( i->os_32 ) { - BX_WRITE_32BIT_REGZ(i->rm, seg_reg); + BX_WRITE_32BIT_REGZ(i->rm(), seg_reg); } else { - BX_WRITE_16BIT_REG(i->rm, seg_reg); + BX_WRITE_16BIT_REG(i->rm(), seg_reg); } } else { @@ -121,7 +124,7 @@ BX_CPU_C::MOV_EwSw(BxInstruction_t *i) } void -BX_CPU_C::MOV_SwEw(BxInstruction_t *i) +BX_CPU_C::MOV_SwEw(bxInstruction_c *i) { Bit16u op2_16; @@ -129,16 +132,16 @@ BX_CPU_C::MOV_SwEw(BxInstruction_t *i) BX_PANIC(("MOV_SwEw: incomplete for CPU < 3")); #endif - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { read_virtual_word(i->seg, i->rm_addr, &op2_16); } - load_seg_reg(&BX_CPU_THIS_PTR sregs[i->nnn], op2_16); + load_seg_reg(&BX_CPU_THIS_PTR sregs[i->nnn()], op2_16); - if (i->nnn == BX_SEG_REG_SS) { + if (i->nnn() == BX_SEG_REG_SS) { // MOV SS inhibits interrupts, debug exceptions and single-step // trap exceptions until the execution boundary following the // next instruction is reached. @@ -150,25 +153,25 @@ BX_CPU_C::MOV_SwEw(BxInstruction_t *i) } void -BX_CPU_C::LEA_GwM(BxInstruction_t *i) +BX_CPU_C::LEA_GwM(bxInstruction_c *i) { - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_PANIC(("LEA_GvM: op2 is a register")); UndefinedOpcode(i); return; } - BX_WRITE_16BIT_REG(i->nnn, (Bit16u) i->rm_addr); + BX_WRITE_16BIT_REG(i->nnn(), (Bit16u) i->rm_addr); } void -BX_CPU_C::MOV_AXOw(BxInstruction_t *i) +BX_CPU_C::MOV_AXOw(bxInstruction_c *i) { Bit16u temp_16; bx_address addr; - addr = i->Id; + addr = i->Id(); /* read from memory address */ @@ -185,12 +188,12 @@ BX_CPU_C::MOV_AXOw(BxInstruction_t *i) void -BX_CPU_C::MOV_OwAX(BxInstruction_t *i) +BX_CPU_C::MOV_OwAX(bxInstruction_c *i) { Bit16u temp_16; bx_address addr; - addr = i->Id; + addr = i->Id(); /* read from register */ temp_16 = AX; @@ -207,15 +210,15 @@ BX_CPU_C::MOV_OwAX(BxInstruction_t *i) void -BX_CPU_C::MOV_EwIw(BxInstruction_t *i) +BX_CPU_C::MOV_EwIw(bxInstruction_c *i) { Bit16u op2_16; - op2_16 = i->Iw; + op2_16 = i->Iw(); /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, op2_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), op2_16); } else { write_virtual_word(i->seg, i->rm_addr, &op2_16); @@ -224,15 +227,15 @@ BX_CPU_C::MOV_EwIw(BxInstruction_t *i) void -BX_CPU_C::MOVZX_GwEb(BxInstruction_t *i) +BX_CPU_C::MOVZX_GwEb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVZX_GvEb: not supported on < 386")); #else Bit8u op2_8; - if (i->mod == 0xc0) { - op2_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -240,20 +243,20 @@ BX_CPU_C::MOVZX_GwEb(BxInstruction_t *i) } /* zero extend byte op2 into word op1 */ - BX_WRITE_16BIT_REG(i->nnn, (Bit16u) op2_8); + BX_WRITE_16BIT_REG(i->nnn(), (Bit16u) op2_8); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::MOVZX_GwEw(BxInstruction_t *i) +BX_CPU_C::MOVZX_GwEw(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVZX_GvEw: not supported on < 386")); #else Bit16u op2_16; - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -261,20 +264,20 @@ BX_CPU_C::MOVZX_GwEw(BxInstruction_t *i) } /* normal move */ - BX_WRITE_16BIT_REG(i->nnn, op2_16); + BX_WRITE_16BIT_REG(i->nnn(), op2_16); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::MOVSX_GwEb(BxInstruction_t *i) +BX_CPU_C::MOVSX_GwEb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVSX_GvEb: not supported on < 386")); #else Bit8u op2_8; - if (i->mod == 0xc0) { - op2_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -282,20 +285,20 @@ BX_CPU_C::MOVSX_GwEb(BxInstruction_t *i) } /* sign extend byte op2 into word op1 */ - BX_WRITE_16BIT_REG(i->nnn, (Bit8s) op2_8); + BX_WRITE_16BIT_REG(i->nnn(), (Bit8s) op2_8); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::MOVSX_GwEw(BxInstruction_t *i) +BX_CPU_C::MOVSX_GwEw(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVSX_GvEw: not supported on < 386")); #else Bit16u op2_16; - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -303,32 +306,32 @@ BX_CPU_C::MOVSX_GwEw(BxInstruction_t *i) } /* normal move */ - BX_WRITE_16BIT_REG(i->nnn, op2_16); + BX_WRITE_16BIT_REG(i->nnn(), op2_16); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::XCHG_EwGw(BxInstruction_t *i) +BX_CPU_C::XCHG_EwGw(bxInstruction_c *i) { Bit16u op2_16, op1_16; #ifdef MAGIC_BREAKPOINT #if BX_DEBUGGER // (mch) Magic break point - if (i->nnn == 3 && i->mod == 0xc0 && i->rm == 3) { + if (i->nnn() == 3 && i->mod() == 0xc0 && i->rm() == 3) { BX_CPU_THIS_PTR magic_break = 1; } #endif #endif /* op2_16 is a register, op2_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); - BX_WRITE_16BIT_REG(i->rm, op2_16); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); + BX_WRITE_16BIT_REG(i->rm(), op2_16); } else { /* pointer, segment address pair */ @@ -336,12 +339,12 @@ BX_CPU_C::XCHG_EwGw(BxInstruction_t *i) Write_RMW_virtual_word(op2_16); } - BX_WRITE_16BIT_REG(i->nnn, op1_16); + BX_WRITE_16BIT_REG(i->nnn(), op1_16); } void -BX_CPU_C::CMOV_GwEw(BxInstruction_t *i) +BX_CPU_C::CMOV_GwEw(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 6) || (BX_CPU_LEVEL_HACKED >= 6) // Note: CMOV accesses a memory source operand (read), regardless @@ -374,8 +377,8 @@ BX_CPU_C::CMOV_GwEw(BxInstruction_t *i) BX_PANIC(("CMOV_GwEw: default case")); } - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -383,7 +386,7 @@ BX_CPU_C::CMOV_GwEw(BxInstruction_t *i) } if (condition) { - BX_WRITE_16BIT_REG(i->nnn, op2_16); + BX_WRITE_16BIT_REG(i->nnn(), op2_16); } #else BX_INFO(("cmov_gwew called")); diff --git a/bochs/cpu/data_xfer32.cc b/bochs/cpu/data_xfer32.cc index 44d9b887c..af106cfe0 100644 --- a/bochs/cpu/data_xfer32.cc +++ b/bochs/cpu/data_xfer32.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: data_xfer32.cc,v 1.10 2002-09-14 17:29:47 kevinlawton Exp $ +// $Id: data_xfer32.cc,v 1.11 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -36,42 +36,48 @@ void -BX_CPU_C::XCHG_ERXEAX(BxInstruction_t *i) +BX_CPU_C::XCHG_ERXEAX(bxInstruction_c *i) { Bit32u temp32; temp32 = EAX; #if BX_SUPPORT_X86_64 - RAX = BX_CPU_THIS_PTR gen_reg[i->nnn].dword.erx; - BX_CPU_THIS_PTR gen_reg[i->nnn].dword.erx = temp32; + RAX = BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].dword.erx; + BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].dword.erx = temp32; + //RAX = BX_CPU_THIS_PTR gen_reg[i->nnn()].dword.erx; + //BX_CPU_THIS_PTR gen_reg[i->nnn()].dword.erx = temp32; #else - EAX = BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx; - BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx = temp32; + EAX = BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].dword.erx; + BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].dword.erx = temp32; + //EAX = BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx; + //BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx = temp32; #endif } void -BX_CPU_C::MOV_ERXId(BxInstruction_t *i) +BX_CPU_C::MOV_ERXId(bxInstruction_c *i) { #if BX_SUPPORT_X86_64 - BX_CPU_THIS_PTR gen_reg[i->nnn].rrx = i->Id; + BX_CPU_THIS_PTR gen_reg[(i->b1 & 0x07) + i->rex_b()].rrx = i->Id(); + //BX_CPU_THIS_PTR gen_reg[i->nnn()].rrx = i->Id(); #else - BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx = i->Id; + BX_CPU_THIS_PTR gen_reg[(i->b1 & 0x07) + i->rex_b()].dword.erx = i->Id(); + //BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx = i->Id(); #endif } void -BX_CPU_C::MOV_EdGd(BxInstruction_t *i) +BX_CPU_C::MOV_EdGd(bxInstruction_c *i) { Bit32u op2_32; /* op2_32 is a register, op2_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ /* now write op2 to op1 */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, op2_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), op2_32); } else { write_virtual_dword(i->seg, i->rm_addr, &op2_32); @@ -80,43 +86,43 @@ BX_CPU_C::MOV_EdGd(BxInstruction_t *i) void -BX_CPU_C::MOV_GdEd(BxInstruction_t *i) +BX_CPU_C::MOV_GdEd(bxInstruction_c *i) { Bit32u op2_32; - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_virtual_dword(i->seg, i->rm_addr, &op2_32); } - BX_WRITE_32BIT_REGZ(i->nnn, op2_32); + BX_WRITE_32BIT_REGZ(i->nnn(), op2_32); } void -BX_CPU_C::LEA_GdM(BxInstruction_t *i) +BX_CPU_C::LEA_GdM(bxInstruction_c *i) { - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_PANIC(("LEA_GvM: op2 is a register")); UndefinedOpcode(i); return; } /* write effective address of op2 in op1 */ - BX_WRITE_32BIT_REGZ(i->nnn, i->rm_addr); + BX_WRITE_32BIT_REGZ(i->nnn(), i->rm_addr); } void -BX_CPU_C::MOV_EAXOd(BxInstruction_t *i) +BX_CPU_C::MOV_EAXOd(bxInstruction_c *i) { Bit32u temp_32; bx_address addr; - addr = i->Id; + addr = i->Id(); /* read from memory address */ @@ -137,12 +143,12 @@ BX_CPU_C::MOV_EAXOd(BxInstruction_t *i) void -BX_CPU_C::MOV_OdEAX(BxInstruction_t *i) +BX_CPU_C::MOV_OdEAX(bxInstruction_c *i) { Bit32u temp_32; bx_address addr; - addr = i->Id; + addr = i->Id(); /* read from register */ temp_32 = EAX; @@ -159,15 +165,15 @@ BX_CPU_C::MOV_OdEAX(BxInstruction_t *i) void -BX_CPU_C::MOV_EdId(BxInstruction_t *i) +BX_CPU_C::MOV_EdId(bxInstruction_c *i) { Bit32u op2_32; - op2_32 = i->Id; + op2_32 = i->Id(); /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, op2_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), op2_32); } else { write_virtual_dword(i->seg, i->rm_addr, &op2_32); @@ -176,15 +182,15 @@ BX_CPU_C::MOV_EdId(BxInstruction_t *i) void -BX_CPU_C::MOVZX_GdEb(BxInstruction_t *i) +BX_CPU_C::MOVZX_GdEb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVZX_GvEb: not supported on < 386")); #else Bit8u op2_8; - if (i->mod == 0xc0) { - op2_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -192,20 +198,20 @@ BX_CPU_C::MOVZX_GdEb(BxInstruction_t *i) } /* zero extend byte op2 into dword op1 */ - BX_WRITE_32BIT_REGZ(i->nnn, (Bit32u) op2_8); + BX_WRITE_32BIT_REGZ(i->nnn(), (Bit32u) op2_8); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::MOVZX_GdEw(BxInstruction_t *i) +BX_CPU_C::MOVZX_GdEw(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVZX_GvEw: not supported on < 386")); #else Bit16u op2_16; - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -213,20 +219,20 @@ BX_CPU_C::MOVZX_GdEw(BxInstruction_t *i) } /* zero extend word op2 into dword op1 */ - BX_WRITE_32BIT_REGZ(i->nnn, (Bit32u) op2_16); + BX_WRITE_32BIT_REGZ(i->nnn(), (Bit32u) op2_16); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::MOVSX_GdEb(BxInstruction_t *i) +BX_CPU_C::MOVSX_GdEb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVSX_GvEb: not supported on < 386")); #else Bit8u op2_8; - if (i->mod == 0xc0) { - op2_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -234,20 +240,20 @@ BX_CPU_C::MOVSX_GdEb(BxInstruction_t *i) } /* sign extend byte op2 into dword op1 */ - BX_WRITE_32BIT_REGZ(i->nnn, (Bit8s) op2_8); + BX_WRITE_32BIT_REGZ(i->nnn(), (Bit8s) op2_8); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::MOVSX_GdEw(BxInstruction_t *i) +BX_CPU_C::MOVSX_GdEw(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVSX_GvEw: not supported on < 386")); #else Bit16u op2_16; - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -255,23 +261,23 @@ BX_CPU_C::MOVSX_GdEw(BxInstruction_t *i) } /* sign extend word op2 into dword op1 */ - BX_WRITE_32BIT_REGZ(i->nnn, (Bit16s) op2_16); + BX_WRITE_32BIT_REGZ(i->nnn(), (Bit16s) op2_16); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::XCHG_EdGd(BxInstruction_t *i) +BX_CPU_C::XCHG_EdGd(bxInstruction_c *i) { Bit32u op2_32, op1_32; /* op2_32 is a register, op2_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); - BX_WRITE_32BIT_REGZ(i->rm, op2_32); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); + BX_WRITE_32BIT_REGZ(i->rm(), op2_32); } else { /* pointer, segment address pair */ @@ -279,12 +285,12 @@ BX_CPU_C::XCHG_EdGd(BxInstruction_t *i) Write_RMW_virtual_dword(op2_32); } - BX_WRITE_32BIT_REGZ(i->nnn, op1_32); + BX_WRITE_32BIT_REGZ(i->nnn(), op1_32); } void -BX_CPU_C::CMOV_GdEd(BxInstruction_t *i) +BX_CPU_C::CMOV_GdEd(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 6) || (BX_CPU_LEVEL_HACKED >= 6) // Note: CMOV accesses a memory source operand (read), regardless @@ -318,8 +324,8 @@ BX_CPU_C::CMOV_GdEd(BxInstruction_t *i) BX_PANIC(("CMOV_GdEd: default case")); } - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -327,7 +333,7 @@ BX_CPU_C::CMOV_GdEd(BxInstruction_t *i) } if (condition) { - BX_WRITE_32BIT_REGZ(i->nnn, op2_32); + BX_WRITE_32BIT_REGZ(i->nnn(), op2_32); } #else BX_INFO(("cmov_gded called")); diff --git a/bochs/cpu/data_xfer64.cc b/bochs/cpu/data_xfer64.cc index 2e2f58fdc..0a6152a03 100644 --- a/bochs/cpu/data_xfer64.cc +++ b/bochs/cpu/data_xfer64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: data_xfer64.cc,v 1.2 2002-09-13 17:04:13 kevinlawton Exp $ +// $Id: data_xfer64.cc,v 1.3 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -36,33 +36,36 @@ void -BX_CPU_C::XCHG_RRXRAX(BxInstruction_t *i) +BX_CPU_C::XCHG_RRXRAX(bxInstruction_c *i) { Bit64u temp64; temp64 = RAX; - RAX = BX_CPU_THIS_PTR gen_reg[i->nnn].rrx; - BX_CPU_THIS_PTR gen_reg[i->nnn].rrx = temp64; + RAX = BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].rrx; + BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].rrx = temp64; + //RAX = BX_CPU_THIS_PTR gen_reg[i->nnn()].rrx; + //BX_CPU_THIS_PTR gen_reg[i->nnn()].rrx = temp64; } void -BX_CPU_C::MOV_RRXIq(BxInstruction_t *i) +BX_CPU_C::MOV_RRXIq(bxInstruction_c *i) { - BX_CPU_THIS_PTR gen_reg[i->nnn].rrx = i->Iq; + BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].rrx = i->Iq(); + //BX_CPU_THIS_PTR gen_reg[i->nnn()].rrx = i->Iq(); } void -BX_CPU_C::MOV_EqGq(BxInstruction_t *i) +BX_CPU_C::MOV_EqGq(bxInstruction_c *i) { Bit64u op2_64; /* op2_64 is a register, op2_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ /* now write op2 to op1 */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, op2_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), op2_64); } else { write_virtual_qword(i->seg, i->rm_addr, &op2_64); @@ -71,13 +74,13 @@ BX_CPU_C::MOV_EqGq(BxInstruction_t *i) void -BX_CPU_C::MOV_GqEq(BxInstruction_t *i) +BX_CPU_C::MOV_GqEq(bxInstruction_c *i) { Bit64u op2_64; - //BX_DEBUG (("MOV_GqEq mod=%02x nnn=%d rm=%d rm_addr=%08x seg=%d",i->mod,i->nnn,i->rm,i->rm_addr,i->seg)); - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + //BX_DEBUG (("MOV_GqEq mod=%02x nnn=%d rm=%d rm_addr=%08x seg=%d",i->mod(),i->nnn(),i->rm(),i->rm_addr,i->seg)); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -86,31 +89,31 @@ BX_CPU_C::MOV_GqEq(BxInstruction_t *i) //BX_DEBUG (("done read_virtual_qword")); } - BX_WRITE_64BIT_REG(i->nnn, op2_64); + BX_WRITE_64BIT_REG(i->nnn(), op2_64); } void -BX_CPU_C::LEA_GqM(BxInstruction_t *i) +BX_CPU_C::LEA_GqM(bxInstruction_c *i) { - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_PANIC(("LEA_GvM: op2 is a register")); UndefinedOpcode(i); return; } /* write effective address of op2 in op1 */ - BX_WRITE_64BIT_REG(i->nnn, i->rm_addr); + BX_WRITE_64BIT_REG(i->nnn(), i->rm_addr); } void -BX_CPU_C::MOV_ALOq(BxInstruction_t *i) +BX_CPU_C::MOV_ALOq(bxInstruction_c *i) { Bit8u temp_8; bx_address addr; - addr = i->Iq; + addr = i->Iq(); /* read from memory address */ @@ -127,12 +130,12 @@ BX_CPU_C::MOV_ALOq(BxInstruction_t *i) void -BX_CPU_C::MOV_OqAL(BxInstruction_t *i) +BX_CPU_C::MOV_OqAL(bxInstruction_c *i) { Bit8u temp_8; bx_address addr; - addr = i->Iq; + addr = i->Iq(); /* read from register */ temp_8 = AL; @@ -147,12 +150,12 @@ BX_CPU_C::MOV_OqAL(BxInstruction_t *i) } void -BX_CPU_C::MOV_AXOq(BxInstruction_t *i) +BX_CPU_C::MOV_AXOq(bxInstruction_c *i) { Bit16u temp_16; bx_address addr; - addr = i->Iq; + addr = i->Iq(); /* read from memory address */ @@ -169,12 +172,12 @@ BX_CPU_C::MOV_AXOq(BxInstruction_t *i) void -BX_CPU_C::MOV_OqAX(BxInstruction_t *i) +BX_CPU_C::MOV_OqAX(bxInstruction_c *i) { Bit16u temp_16; bx_address addr; - addr = i->Iq; + addr = i->Iq(); /* read from register */ temp_16 = AX; @@ -189,12 +192,12 @@ BX_CPU_C::MOV_OqAX(BxInstruction_t *i) } void -BX_CPU_C::MOV_EAXOq(BxInstruction_t *i) +BX_CPU_C::MOV_EAXOq(bxInstruction_c *i) { Bit32u temp_32; bx_address addr; - addr = i->Iq; + addr = i->Iq(); /* read from memory address */ @@ -211,12 +214,12 @@ BX_CPU_C::MOV_EAXOq(BxInstruction_t *i) void -BX_CPU_C::MOV_OqEAX(BxInstruction_t *i) +BX_CPU_C::MOV_OqEAX(bxInstruction_c *i) { Bit32u temp_32; bx_address addr; - addr = i->Iq; + addr = i->Iq(); /* read from register */ temp_32 = EAX; @@ -231,12 +234,12 @@ BX_CPU_C::MOV_OqEAX(BxInstruction_t *i) } void -BX_CPU_C::MOV_RAXOq(BxInstruction_t *i) +BX_CPU_C::MOV_RAXOq(bxInstruction_c *i) { Bit64u temp_64; bx_address addr; - addr = i->Iq; + addr = i->Iq(); /* read from memory address */ @@ -253,12 +256,12 @@ BX_CPU_C::MOV_RAXOq(BxInstruction_t *i) void -BX_CPU_C::MOV_OqRAX(BxInstruction_t *i) +BX_CPU_C::MOV_OqRAX(bxInstruction_c *i) { Bit64u temp_64; bx_address addr; - addr = i->Iq; + addr = i->Iq(); /* read from register */ temp_64 = RAX; @@ -275,15 +278,15 @@ BX_CPU_C::MOV_OqRAX(BxInstruction_t *i) void -BX_CPU_C::MOV_EqId(BxInstruction_t *i) +BX_CPU_C::MOV_EqId(bxInstruction_c *i) { Bit64u op2_64; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); /* now write sum back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, op2_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), op2_64); } else { write_virtual_qword(i->seg, i->rm_addr, &op2_64); @@ -292,15 +295,15 @@ BX_CPU_C::MOV_EqId(BxInstruction_t *i) void -BX_CPU_C::MOVZX_GqEb(BxInstruction_t *i) +BX_CPU_C::MOVZX_GqEb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVZX_GvEb: not supported on < 386")); #else Bit8u op2_8; - if (i->mod == 0xc0) { - op2_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -308,20 +311,20 @@ BX_CPU_C::MOVZX_GqEb(BxInstruction_t *i) } /* zero extend byte op2 into qword op1 */ - BX_WRITE_64BIT_REG(i->nnn, (Bit64u) op2_8); + BX_WRITE_64BIT_REG(i->nnn(), (Bit64u) op2_8); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::MOVZX_GqEw(BxInstruction_t *i) +BX_CPU_C::MOVZX_GqEw(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVZX_GvEw: not supported on < 386")); #else Bit16u op2_16; - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -329,20 +332,20 @@ BX_CPU_C::MOVZX_GqEw(BxInstruction_t *i) } /* zero extend word op2 into qword op1 */ - BX_WRITE_64BIT_REG(i->nnn, (Bit64u) op2_16); + BX_WRITE_64BIT_REG(i->nnn(), (Bit64u) op2_16); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::MOVSX_GqEb(BxInstruction_t *i) +BX_CPU_C::MOVSX_GqEb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVSX_GvEb: not supported on < 386")); #else Bit8u op2_8; - if (i->mod == 0xc0) { - op2_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -350,20 +353,20 @@ BX_CPU_C::MOVSX_GqEb(BxInstruction_t *i) } /* sign extend byte op2 into qword op1 */ - BX_WRITE_64BIT_REG(i->nnn, (Bit8s) op2_8); + BX_WRITE_64BIT_REG(i->nnn(), (Bit8s) op2_8); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::MOVSX_GqEw(BxInstruction_t *i) +BX_CPU_C::MOVSX_GqEw(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVSX_GvEw: not supported on < 386")); #else Bit16u op2_16; - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -371,20 +374,20 @@ BX_CPU_C::MOVSX_GqEw(BxInstruction_t *i) } /* sign extend word op2 into qword op1 */ - BX_WRITE_64BIT_REG(i->nnn, (Bit16s) op2_16); + BX_WRITE_64BIT_REG(i->nnn(), (Bit16s) op2_16); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::MOVSX_GqEd(BxInstruction_t *i) +BX_CPU_C::MOVSX_GqEd(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOVSX_GvEw: not supported on < 386")); #else Bit32u op2_32; - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -392,23 +395,23 @@ BX_CPU_C::MOVSX_GqEd(BxInstruction_t *i) } /* sign extend word op2 into qword op1 */ - BX_WRITE_64BIT_REG(i->nnn, (Bit16s) op2_32); + BX_WRITE_64BIT_REG(i->nnn(), (Bit16s) op2_32); #endif /* BX_CPU_LEVEL < 3 */ } void -BX_CPU_C::XCHG_EqGq(BxInstruction_t *i) +BX_CPU_C::XCHG_EqGq(bxInstruction_c *i) { Bit64u op2_64, op1_64; /* op2_64 is a register, op2_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); - BX_WRITE_64BIT_REG(i->rm, op2_64); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); + BX_WRITE_64BIT_REG(i->rm(), op2_64); } else { /* pointer, segment address pair */ @@ -416,12 +419,12 @@ BX_CPU_C::XCHG_EqGq(BxInstruction_t *i) write_RMW_virtual_qword(op2_64); } - BX_WRITE_64BIT_REG(i->nnn, op1_64); + BX_WRITE_64BIT_REG(i->nnn(), op1_64); } void -BX_CPU_C::CMOV_GqEq(BxInstruction_t *i) +BX_CPU_C::CMOV_GqEq(bxInstruction_c *i) { #if (BX_CPU_LEVEL >= 6) || (BX_CPU_LEVEL_HACKED >= 6) // Note: CMOV accesses a memory source operand (read), regardless @@ -455,8 +458,8 @@ BX_CPU_C::CMOV_GqEq(BxInstruction_t *i) BX_PANIC(("CMOV_GdEd: default case")); } - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -464,7 +467,7 @@ BX_CPU_C::CMOV_GqEq(BxInstruction_t *i) } if (condition) { - BX_WRITE_64BIT_REG(i->nnn, op2_64); + BX_WRITE_64BIT_REG(i->nnn(), op2_64); } #else BX_PANIC(("cmov_gded called")); diff --git a/bochs/cpu/data_xfer8.cc b/bochs/cpu/data_xfer8.cc index 4060e76f2..f464356d4 100644 --- a/bochs/cpu/data_xfer8.cc +++ b/bochs/cpu/data_xfer8.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: data_xfer8.cc,v 1.7 2002-09-13 21:47:21 kevinlawton Exp $ +// $Id: data_xfer8.cc,v 1.8 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -35,29 +35,29 @@ void -BX_CPU_C::MOV_RLIb(BxInstruction_t *i) +BX_CPU_C::MOV_RLIb(bxInstruction_c *i) { - BX_CPU_THIS_PTR gen_reg[i->b1 & 0x03].word.byte.rl = i->Ib; + BX_CPU_THIS_PTR gen_reg[i->b1 & 0x03].word.byte.rl = i->Ib(); } void -BX_CPU_C::MOV_RHIb(BxInstruction_t *i) +BX_CPU_C::MOV_RHIb(bxInstruction_c *i) { - BX_CPU_THIS_PTR gen_reg[i->b1 & 0x03].word.byte.rh = i->Ib; + BX_CPU_THIS_PTR gen_reg[i->b1 & 0x03].word.byte.rh = i->Ib(); } void -BX_CPU_C::MOV_EbGb(BxInstruction_t *i) +BX_CPU_C::MOV_EbGb(bxInstruction_c *i) { Bit8u op2; /* op2 is a register, op2_addr is an index of a register */ - op2 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* now write op2 to op1 */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, op2); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, op2); } else { write_virtual_byte(i->seg, i->rm_addr, &op2); @@ -66,30 +66,30 @@ BX_CPU_C::MOV_EbGb(BxInstruction_t *i) void -BX_CPU_C::MOV_GbEb(BxInstruction_t *i) +BX_CPU_C::MOV_GbEb(bxInstruction_c *i) { Bit8u op2; - if (i->mod == 0xc0) { - op2 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ read_virtual_byte(i->seg, i->rm_addr, &op2); } - BX_WRITE_8BIT_REGx(i->nnn, i->extend8bit, op2); + BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bit, op2); } void -BX_CPU_C::MOV_ALOb(BxInstruction_t *i) +BX_CPU_C::MOV_ALOb(bxInstruction_c *i) { Bit8u temp_8; bx_address addr; - addr = i->Id; + addr = i->Id(); /* read from memory address */ if (!BX_NULL_SEG_REG(i->seg)) { @@ -106,12 +106,12 @@ BX_CPU_C::MOV_ALOb(BxInstruction_t *i) void -BX_CPU_C::MOV_ObAL(BxInstruction_t *i) +BX_CPU_C::MOV_ObAL(bxInstruction_c *i) { Bit8u temp_8; bx_address addr; - addr = i->Id; + addr = i->Id(); /* read from register */ temp_8 = AL; @@ -127,15 +127,15 @@ BX_CPU_C::MOV_ObAL(BxInstruction_t *i) void -BX_CPU_C::MOV_EbIb(BxInstruction_t *i) +BX_CPU_C::MOV_EbIb(bxInstruction_c *i) { Bit8u op2; - op2 = i->Ib; + op2 = i->Ib(); /* now write op2 back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, op2); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, op2); } else { write_virtual_byte(i->seg, i->rm_addr, &op2); @@ -145,7 +145,7 @@ BX_CPU_C::MOV_EbIb(BxInstruction_t *i) void -BX_CPU_C::XLAT(BxInstruction_t *i) +BX_CPU_C::XLAT(bxInstruction_c *i) { Bit32u offset_32; Bit8u al; @@ -171,17 +171,17 @@ BX_CPU_C::XLAT(BxInstruction_t *i) } void -BX_CPU_C::XCHG_EbGb(BxInstruction_t *i) +BX_CPU_C::XCHG_EbGb(bxInstruction_c *i) { Bit8u op2, op1; /* op2 is a register, op2_addr is an index of a register */ - op2 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, op2); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, op2); } else { /* pointer, segment address pair */ @@ -189,5 +189,5 @@ BX_CPU_C::XCHG_EbGb(BxInstruction_t *i) Write_RMW_virtual_byte(op2); } - BX_WRITE_8BIT_REGx(i->nnn, i->extend8bit, op1); + BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bit, op1); } diff --git a/bochs/cpu/fetchdecode.cc b/bochs/cpu/fetchdecode.cc index 66f5693b9..08767013a 100644 --- a/bochs/cpu/fetchdecode.cc +++ b/bochs/cpu/fetchdecode.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: fetchdecode.cc,v 1.11 2002-09-17 04:20:42 kevinlawton Exp $ +// $Id: fetchdecode.cc,v 1.12 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -69,7 +69,7 @@ -void BxResolveError(BxInstruction_t *); +void BxResolveError(bxInstruction_c *); #if BX_DYNAMIC_TRANSLATION // For 16-bit address mode, this matrix describes the registers @@ -1430,17 +1430,19 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = { unsigned -BX_CPU_C::FetchDecode(Bit8u *iptr, BxInstruction_t *instruction, +BX_CPU_C::FetchDecode(Bit8u *iptr, bxInstruction_c *instruction, unsigned remain, Boolean is_32) { // remain must be at least 1 unsigned b1, b2, ilen=1, attr; unsigned imm_mode, offset; + unsigned rm, mod, nnn; instruction->os_32 = instruction->as_32 = is_32; #if BX_SUPPORT_X86_64 instruction->os_64 = instruction->as_64 = instruction->extend8bit = 0; + instruction->rexB = 0; #endif instruction->ResolveModrm = NULL; instruction->seg = BX_SEG_REG_NULL; @@ -1454,12 +1456,6 @@ another_byte: offset = instruction->os_32 << 9; // * 512 instruction->attr = attr = BxOpcodeInfo[b1+offset].Attr; -#if BX_SUPPORT_X86_64 -#warning "KPL: hacked because simple instructions that used to depend on b1" -#warning "KPL: now look at i->nnn" -instruction->nnn = (b1 & 7); -#endif - if ( !(attr & BxAnother) ) { // Opcode does not require a MODRM byte. // Note that a 2-byte opcode (0F XX) will jump to before @@ -1553,13 +1549,15 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1)); return(0); // Parse mod-nnn-rm and related bytes - unsigned rm; - instruction->modrm = b2; - rm = - instruction->rm = b2 & 0x07; - instruction->mod = b2 & 0xc0; // leave unshifted - instruction->nnn = (b2 >> 3) & 0x07; - if (instruction->mod == 0xc0) { // mod == 11b + mod = b2 & 0xc0; // leave unshifted + nnn = (b2 >> 3) & 0x07; + rm = b2 & 0x07; + instruction->modRMForm.modRMData = (b2<<20); + instruction->modRMForm.modRMData |= mod; + instruction->modRMForm.modRMData |= (nnn<<8); + instruction->modRMForm.modRMData |= rm; + + if (mod == 0xc0) { // mod == 11b goto modrm_done; } if (instruction->as_32) { @@ -1568,7 +1566,7 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1)); #if BX_DYNAMIC_TRANSLATION instruction->DTMemRegsUsed = 1<mod == 0x00) { // mod == 00b + if (mod == 0x00) { // mod == 00b instruction->ResolveModrm = BxResolve32Mod0[rm]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0[rm]; @@ -1596,7 +1594,7 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1)); // mod==00b, rm!=4, rm!=5 goto modrm_done; } - if (instruction->mod == 0x40) { // mod == 01b + if (mod == 0x40) { // mod == 01b instruction->ResolveModrm = BxResolve32Mod1or2[rm]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm]; @@ -1606,7 +1604,7 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1)); get_8bit_displ: if (ilen < remain) { // 8 sign extended to 32 - instruction->displ32u = (Bit8s) *iptr++; + instruction->modRMForm.displ32u = (Bit8s) *iptr++; ilen++; goto modrm_done; } @@ -1628,7 +1626,7 @@ get_32bit_displ: imm32u |= (*iptr++) << 8; imm32u |= (*iptr++) << 16; imm32u |= (*iptr++) << 24; - instruction->displ32u = imm32u; + instruction->modRMForm.displ32u = imm32u; ilen += 4; goto modrm_done; } @@ -1637,7 +1635,7 @@ get_32bit_displ: } } else { // mod!=11b, rm==4, s-i-b byte follows - unsigned sib, base; + unsigned sib, base, index, scale; if (ilen < remain) { sib = *iptr++; ilen++; @@ -1645,25 +1643,26 @@ get_32bit_displ: else { return(0); } - instruction->sib = sib; - base = - instruction->base = sib & 0x07; sib >>= 3; - instruction->index = sib & 0x07; sib >>= 3; - instruction->scale = sib; + base = sib & 0x07; sib >>= 3; + index = sib & 0x07; sib >>= 3; + scale = sib; + instruction->modRMForm.modRMData |= (base<<12); + instruction->modRMForm.modRMData |= (index<<16); + instruction->modRMForm.modRMData |= (scale<<4); #if BX_DYNAMIC_TRANSLATION - if (instruction->index == 0x04) // 100b + if (index == 0x04) // 100b instruction->DTMemRegsUsed = 0; else - instruction->DTMemRegsUsed = 1<index; + instruction->DTMemRegsUsed = 1<mod == 0x00) { // mod==00b, rm==4 + if (mod == 0x00) { // mod==00b, rm==4 instruction->ResolveModrm = BxResolve32Mod0Base[base]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0Base[base]; #endif if (BX_NULL_SEG_REG(instruction->seg)) instruction->seg = BX_CPU_THIS_PTR sreg_mod0_base32[base]; - if (instruction->base == 0x05) { + if (base == 0x05) { goto get_32bit_displ; } // mod==00b, rm==4, base!=5 @@ -1676,7 +1675,7 @@ get_32bit_displ: // for remaining 32bit cases instruction->DTMemRegsUsed |= 1<mod == 0x40) { // mod==01b, rm==4 + if (mod == 0x40) { // mod==01b, rm==4 instruction->ResolveModrm = BxResolve32Mod1or2Base[base]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base]; @@ -1685,7 +1684,7 @@ get_32bit_displ: instruction->seg = BX_CPU_THIS_PTR sreg_mod1or2_base32[base]; goto get_8bit_displ; } - // (instruction->mod == 0x80), mod==10b, rm==4 + // (mod == 0x80), mod==10b, rm==4 instruction->ResolveModrm = BxResolve32Mod1or2Base[base]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base]; @@ -1697,7 +1696,7 @@ get_32bit_displ: } else { // 16-bit addressing modes, mod==11b handled above - if (instruction->mod == 0x40) { // mod == 01b + if (mod == 0x40) { // mod == 01b instruction->ResolveModrm = BxResolve16Mod1or2[rm]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve16Mod1or2[rm]; @@ -1709,7 +1708,7 @@ get_32bit_displ: #endif if (ilen < remain) { // 8 sign extended to 16 - instruction->displ16u = (Bit8s) *iptr++; + instruction->modRMForm.displ16u = (Bit8s) *iptr++; ilen++; goto modrm_done; } @@ -1717,7 +1716,7 @@ get_32bit_displ: return(0); } } - if (instruction->mod == 0x80) { // mod == 10b + if (mod == 0x80) { // mod == 10b instruction->ResolveModrm = BxResolve16Mod1or2[rm]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve16Mod1or2[rm]; @@ -1731,7 +1730,7 @@ get_32bit_displ: Bit16u displ16u; displ16u = *iptr++; displ16u |= (*iptr++) << 8; - instruction->displ16u = displ16u; + instruction->modRMForm.displ16u = displ16u; ilen += 2; goto modrm_done; } @@ -1770,9 +1769,9 @@ modrm_done: BxOpcodeInfo_t *OpcodeInfoPtr; OpcodeInfoPtr = BxOpcodeInfo[b1+offset].AnotherArray; - instruction->execute = OpcodeInfoPtr[instruction->nnn].ExecutePtr; + instruction->execute = OpcodeInfoPtr[nnn].ExecutePtr; // get additional attributes from group table - attr |= OpcodeInfoPtr[instruction->nnn].Attr; + attr |= OpcodeInfoPtr[nnn].Attr; instruction->attr = attr; #if BX_DYNAMIC_TRANSLATION instruction->DTAttr = 0; // for now @@ -1794,7 +1793,7 @@ modrm_done: switch (imm_mode) { case BxImmediate_Ib: if (ilen < remain) { - instruction->Ib = *iptr; + instruction->modRMForm.Ib = *iptr; ilen++; } else { @@ -1806,9 +1805,9 @@ modrm_done: Bit8s temp8s; temp8s = *iptr; if (instruction->os_32) - instruction->Id = (Bit32s) temp8s; + instruction->modRMForm.Id = (Bit32s) temp8s; else - instruction->Iw = (Bit16s) temp8s; + instruction->modRMForm.Iw = (Bit16s) temp8s; ilen++; } else { @@ -1824,7 +1823,7 @@ modrm_done: imm32u |= (*iptr++) << 8; imm32u |= (*iptr++) << 16; imm32u |= (*iptr) << 24; - instruction->Id = imm32u; + instruction->modRMForm.Id = imm32u; ilen += 4; } else { @@ -1836,7 +1835,7 @@ modrm_done: Bit16u imm16u; imm16u = *iptr++; imm16u |= (*iptr) << 8; - instruction->Iw = imm16u; + instruction->modRMForm.Iw = imm16u; ilen += 2; } else { @@ -1851,7 +1850,7 @@ modrm_done: Bit16u imm16u; imm16u = *iptr++; imm16u |= (*iptr) << 8; - instruction->Iw2 = imm16u; + instruction->modRMForm.Iw2 = imm16u; ilen += 2; } else { @@ -1867,7 +1866,7 @@ modrm_done: imm32u |= (*iptr++) << 8; imm32u |= (*iptr++) << 16; imm32u |= (*iptr) << 24; - instruction->Id = imm32u; + instruction->modRMForm.Id = imm32u; ilen += 4; } else { @@ -1880,7 +1879,7 @@ modrm_done: Bit32u imm32u; imm32u = *iptr++; imm32u |= (*iptr) << 8; - instruction->Id = imm32u; + instruction->modRMForm.Id = imm32u; ilen += 2; } else { @@ -1894,7 +1893,7 @@ modrm_done: Bit16u imm16u; imm16u = *iptr++; imm16u |= (*iptr) << 8; - instruction->Iw = imm16u; + instruction->modRMForm.Iw = imm16u; ilen += 2; } else { @@ -1903,7 +1902,7 @@ modrm_done: if (imm_mode == BxImmediate_Iw) break; iptr++; if (ilen < remain) { - instruction->Ib2 = *iptr; + instruction->modRMForm.Ib2 = *iptr; ilen++; } else { @@ -1914,7 +1913,7 @@ modrm_done: if (ilen < remain) { Bit8s temp8s; temp8s = *iptr; - instruction->Id = temp8s; + instruction->modRMForm.Id = temp8s; ilen++; } else { @@ -1926,7 +1925,7 @@ modrm_done: Bit16u imm16u; imm16u = *iptr++; imm16u |= (*iptr) << 8; - instruction->Id = (Bit16s) imm16u; + instruction->modRMForm.Id = (Bit16s) imm16u; ilen += 2; } else { @@ -1946,11 +1945,11 @@ BX_INFO(("b1 was %x", b1)); } void -BX_CPU_C::BxError(BxInstruction_t *i) +BX_CPU_C::BxError(bxInstruction_c *i) { // extern void dump_core(); BX_INFO(("BxError: instruction with op1=0x%x", i->b1)); - BX_INFO(("nnn was %u", i->nnn)); + BX_INFO(("nnn was %u", i->nnn())); BX_INFO(("WARNING: Encountered an unknown instruction (signalling illegal instruction):")); // dump_core(); @@ -1959,7 +1958,7 @@ BX_CPU_C::BxError(BxInstruction_t *i) } void -BX_CPU_C::BxResolveError(BxInstruction_t *i) +BX_CPU_C::BxResolveError(bxInstruction_c *i) { BX_PANIC(("BxResolveError: instruction with op1=0x%x", i->b1)); } diff --git a/bochs/cpu/fetchdecode64.cc b/bochs/cpu/fetchdecode64.cc index 201a8343f..d4214a3b5 100644 --- a/bochs/cpu/fetchdecode64.cc +++ b/bochs/cpu/fetchdecode64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: fetchdecode64.cc,v 1.2 2002-09-17 04:20:42 kevinlawton Exp $ +// $Id: fetchdecode64.cc,v 1.3 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -69,7 +69,7 @@ -void BxResolveError(BxInstruction_t *); +void BxResolveError(bxInstruction_c *); #if BX_DYNAMIC_TRANSLATION // For 16-bit address mode, this matrix describes the registers @@ -2012,13 +2012,14 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = { unsigned -BX_CPU_C::FetchDecode64(Bit8u *iptr, BxInstruction_t *instruction, +BX_CPU_C::FetchDecode64(Bit8u *iptr, bxInstruction_c *instruction, unsigned remain) { // remain must be at least 1 unsigned b1, b2, ilen=1, attr; unsigned imm_mode, offset, rex_r,rex_x,rex_b; + unsigned rm, mod, nnn; instruction->os_32 = 1; // operand size 32 override defaults to 1 instruction->os_64 = 0; // operand size 64 override defaults to 0 @@ -2028,7 +2029,7 @@ BX_CPU_C::FetchDecode64(Bit8u *iptr, BxInstruction_t *instruction, offset = 512*1; rex_r = 0; rex_x = 0; - rex_b = 0; + instruction->rexB = rex_b = 0; instruction->ResolveModrm = NULL; instruction->seg = BX_SEG_REG_NULL; instruction->rep_used = 0; @@ -2099,7 +2100,7 @@ another_byte: //BX_DEBUG((" index+8")); } if (b1 & 0x1) { - rex_b = 8; + instruction->rexB = rex_b = 8; //BX_DEBUG((" base+8")); } if (ilen < remain) { @@ -2164,25 +2165,29 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1)); return(0); // Parse mod-nnn-rm and related bytes - unsigned rm; - instruction->modrm = b2; - rm = b2 & 0x07; - instruction->mod = b2 & 0xc0; // leave unshifted - instruction->nnn = ((b2 >> 3) & 0x07) + rex_r; - if (instruction->mod == 0xc0) { // mod == 11b + mod = b2 & 0xc0; + nnn = ((b2 >> 3) & 0x07) + rex_r; + rm = b2 & 0x07; + instruction->modRMForm.modRMData = (b2<<20); + instruction->modRMForm.modRMData |= mod; + instruction->modRMForm.modRMData |= (nnn<<8); + + if (mod == 0xc0) { // mod == 11b rm += rex_b; + instruction->modRMForm.modRMData |= rm; goto modrm_done; } if (rm != 4) { rm += rex_b; } + instruction->modRMForm.modRMData |= rm; if (instruction->as_64) { // 64-bit addressing modes; note that mod==11b handled above if (rm != 4) { // no s-i-b byte #if BX_DYNAMIC_TRANSLATION instruction->DTMemRegsUsed = 1<mod == 0x00) { // mod == 00b + if (mod == 0x00) { // mod == 00b instruction->ResolveModrm = BxResolve64Mod0[rm]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0[rm]; @@ -2197,7 +2202,7 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1)); imm32u |= (*iptr++) << 16; imm32u |= (*iptr++) << 24; ilen += 4; - instruction->displ32u = imm32u; + instruction->modRMForm.displ32u = imm32u; #if BX_DYNAMIC_TRANSLATION instruction->DTMemRegsUsed = 0; #endif @@ -2210,7 +2215,7 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1)); // mod==00b, rm!=4, rm!=5 goto modrm_done; } - if (instruction->mod == 0x40) { // mod == 01b + if (mod == 0x40) { // mod == 01b instruction->ResolveModrm = BxResolve64Mod1or2[rm]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm]; @@ -2220,7 +2225,7 @@ BX_PANIC(("fetch_decode: prefix default = 0x%02x", b1)); get_8bit_displ_1: if (ilen < remain) { // 8 sign extended to 32 - instruction->displ32u = (Bit8s) *iptr++; + instruction->modRMForm.displ32u = (Bit8s) *iptr++; ilen++; goto modrm_done; } @@ -2242,7 +2247,7 @@ get_32bit_displ_1: imm32u |= (*iptr++) << 8; imm32u |= (*iptr++) << 16; imm32u |= (*iptr++) << 24; - instruction->displ32u = imm32u; + instruction->modRMForm.displ32u = imm32u; ilen += 4; goto modrm_done; } @@ -2251,7 +2256,7 @@ get_32bit_displ_1: } } else { // mod!=11b, rm==4, s-i-b byte follows - unsigned sib, base; + unsigned sib, base, index, scale; if (ilen < remain) { sib = *iptr++; ilen++; @@ -2259,25 +2264,26 @@ get_32bit_displ_1: else { return(0); } - instruction->sib = sib; - base = - instruction->base = (sib & 0x07) + rex_b; sib >>= 3; - instruction->index = (sib & 0x07) + rex_x; sib >>= 3; - instruction->scale = sib; + base = (sib & 0x07) + rex_b; sib >>= 3; + index = (sib & 0x07) + rex_x; sib >>= 3; + scale = sib; + instruction->modRMForm.modRMData |= (base<<12); + instruction->modRMForm.modRMData |= (index<<16); + instruction->modRMForm.modRMData |= (scale<<4); #if BX_DYNAMIC_TRANSLATION - if (instruction->index == 0x04) // 100b + if (instruction->modRMForm.index == 0x04) // 100b instruction->DTMemRegsUsed = 0; else - instruction->DTMemRegsUsed = 1<index; + instruction->DTMemRegsUsed = 1<modRMForm.index; #endif - if (instruction->mod == 0x00) { // mod==00b, rm==4 + if (mod == 0x00) { // mod==00b, rm==4 instruction->ResolveModrm = BxResolve64Mod0Base[base]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0Base[base]; #endif if (BX_NULL_SEG_REG(instruction->seg)) instruction->seg = BX_CPU_THIS_PTR sreg_mod0_base32[base]; - if (instruction->base == 0x05) { + if (base == 0x05) { goto get_32bit_displ_1; } // mod==00b, rm==4, base!=5 @@ -2290,7 +2296,7 @@ get_32bit_displ_1: // for remaining 32bit cases instruction->DTMemRegsUsed |= 1<mod == 0x40) { // mod==01b, rm==4 + if (mod == 0x40) { // mod==01b, rm==4 instruction->ResolveModrm = BxResolve64Mod1or2Base[base]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base]; @@ -2299,7 +2305,7 @@ get_32bit_displ_1: instruction->seg = BX_CPU_THIS_PTR sreg_mod1or2_base32[base]; goto get_8bit_displ_1; } - // (instruction->mod == 0x80), mod==10b, rm==4 + // (mod == 0x80), mod==10b, rm==4 instruction->ResolveModrm = BxResolve64Mod1or2Base[base]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base]; @@ -2315,7 +2321,7 @@ get_32bit_displ_1: #if BX_DYNAMIC_TRANSLATION instruction->DTMemRegsUsed = 1<mod == 0x00) { // mod == 00b + if (mod == 0x00) { // mod == 00b instruction->ResolveModrm = BxResolve32Mod0[rm]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0[rm]; @@ -2343,7 +2349,7 @@ get_32bit_displ_1: // mod==00b, rm!=4, rm!=5 goto modrm_done; } - if (instruction->mod == 0x40) { // mod == 01b + if (mod == 0x40) { // mod == 01b instruction->ResolveModrm = BxResolve32Mod1or2[rm]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2[rm]; @@ -2353,7 +2359,7 @@ get_32bit_displ_1: get_8bit_displ: if (ilen < remain) { // 8 sign extended to 32 - instruction->displ32u = (Bit8s) *iptr++; + instruction->modRMForm.displ32u = (Bit8s) *iptr++; ilen++; goto modrm_done; } @@ -2375,7 +2381,7 @@ get_32bit_displ: imm32u |= (*iptr++) << 8; imm32u |= (*iptr++) << 16; imm32u |= (*iptr++) << 24; - instruction->displ32u = imm32u; + instruction->modRMForm.displ32u = imm32u; ilen += 4; goto modrm_done; } @@ -2384,7 +2390,7 @@ get_32bit_displ: } } else { // mod!=11b, rm==4, s-i-b byte follows - unsigned sib, base; + unsigned sib, base, index, scale; if (ilen < remain) { sib = *iptr++; ilen++; @@ -2392,25 +2398,26 @@ get_32bit_displ: else { return(0); } - instruction->sib = sib; - base = - instruction->base = (sib & 0x07) + rex_b; sib >>= 3; - instruction->index = (sib & 0x07) + rex_x; sib >>= 3; - instruction->scale = sib; + base = (sib & 0x07) + rex_b; sib >>= 3; + index = (sib & 0x07) + rex_x; sib >>= 3; + scale = sib; + instruction->modRMForm.modRMData |= (base<<12); + instruction->modRMForm.modRMData |= (index<<16); + instruction->modRMForm.modRMData |= (scale<<4); #if BX_DYNAMIC_TRANSLATION - if (instruction->index == 0x04) // 100b + if (instruction->modRMForm.index == 0x04) // 100b instruction->DTMemRegsUsed = 0; else - instruction->DTMemRegsUsed = 1<index; + instruction->DTMemRegsUsed = 1<modRMForm.index; #endif - if (instruction->mod == 0x00) { // mod==00b, rm==4 + if (mod == 0x00) { // mod==00b, rm==4 instruction->ResolveModrm = BxResolve32Mod0Base[base]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod0Base[base]; #endif if (BX_NULL_SEG_REG(instruction->seg)) instruction->seg = BX_CPU_THIS_PTR sreg_mod0_base32[base]; - if (instruction->base == 0x05) { + if (base == 0x05) { goto get_32bit_displ; } // mod==00b, rm==4, base!=5 @@ -2423,7 +2430,7 @@ get_32bit_displ: // for remaining 32bit cases instruction->DTMemRegsUsed |= 1<mod == 0x40) { // mod==01b, rm==4 + if (mod == 0x40) { // mod==01b, rm==4 instruction->ResolveModrm = BxResolve32Mod1or2Base[base]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base]; @@ -2432,7 +2439,7 @@ get_32bit_displ: instruction->seg = BX_CPU_THIS_PTR sreg_mod1or2_base32[base]; goto get_8bit_displ; } - // (instruction->mod == 0x80), mod==10b, rm==4 + // (mod == 0x80), mod==10b, rm==4 instruction->ResolveModrm = BxResolve32Mod1or2Base[base]; #if BX_DYNAMIC_TRANSLATION instruction->DTResolveModrm = (BxVoidFPtr_t) BxDTResolve32Mod1or2Base[base]; @@ -2444,7 +2451,6 @@ get_32bit_displ: } modrm_done: - instruction->rm = rm; /* BX_DEBUG (("as_64=%d os_64=%d as_32=%d os_32=%d b1=%04x b2=%04x ofs=%4d rm=%d mod=%d nnn=%d", instruction->as_64, @@ -2452,18 +2458,18 @@ modrm_done: instruction->as_32, instruction->os_32, b1,b2,offset, - instruction->rm, - instruction->mod, - instruction->nnn + instruction->modRMForm.rm, + mod, + nnn )); */ if (attr & BxGroupN) { BxOpcodeInfo_t *OpcodeInfoPtr; OpcodeInfoPtr = BxOpcodeInfo64[b1+offset].AnotherArray; - instruction->execute = OpcodeInfoPtr[instruction->nnn].ExecutePtr; + instruction->execute = OpcodeInfoPtr[nnn].ExecutePtr; // get additional attributes from group table - attr |= OpcodeInfoPtr[instruction->nnn].Attr; + attr |= OpcodeInfoPtr[nnn].Attr; instruction->attr = attr; #if BX_DYNAMIC_TRANSLATION instruction->DTAttr = 0; // for now @@ -2483,7 +2489,6 @@ modrm_done: // the if() above after fetching the 2nd byte, so this path is // taken in all cases if a modrm byte is NOT required. instruction->execute = BxOpcodeInfo64[b1+offset].ExecutePtr; - instruction->nnn = (b1 & 7) + rex_b; #if BX_DYNAMIC_TRANSLATION instruction->DTAttr = BxDTOpcodeInfo[b1+offset].DTAttr; instruction->DTFPtr = BxDTOpcodeInfo[b1+offset].DTASFPtr; @@ -2497,7 +2502,7 @@ modrm_done: switch (imm_mode) { case BxImmediate_Ib: if (ilen < remain) { - instruction->Ib = *iptr; + instruction->modRMForm.Ib = *iptr; ilen++; } else { @@ -2509,9 +2514,9 @@ modrm_done: Bit8s temp8s; temp8s = *iptr; if (instruction->os_32) - instruction->Id = (Bit32s) temp8s; + instruction->modRMForm.Id = (Bit32s) temp8s; else - instruction->Iw = (Bit16s) temp8s; + instruction->modRMForm.Iw = (Bit16s) temp8s; ilen++; } else { @@ -2527,7 +2532,7 @@ modrm_done: imm32u |= (*iptr++) << 8; imm32u |= (*iptr++) << 16; imm32u |= (*iptr) << 24; - instruction->Id = imm32u; + instruction->modRMForm.Id = imm32u; ilen += 4; } else { @@ -2539,7 +2544,7 @@ modrm_done: Bit16u imm16u; imm16u = *iptr++; imm16u |= (*iptr) << 8; - instruction->Iw = imm16u; + instruction->modRMForm.Iw = imm16u; ilen += 2; } else { @@ -2554,7 +2559,7 @@ modrm_done: Bit16u imm16u; imm16u = *iptr++; imm16u |= (*iptr) << 8; - instruction->Iw2 = imm16u; + instruction->modRMForm.Iw2 = imm16u; ilen += 2; } else { @@ -2573,7 +2578,7 @@ modrm_done: imm64u |= ((Bit64u)*iptr++) << 40; imm64u |= ((Bit64u)*iptr++) << 48; imm64u |= ((Bit64u)*iptr) << 56; - instruction->Iq = imm64u; + instruction->IqForm.Iq = imm64u; ilen += 8; } else { @@ -2589,7 +2594,7 @@ modrm_done: imm32u |= (*iptr++) << 8; imm32u |= (*iptr++) << 16; imm32u |= (*iptr) << 24; - instruction->Id = imm32u; + instruction->modRMForm.Id = imm32u; ilen += 4; } else { @@ -2602,7 +2607,7 @@ modrm_done: Bit32u imm32u; imm32u = *iptr++; imm32u |= (*iptr) << 8; - instruction->Id = imm32u; + instruction->modRMForm.Id = imm32u; ilen += 2; } else { @@ -2616,7 +2621,7 @@ modrm_done: Bit16u imm16u; imm16u = *iptr++; imm16u |= (*iptr) << 8; - instruction->Iw = imm16u; + instruction->modRMForm.Iw = imm16u; ilen += 2; } else { @@ -2625,7 +2630,7 @@ modrm_done: if (imm_mode == BxImmediate_Iw) break; iptr++; if (ilen < remain) { - instruction->Ib2 = *iptr; + instruction->modRMForm.Ib2 = *iptr; ilen++; } else { @@ -2636,7 +2641,7 @@ modrm_done: if (ilen < remain) { Bit8s temp8s; temp8s = *iptr; - instruction->Id = temp8s; + instruction->modRMForm.Id = temp8s; ilen++; } else { @@ -2648,7 +2653,7 @@ modrm_done: Bit16u imm16u; imm16u = *iptr++; imm16u |= (*iptr) << 8; - instruction->Id = (Bit16s) imm16u; + instruction->modRMForm.Id = (Bit16s) imm16u; ilen += 2; } else { @@ -2669,11 +2674,11 @@ BX_INFO(("b1 was %x", b1)); #ifdef ignore void -BX_CPU_C::BxError(BxInstruction_t *i) +BX_CPU_C::BxError(bxInstruction_c *i) { // extern void dump_core(); BX_INFO(("BxError: instruction with op1=0x%x", i->b1)); - BX_INFO(("nnn was %u", i->nnn)); + BX_INFO(("nnn was %u", i->modRMForm.nnn)); BX_INFO(("WARNING: Encountered an unknown instruction (signalling illegal instruction):")); // dump_core(); @@ -2682,7 +2687,7 @@ BX_CPU_C::BxError(BxInstruction_t *i) } void -BX_CPU_C::BxResolveError(BxInstruction_t *i) +BX_CPU_C::BxResolveError(bxInstruction_c *i) { BX_PANIC(("BxResolveError: instruction with op1=0x%x", i->b1)); } diff --git a/bochs/cpu/flag_ctrl.cc b/bochs/cpu/flag_ctrl.cc index 842836c0a..acd17e7e1 100644 --- a/bochs/cpu/flag_ctrl.cc +++ b/bochs/cpu/flag_ctrl.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: flag_ctrl.cc,v 1.10 2002-09-15 01:00:19 kevinlawton Exp $ +// $Id: flag_ctrl.cc,v 1.11 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2002 MandrakeSoft S.A. @@ -38,7 +38,7 @@ void -BX_CPU_C::SAHF(BxInstruction_t *i) +BX_CPU_C::SAHF(bxInstruction_c *i) { set_SF((AH & 0x80) >> 7); set_ZF((AH & 0x40) >> 6); @@ -48,7 +48,7 @@ BX_CPU_C::SAHF(BxInstruction_t *i) } void -BX_CPU_C::LAHF(BxInstruction_t *i) +BX_CPU_C::LAHF(bxInstruction_c *i) { AH = (get_SF() ? 0x80 : 0) | (get_ZF() ? 0x40 : 0) | @@ -59,19 +59,19 @@ BX_CPU_C::LAHF(BxInstruction_t *i) } void -BX_CPU_C::CLC(BxInstruction_t *i) +BX_CPU_C::CLC(bxInstruction_c *i) { set_CF(0); } void -BX_CPU_C::STC(BxInstruction_t *i) +BX_CPU_C::STC(bxInstruction_c *i) { set_CF(1); } void -BX_CPU_C::CLI(BxInstruction_t *i) +BX_CPU_C::CLI(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 2 if (protected_mode()) { @@ -96,7 +96,7 @@ BX_CPU_C::CLI(BxInstruction_t *i) } void -BX_CPU_C::STI(BxInstruction_t *i) +BX_CPU_C::STI(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 2 if (protected_mode()) { @@ -125,25 +125,25 @@ BX_CPU_C::STI(BxInstruction_t *i) } void -BX_CPU_C::CLD(BxInstruction_t *i) +BX_CPU_C::CLD(bxInstruction_c *i) { BX_CPU_THIS_PTR clear_DF (); } void -BX_CPU_C::STD(BxInstruction_t *i) +BX_CPU_C::STD(bxInstruction_c *i) { BX_CPU_THIS_PTR assert_DF (); } void -BX_CPU_C::CMC(BxInstruction_t *i) +BX_CPU_C::CMC(bxInstruction_c *i) { set_CF( !get_CF() ); } void -BX_CPU_C::PUSHF_Fv(BxInstruction_t *i) +BX_CPU_C::PUSHF_Fv(bxInstruction_c *i) { if (v8086_mode() && (BX_CPU_THIS_PTR get_IOPL ()<3)) { exception(BX_GP_EXCEPTION, 0, 0); @@ -169,7 +169,7 @@ BX_CPU_C::PUSHF_Fv(BxInstruction_t *i) void -BX_CPU_C::POPF_Fv(BxInstruction_t *i) +BX_CPU_C::POPF_Fv(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 3 @@ -236,7 +236,7 @@ BX_CPU_C::POPF_Fv(BxInstruction_t *i) void -BX_CPU_C::SALC(BxInstruction_t *i) +BX_CPU_C::SALC(bxInstruction_c *i) { if ( get_CF() ) { AL = 0xff; diff --git a/bochs/cpu/io.cc b/bochs/cpu/io.cc index 90f0414f3..1ecc973a4 100644 --- a/bochs/cpu/io.cc +++ b/bochs/cpu/io.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: io.cc,v 1.14 2002-09-16 20:23:38 kevinlawton Exp $ +// $Id: io.cc,v 1.15 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -45,7 +45,7 @@ void -BX_CPU_C::INSB_YbDX(BxInstruction_t *i) +BX_CPU_C::INSB_YbDX(bxInstruction_c *i) { Bit8u value8=0; @@ -109,7 +109,7 @@ BX_CPU_C::INSB_YbDX(BxInstruction_t *i) } void -BX_CPU_C::INSW_YvDX(BxInstruction_t *i) +BX_CPU_C::INSW_YvDX(bxInstruction_c *i) // input word/doubleword from port to string { bx_address edi; @@ -336,7 +336,7 @@ doIncr: } void -BX_CPU_C::OUTSB_DXXb(BxInstruction_t *i) +BX_CPU_C::OUTSB_DXXb(bxInstruction_c *i) { unsigned seg; Bit8u value8; @@ -387,7 +387,7 @@ BX_CPU_C::OUTSB_DXXb(BxInstruction_t *i) } void -BX_CPU_C::OUTSW_DXXv(BxInstruction_t *i) +BX_CPU_C::OUTSW_DXXv(bxInstruction_c *i) // output word/doubleword string to port { unsigned seg; @@ -612,11 +612,11 @@ doIncr: void -BX_CPU_C::IN_ALIb(BxInstruction_t *i) +BX_CPU_C::IN_ALIb(bxInstruction_c *i) { Bit8u al, imm8; - imm8 = i->Ib; + imm8 = i->Ib(); al = BX_CPU_THIS_PTR inp8(imm8); @@ -624,12 +624,12 @@ BX_CPU_C::IN_ALIb(BxInstruction_t *i) } void -BX_CPU_C::IN_eAXIb(BxInstruction_t *i) +BX_CPU_C::IN_eAXIb(bxInstruction_c *i) { Bit8u imm8; - imm8 = i->Ib; + imm8 = i->Ib(); #if BX_CPU_LEVEL > 2 if (i->os_32) { @@ -649,11 +649,11 @@ BX_CPU_C::IN_eAXIb(BxInstruction_t *i) } void -BX_CPU_C::OUT_IbAL(BxInstruction_t *i) +BX_CPU_C::OUT_IbAL(bxInstruction_c *i) { Bit8u al, imm8; - imm8 = i->Ib; + imm8 = i->Ib(); al = AL; @@ -661,11 +661,11 @@ BX_CPU_C::OUT_IbAL(BxInstruction_t *i) } void -BX_CPU_C::OUT_IbeAX(BxInstruction_t *i) +BX_CPU_C::OUT_IbeAX(bxInstruction_c *i) { Bit8u imm8; - imm8 = i->Ib; + imm8 = i->Ib(); #if BX_CPU_LEVEL > 2 if (i->os_32) { @@ -679,7 +679,7 @@ BX_CPU_C::OUT_IbeAX(BxInstruction_t *i) } void -BX_CPU_C::IN_ALDX(BxInstruction_t *i) +BX_CPU_C::IN_ALDX(bxInstruction_c *i) { Bit8u al; @@ -689,7 +689,7 @@ BX_CPU_C::IN_ALDX(BxInstruction_t *i) } void -BX_CPU_C::IN_eAXDX(BxInstruction_t *i) +BX_CPU_C::IN_eAXDX(bxInstruction_c *i) { #if BX_CPU_LEVEL > 2 if (i->os_32) { @@ -709,7 +709,7 @@ BX_CPU_C::IN_eAXDX(BxInstruction_t *i) } void -BX_CPU_C::OUT_DXAL(BxInstruction_t *i) +BX_CPU_C::OUT_DXAL(bxInstruction_c *i) { Bit16u dx; Bit8u al; @@ -721,7 +721,7 @@ BX_CPU_C::OUT_DXAL(BxInstruction_t *i) } void -BX_CPU_C::OUT_DXeAX(BxInstruction_t *i) +BX_CPU_C::OUT_DXeAX(bxInstruction_c *i) { Bit16u dx; diff --git a/bochs/cpu/logical16.cc b/bochs/cpu/logical16.cc index c9f2832cd..82ccf7de4 100644 --- a/bochs/cpu/logical16.cc +++ b/bochs/cpu/logical16.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: logical16.cc,v 1.6 2002-09-06 21:54:57 kevinlawton Exp $ +// $Id: logical16.cc,v 1.7 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -37,17 +37,17 @@ void -BX_CPU_C::XOR_EwGw(BxInstruction_t *i) +BX_CPU_C::XOR_EwGw(bxInstruction_c *i) { Bit16u op2_16, op1_16, result_16; /* op2_16 is a register, op2_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -57,8 +57,8 @@ BX_CPU_C::XOR_EwGw(BxInstruction_t *i) result_16 = op1_16 ^ op2_16; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -69,15 +69,15 @@ BX_CPU_C::XOR_EwGw(BxInstruction_t *i) void -BX_CPU_C::XOR_GwEw(BxInstruction_t *i) +BX_CPU_C::XOR_GwEw(bxInstruction_c *i) { Bit16u op1_16, op2_16, result_16; - op1_16 = BX_READ_16BIT_REG(i->nnn); + op1_16 = BX_READ_16BIT_REG(i->nnn()); /* op2_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -87,20 +87,20 @@ BX_CPU_C::XOR_GwEw(BxInstruction_t *i) result_16 = op1_16 ^ op2_16; /* now write result back to destination */ - BX_WRITE_16BIT_REG(i->nnn, result_16); + BX_WRITE_16BIT_REG(i->nnn(), result_16); SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16); } void -BX_CPU_C::XOR_AXIw(BxInstruction_t *i) +BX_CPU_C::XOR_AXIw(bxInstruction_c *i) { Bit16u op1_16, op2_16, sum_16; op1_16 = AX; - op2_16 = i->Iw; + op2_16 = i->Iw(); sum_16 = op1_16 ^ op2_16; @@ -111,16 +111,16 @@ BX_CPU_C::XOR_AXIw(BxInstruction_t *i) } void -BX_CPU_C::XOR_EwIw(BxInstruction_t *i) +BX_CPU_C::XOR_EwIw(bxInstruction_c *i) { Bit16u op2_16, op1_16, result_16; - op2_16 = i->Iw; + op2_16 = i->Iw(); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -130,8 +130,8 @@ BX_CPU_C::XOR_EwIw(BxInstruction_t *i) result_16 = op1_16 ^ op2_16; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -142,16 +142,16 @@ BX_CPU_C::XOR_EwIw(BxInstruction_t *i) void -BX_CPU_C::OR_EwIw(BxInstruction_t *i) +BX_CPU_C::OR_EwIw(bxInstruction_c *i) { Bit16u op2_16, op1_16, result_16; - op2_16 = i->Iw; + op2_16 = i->Iw(); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -161,8 +161,8 @@ BX_CPU_C::OR_EwIw(BxInstruction_t *i) result_16 = op1_16 | op2_16; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -173,13 +173,13 @@ BX_CPU_C::OR_EwIw(BxInstruction_t *i) void -BX_CPU_C::NOT_Ew(BxInstruction_t *i) +BX_CPU_C::NOT_Ew(bxInstruction_c *i) { Bit16u op1_16, result_16; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -189,8 +189,8 @@ BX_CPU_C::NOT_Ew(BxInstruction_t *i) result_16 = ~op1_16; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -199,17 +199,17 @@ BX_CPU_C::NOT_Ew(BxInstruction_t *i) void -BX_CPU_C::OR_EwGw(BxInstruction_t *i) +BX_CPU_C::OR_EwGw(bxInstruction_c *i) { Bit16u op2_16, op1_16, result_16; /* op2_16 is a register, op2_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -219,8 +219,8 @@ BX_CPU_C::OR_EwGw(BxInstruction_t *i) result_16 = op1_16 | op2_16; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -231,16 +231,16 @@ BX_CPU_C::OR_EwGw(BxInstruction_t *i) void -BX_CPU_C::OR_GwEw(BxInstruction_t *i) +BX_CPU_C::OR_GwEw(bxInstruction_c *i) { Bit16u op1_16, op2_16, result_16; - op1_16 = BX_READ_16BIT_REG(i->nnn); + op1_16 = BX_READ_16BIT_REG(i->nnn()); /* op2_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -250,20 +250,20 @@ BX_CPU_C::OR_GwEw(BxInstruction_t *i) result_16 = op1_16 | op2_16; /* now write result back to destination */ - BX_WRITE_16BIT_REG(i->nnn, result_16); + BX_WRITE_16BIT_REG(i->nnn(), result_16); SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16); } void -BX_CPU_C::OR_AXIw(BxInstruction_t *i) +BX_CPU_C::OR_AXIw(bxInstruction_c *i) { Bit16u op1_16, op2_16, sum_16; op1_16 = AX; - op2_16 = i->Iw; + op2_16 = i->Iw(); sum_16 = op1_16 | op2_16; @@ -276,18 +276,18 @@ BX_CPU_C::OR_AXIw(BxInstruction_t *i) void -BX_CPU_C::AND_EwGw(BxInstruction_t *i) +BX_CPU_C::AND_EwGw(bxInstruction_c *i) { Bit16u op2_16, op1_16, result_16; /* op2_16 is a register, op2_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -297,8 +297,8 @@ BX_CPU_C::AND_EwGw(BxInstruction_t *i) result_16 = op1_16 & op2_16; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -309,16 +309,16 @@ BX_CPU_C::AND_EwGw(BxInstruction_t *i) void -BX_CPU_C::AND_GwEw(BxInstruction_t *i) +BX_CPU_C::AND_GwEw(bxInstruction_c *i) { Bit16u op1_16, op2_16, result_16; - op1_16 = BX_READ_16BIT_REG(i->nnn); + op1_16 = BX_READ_16BIT_REG(i->nnn()); /* op2_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -328,20 +328,20 @@ BX_CPU_C::AND_GwEw(BxInstruction_t *i) result_16 = op1_16 & op2_16; /* now write result back to destination */ - BX_WRITE_16BIT_REG(i->nnn, result_16); + BX_WRITE_16BIT_REG(i->nnn(), result_16); SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_AND16); } void -BX_CPU_C::AND_AXIw(BxInstruction_t *i) +BX_CPU_C::AND_AXIw(bxInstruction_c *i) { Bit16u op1_16, op2_16, sum_16; op1_16 = AX; - op2_16 = i->Iw; + op2_16 = i->Iw(); sum_16 = op1_16 & op2_16; @@ -352,15 +352,15 @@ BX_CPU_C::AND_AXIw(BxInstruction_t *i) } void -BX_CPU_C::AND_EwIw(BxInstruction_t *i) +BX_CPU_C::AND_EwIw(bxInstruction_c *i) { Bit16u op2_16, op1_16, result_16; - op2_16 = i->Iw; + op2_16 = i->Iw(); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -370,8 +370,8 @@ BX_CPU_C::AND_EwIw(BxInstruction_t *i) result_16 = op1_16 & op2_16; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -382,17 +382,17 @@ BX_CPU_C::AND_EwIw(BxInstruction_t *i) void -BX_CPU_C::TEST_EwGw(BxInstruction_t *i) +BX_CPU_C::TEST_EwGw(bxInstruction_c *i) { Bit16u op2_16, op1_16, result_16; /* op2_16 is a register, op2_addr is an index of a register */ - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -407,14 +407,14 @@ BX_CPU_C::TEST_EwGw(BxInstruction_t *i) void -BX_CPU_C::TEST_AXIw(BxInstruction_t *i) +BX_CPU_C::TEST_AXIw(bxInstruction_c *i) { Bit16u op2_16, op1_16, result_16; op1_16 = AX; /* op2_16 is imm16 */ - op2_16 = i->Iw; + op2_16 = i->Iw(); result_16 = op1_16 & op2_16; @@ -423,17 +423,17 @@ BX_CPU_C::TEST_AXIw(BxInstruction_t *i) void -BX_CPU_C::TEST_EwIw(BxInstruction_t *i) +BX_CPU_C::TEST_EwIw(bxInstruction_c *i) { Bit16u op2_16, op1_16, result_16; /* op2_16 is imm16 */ - op2_16 = i->Iw; + op2_16 = i->Iw(); /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ diff --git a/bochs/cpu/logical32.cc b/bochs/cpu/logical32.cc index ba8d53f23..5e1170f5c 100644 --- a/bochs/cpu/logical32.cc +++ b/bochs/cpu/logical32.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: logical32.cc,v 1.7 2002-09-13 22:20:45 kevinlawton Exp $ +// $Id: logical32.cc,v 1.8 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -37,17 +37,17 @@ void -BX_CPU_C::XOR_EdGd(BxInstruction_t *i) +BX_CPU_C::XOR_EdGd(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op2_32, op1_32, result_32; /* op2_32 is a register, op2_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -57,8 +57,8 @@ BX_CPU_C::XOR_EdGd(BxInstruction_t *i) result_32 = op1_32 ^ op2_32; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -69,16 +69,16 @@ BX_CPU_C::XOR_EdGd(BxInstruction_t *i) void -BX_CPU_C::XOR_GdEd(BxInstruction_t *i) +BX_CPU_C::XOR_GdEd(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op1_32, op2_32, result_32; - op1_32 = BX_READ_32BIT_REG(i->nnn); + op1_32 = BX_READ_32BIT_REG(i->nnn()); /* op2_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -88,21 +88,21 @@ BX_CPU_C::XOR_GdEd(BxInstruction_t *i) result_32 = op1_32 ^ op2_32; /* now write result back to destination */ - BX_WRITE_32BIT_REGZ(i->nnn, result_32); + BX_WRITE_32BIT_REGZ(i->nnn(), result_32); SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32); } void -BX_CPU_C::XOR_EAXId(BxInstruction_t *i) +BX_CPU_C::XOR_EAXId(bxInstruction_c *i) { /* for 32 bit operand size mode */ Bit32u op1_32, op2_32, sum_32; op1_32 = EAX; - op2_32 = i->Id; + op2_32 = i->Id(); sum_32 = op1_32 ^ op2_32; @@ -117,15 +117,15 @@ BX_CPU_C::XOR_EAXId(BxInstruction_t *i) } void -BX_CPU_C::XOR_EdId(BxInstruction_t *i) +BX_CPU_C::XOR_EdId(bxInstruction_c *i) { Bit32u op2_32, op1_32, result_32; - op2_32 = i->Id; + op2_32 = i->Id(); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -135,8 +135,8 @@ BX_CPU_C::XOR_EdId(BxInstruction_t *i) result_32 = op1_32 ^ op2_32; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -147,15 +147,15 @@ BX_CPU_C::XOR_EdId(BxInstruction_t *i) void -BX_CPU_C::OR_EdId(BxInstruction_t *i) +BX_CPU_C::OR_EdId(bxInstruction_c *i) { Bit32u op2_32, op1_32, result_32; - op2_32 = i->Id; + op2_32 = i->Id(); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -165,8 +165,8 @@ BX_CPU_C::OR_EdId(BxInstruction_t *i) result_32 = op1_32 | op2_32; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -176,13 +176,13 @@ BX_CPU_C::OR_EdId(BxInstruction_t *i) } void -BX_CPU_C::NOT_Ed(BxInstruction_t *i) +BX_CPU_C::NOT_Ed(bxInstruction_c *i) { Bit32u op1_32, result_32; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -192,8 +192,8 @@ BX_CPU_C::NOT_Ed(BxInstruction_t *i) result_32 = ~op1_32; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -202,16 +202,16 @@ BX_CPU_C::NOT_Ed(BxInstruction_t *i) void -BX_CPU_C::OR_EdGd(BxInstruction_t *i) +BX_CPU_C::OR_EdGd(bxInstruction_c *i) { Bit32u op2_32, op1_32, result_32; /* op2_32 is a register, op2_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -221,8 +221,8 @@ BX_CPU_C::OR_EdGd(BxInstruction_t *i) result_32 = op1_32 | op2_32; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -233,15 +233,15 @@ BX_CPU_C::OR_EdGd(BxInstruction_t *i) void -BX_CPU_C::OR_GdEd(BxInstruction_t *i) +BX_CPU_C::OR_GdEd(bxInstruction_c *i) { Bit32u op1_32, op2_32, result_32; - op1_32 = BX_READ_32BIT_REG(i->nnn); + op1_32 = BX_READ_32BIT_REG(i->nnn()); /* op2_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -251,20 +251,20 @@ BX_CPU_C::OR_GdEd(BxInstruction_t *i) result_32 = op1_32 | op2_32; /* now write result back to destination */ - BX_WRITE_32BIT_REGZ(i->nnn, result_32); + BX_WRITE_32BIT_REGZ(i->nnn(), result_32); SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32); } void -BX_CPU_C::OR_EAXId(BxInstruction_t *i) +BX_CPU_C::OR_EAXId(bxInstruction_c *i) { Bit32u op1_32, op2_32, sum_32; op1_32 = EAX; - op2_32 = i->Id; + op2_32 = i->Id(); sum_32 = op1_32 | op2_32; @@ -281,16 +281,16 @@ BX_CPU_C::OR_EAXId(BxInstruction_t *i) void -BX_CPU_C::AND_EdGd(BxInstruction_t *i) +BX_CPU_C::AND_EdGd(bxInstruction_c *i) { Bit32u op2_32, op1_32, result_32; /* op2_32 is a register, op2_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -300,8 +300,8 @@ BX_CPU_C::AND_EdGd(BxInstruction_t *i) result_32 = op1_32 & op2_32; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -312,15 +312,15 @@ BX_CPU_C::AND_EdGd(BxInstruction_t *i) void -BX_CPU_C::AND_GdEd(BxInstruction_t *i) +BX_CPU_C::AND_GdEd(bxInstruction_c *i) { Bit32u op1_32, op2_32, result_32; - op1_32 = BX_READ_32BIT_REG(i->nnn); + op1_32 = BX_READ_32BIT_REG(i->nnn()); /* op2_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -330,20 +330,20 @@ BX_CPU_C::AND_GdEd(BxInstruction_t *i) result_32 = op1_32 & op2_32; /* now write result back to destination */ - BX_WRITE_32BIT_REGZ(i->nnn, result_32); + BX_WRITE_32BIT_REGZ(i->nnn(), result_32); SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32); } void -BX_CPU_C::AND_EAXId(BxInstruction_t *i) +BX_CPU_C::AND_EAXId(bxInstruction_c *i) { Bit32u op1_32, op2_32, sum_32; op1_32 = EAX; - op2_32 = i->Id; + op2_32 = i->Id(); sum_32 = op1_32 & op2_32; @@ -358,15 +358,15 @@ BX_CPU_C::AND_EAXId(BxInstruction_t *i) } void -BX_CPU_C::AND_EdId(BxInstruction_t *i) +BX_CPU_C::AND_EdId(bxInstruction_c *i) { Bit32u op2_32, op1_32, result_32; - op2_32 = i->Id; + op2_32 = i->Id(); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -376,8 +376,8 @@ BX_CPU_C::AND_EdId(BxInstruction_t *i) result_32 = op1_32 & op2_32; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -388,16 +388,16 @@ BX_CPU_C::AND_EdId(BxInstruction_t *i) void -BX_CPU_C::TEST_EdGd(BxInstruction_t *i) +BX_CPU_C::TEST_EdGd(bxInstruction_c *i) { Bit32u op2_32, op1_32, result_32; /* op2_32 is a register, op2_addr is an index of a register */ - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -412,7 +412,7 @@ BX_CPU_C::TEST_EdGd(BxInstruction_t *i) void -BX_CPU_C::TEST_EAXId(BxInstruction_t *i) +BX_CPU_C::TEST_EAXId(bxInstruction_c *i) { Bit32u op2_32, op1_32, result_32; @@ -420,7 +420,7 @@ BX_CPU_C::TEST_EAXId(BxInstruction_t *i) op1_32 = EAX; /* op2 is imm32 */ - op2_32 = i->Id; + op2_32 = i->Id(); result_32 = op1_32 & op2_32; @@ -429,16 +429,16 @@ BX_CPU_C::TEST_EAXId(BxInstruction_t *i) void -BX_CPU_C::TEST_EdId(BxInstruction_t *i) +BX_CPU_C::TEST_EdId(bxInstruction_c *i) { Bit32u op2_32, op1_32, result_32; /* op2 is imm32 */ - op2_32 = i->Id; + op2_32 = i->Id(); /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ diff --git a/bochs/cpu/logical64.cc b/bochs/cpu/logical64.cc index 9a857a52b..b05b5d9a2 100644 --- a/bochs/cpu/logical64.cc +++ b/bochs/cpu/logical64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: logical64.cc,v 1.1 2002-09-13 15:53:22 kevinlawton Exp $ +// $Id: logical64.cc,v 1.2 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -37,17 +37,17 @@ void -BX_CPU_C::XOR_EqGq(BxInstruction_t *i) +BX_CPU_C::XOR_EqGq(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op2_64, op1_64, result_64; /* op2_64 is a register, op2_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -57,8 +57,8 @@ BX_CPU_C::XOR_EqGq(BxInstruction_t *i) result_64 = op1_64 ^ op2_64; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -69,16 +69,16 @@ BX_CPU_C::XOR_EqGq(BxInstruction_t *i) void -BX_CPU_C::XOR_GqEq(BxInstruction_t *i) +BX_CPU_C::XOR_GqEq(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op1_64, op2_64, result_64; - op1_64 = BX_READ_64BIT_REG(i->nnn); + op1_64 = BX_READ_64BIT_REG(i->nnn()); /* op2_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -88,21 +88,21 @@ BX_CPU_C::XOR_GqEq(BxInstruction_t *i) result_64 = op1_64 ^ op2_64; /* now write result back to destination */ - BX_WRITE_64BIT_REG(i->nnn, result_64); + BX_WRITE_64BIT_REG(i->nnn(), result_64); SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_XOR64); } void -BX_CPU_C::XOR_RAXId(BxInstruction_t *i) +BX_CPU_C::XOR_RAXId(bxInstruction_c *i) { /* for 64 bit operand size mode */ Bit64u op1_64, op2_64, sum_64; op1_64 = RAX; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); sum_64 = op1_64 ^ op2_64; @@ -113,15 +113,15 @@ BX_CPU_C::XOR_RAXId(BxInstruction_t *i) } void -BX_CPU_C::XOR_EqId(BxInstruction_t *i) +BX_CPU_C::XOR_EqId(bxInstruction_c *i) { Bit64u op2_64, op1_64, result_64; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -131,8 +131,8 @@ BX_CPU_C::XOR_EqId(BxInstruction_t *i) result_64 = op1_64 ^ op2_64; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -143,15 +143,15 @@ BX_CPU_C::XOR_EqId(BxInstruction_t *i) void -BX_CPU_C::OR_EqId(BxInstruction_t *i) +BX_CPU_C::OR_EqId(bxInstruction_c *i) { Bit64u op2_64, op1_64, result_64; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -161,8 +161,8 @@ BX_CPU_C::OR_EqId(BxInstruction_t *i) result_64 = op1_64 | op2_64; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -172,13 +172,13 @@ BX_CPU_C::OR_EqId(BxInstruction_t *i) } void -BX_CPU_C::NOT_Eq(BxInstruction_t *i) +BX_CPU_C::NOT_Eq(bxInstruction_c *i) { Bit64u op1_64, result_64; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -188,8 +188,8 @@ BX_CPU_C::NOT_Eq(BxInstruction_t *i) result_64 = ~op1_64; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -198,16 +198,16 @@ BX_CPU_C::NOT_Eq(BxInstruction_t *i) void -BX_CPU_C::OR_EqGq(BxInstruction_t *i) +BX_CPU_C::OR_EqGq(bxInstruction_c *i) { Bit64u op2_64, op1_64, result_64; /* op2_64 is a register, op2_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -217,8 +217,8 @@ BX_CPU_C::OR_EqGq(BxInstruction_t *i) result_64 = op1_64 | op2_64; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -229,15 +229,15 @@ BX_CPU_C::OR_EqGq(BxInstruction_t *i) void -BX_CPU_C::OR_GqEq(BxInstruction_t *i) +BX_CPU_C::OR_GqEq(bxInstruction_c *i) { Bit64u op1_64, op2_64, result_64; - op1_64 = BX_READ_64BIT_REG(i->nnn); + op1_64 = BX_READ_64BIT_REG(i->nnn()); /* op2_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -247,20 +247,20 @@ BX_CPU_C::OR_GqEq(BxInstruction_t *i) result_64 = op1_64 | op2_64; /* now write result back to destination */ - BX_WRITE_64BIT_REG(i->nnn, result_64); + BX_WRITE_64BIT_REG(i->nnn(), result_64); SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_OR64); } void -BX_CPU_C::OR_RAXId(BxInstruction_t *i) +BX_CPU_C::OR_RAXId(bxInstruction_c *i) { Bit64u op1_64, op2_64, sum_64; op1_64 = RAX; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); sum_64 = op1_64 | op2_64; @@ -273,16 +273,16 @@ BX_CPU_C::OR_RAXId(BxInstruction_t *i) void -BX_CPU_C::AND_EqGq(BxInstruction_t *i) +BX_CPU_C::AND_EqGq(bxInstruction_c *i) { Bit64u op2_64, op1_64, result_64; /* op2_64 is a register, op2_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -292,8 +292,8 @@ BX_CPU_C::AND_EqGq(BxInstruction_t *i) result_64 = op1_64 & op2_64; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -304,15 +304,15 @@ BX_CPU_C::AND_EqGq(BxInstruction_t *i) void -BX_CPU_C::AND_GqEq(BxInstruction_t *i) +BX_CPU_C::AND_GqEq(bxInstruction_c *i) { Bit64u op1_64, op2_64, result_64; - op1_64 = BX_READ_64BIT_REG(i->nnn); + op1_64 = BX_READ_64BIT_REG(i->nnn()); /* op2_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -322,20 +322,20 @@ BX_CPU_C::AND_GqEq(BxInstruction_t *i) result_64 = op1_64 & op2_64; /* now write result back to destination */ - BX_WRITE_64BIT_REG(i->nnn, result_64); + BX_WRITE_64BIT_REG(i->nnn(), result_64); SET_FLAGS_OSZAPC_64(op1_64, op2_64, result_64, BX_INSTR_AND64); } void -BX_CPU_C::AND_RAXId(BxInstruction_t *i) +BX_CPU_C::AND_RAXId(bxInstruction_c *i) { Bit64u op1_64, op2_64, sum_64; op1_64 = RAX; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); sum_64 = op1_64 & op2_64; @@ -346,15 +346,15 @@ BX_CPU_C::AND_RAXId(BxInstruction_t *i) } void -BX_CPU_C::AND_EqId(BxInstruction_t *i) +BX_CPU_C::AND_EqId(bxInstruction_c *i) { Bit64u op2_64, op1_64, result_64; - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -364,8 +364,8 @@ BX_CPU_C::AND_EqId(BxInstruction_t *i) result_64 = op1_64 & op2_64; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -376,16 +376,16 @@ BX_CPU_C::AND_EqId(BxInstruction_t *i) void -BX_CPU_C::TEST_EqGq(BxInstruction_t *i) +BX_CPU_C::TEST_EqGq(bxInstruction_c *i) { Bit64u op2_64, op1_64, result_64; /* op2_64 is a register, op2_addr is an index of a register */ - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -400,7 +400,7 @@ BX_CPU_C::TEST_EqGq(BxInstruction_t *i) void -BX_CPU_C::TEST_RAXId(BxInstruction_t *i) +BX_CPU_C::TEST_RAXId(bxInstruction_c *i) { Bit64u op2_64, op1_64, result_64; @@ -408,7 +408,7 @@ BX_CPU_C::TEST_RAXId(BxInstruction_t *i) op1_64 = RAX; /* op2 is imm64 */ - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); result_64 = op1_64 & op2_64; @@ -417,16 +417,16 @@ BX_CPU_C::TEST_RAXId(BxInstruction_t *i) void -BX_CPU_C::TEST_EqId(BxInstruction_t *i) +BX_CPU_C::TEST_EqId(bxInstruction_c *i) { Bit64u op2_64, op1_64, result_64; /* op2 is imm64 */ - op2_64 = (Bit32s) i->Id; + op2_64 = (Bit32s) i->Id(); /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ diff --git a/bochs/cpu/logical8.cc b/bochs/cpu/logical8.cc index e8ad40c29..5f3b0e572 100644 --- a/bochs/cpu/logical8.cc +++ b/bochs/cpu/logical8.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: logical8.cc,v 1.7 2002-09-13 22:20:45 kevinlawton Exp $ +// $Id: logical8.cc,v 1.8 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -36,16 +36,16 @@ void -BX_CPU_C::XOR_EbGb(BxInstruction_t *i) +BX_CPU_C::XOR_EbGb(bxInstruction_c *i) { Bit8u op2, op1, result; /* op2 is a register, op2_addr is an index of a register */ - op2 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -55,8 +55,8 @@ BX_CPU_C::XOR_EbGb(BxInstruction_t *i) result = op1 ^ op2; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result); } else { Write_RMW_virtual_byte(result); @@ -66,15 +66,15 @@ BX_CPU_C::XOR_EbGb(BxInstruction_t *i) } void -BX_CPU_C::XOR_GbEb(BxInstruction_t *i) +BX_CPU_C::XOR_GbEb(bxInstruction_c *i) { Bit8u op1, op2, result; - op1 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op1 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -84,20 +84,20 @@ BX_CPU_C::XOR_GbEb(BxInstruction_t *i) result = op1 ^ op2; /* now write result back to destination, which is a register */ - BX_WRITE_8BIT_REGx(i->nnn, i->extend8bit, result); + BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bit, result); SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_XOR8); } void -BX_CPU_C::XOR_ALIb(BxInstruction_t *i) +BX_CPU_C::XOR_ALIb(bxInstruction_c *i) { Bit8u op1, op2, sum; op1 = AL; - op2 = i->Ib; + op2 = i->Ib(); sum = op1 ^ op2; @@ -109,15 +109,15 @@ BX_CPU_C::XOR_ALIb(BxInstruction_t *i) void -BX_CPU_C::XOR_EbIb(BxInstruction_t *i) +BX_CPU_C::XOR_EbIb(bxInstruction_c *i) { Bit8u op2, op1, result; - op2 = i->Ib; + op2 = i->Ib(); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -127,8 +127,8 @@ BX_CPU_C::XOR_EbIb(BxInstruction_t *i) result = op1 ^ op2; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result); } else { Write_RMW_virtual_byte(result); @@ -140,15 +140,15 @@ BX_CPU_C::XOR_EbIb(BxInstruction_t *i) void -BX_CPU_C::OR_EbIb(BxInstruction_t *i) +BX_CPU_C::OR_EbIb(bxInstruction_c *i) { Bit8u op2, op1, result; - op2 = i->Ib; + op2 = i->Ib(); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -158,8 +158,8 @@ BX_CPU_C::OR_EbIb(BxInstruction_t *i) result = op1 | op2; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result); } else { Write_RMW_virtual_byte(result); @@ -170,14 +170,14 @@ BX_CPU_C::OR_EbIb(BxInstruction_t *i) void -BX_CPU_C::NOT_Eb(BxInstruction_t *i) +BX_CPU_C::NOT_Eb(bxInstruction_c *i) { Bit8u op1_8, result_8; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -187,8 +187,8 @@ BX_CPU_C::NOT_Eb(BxInstruction_t *i) result_8 = ~op1_8; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { Write_RMW_virtual_byte(result_8); @@ -197,17 +197,17 @@ BX_CPU_C::NOT_Eb(BxInstruction_t *i) void -BX_CPU_C::OR_EbGb(BxInstruction_t *i) +BX_CPU_C::OR_EbGb(bxInstruction_c *i) { Bit8u op2, op1, result; /* op2 is a register, op2_addr is an index of a register */ - op2 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -217,8 +217,8 @@ BX_CPU_C::OR_EbGb(BxInstruction_t *i) result = op1 | op2; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result); } else { Write_RMW_virtual_byte(result); @@ -229,16 +229,16 @@ BX_CPU_C::OR_EbGb(BxInstruction_t *i) void -BX_CPU_C::OR_GbEb(BxInstruction_t *i) +BX_CPU_C::OR_GbEb(bxInstruction_c *i) { Bit8u op1, op2, result; - op1 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op1 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -248,7 +248,7 @@ BX_CPU_C::OR_GbEb(BxInstruction_t *i) result = op1 | op2; /* now write result back to destination, which is a register */ - BX_WRITE_8BIT_REGx(i->nnn, i->extend8bit, result); + BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bit, result); SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_OR8); @@ -256,14 +256,14 @@ BX_CPU_C::OR_GbEb(BxInstruction_t *i) void -BX_CPU_C::OR_ALIb(BxInstruction_t *i) +BX_CPU_C::OR_ALIb(bxInstruction_c *i) { Bit8u op1, op2, sum; op1 = AL; - op2 = i->Ib; + op2 = i->Ib(); sum = op1 | op2; @@ -276,16 +276,16 @@ BX_CPU_C::OR_ALIb(BxInstruction_t *i) void -BX_CPU_C::AND_EbGb(BxInstruction_t *i) +BX_CPU_C::AND_EbGb(bxInstruction_c *i) { Bit8u op2, op1, result; /* op2 is a register, op2_addr is an index of a register */ - op2 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -295,8 +295,8 @@ BX_CPU_C::AND_EbGb(BxInstruction_t *i) result = op1 & op2; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result); } else { Write_RMW_virtual_byte(result); @@ -307,15 +307,15 @@ BX_CPU_C::AND_EbGb(BxInstruction_t *i) void -BX_CPU_C::AND_GbEb(BxInstruction_t *i) +BX_CPU_C::AND_GbEb(bxInstruction_c *i) { Bit8u op1, op2, result; - op1 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op1 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -325,21 +325,21 @@ BX_CPU_C::AND_GbEb(BxInstruction_t *i) result = op1 & op2; /* now write result back to destination, which is a register */ - BX_WRITE_8BIT_REGx(i->nnn, i->extend8bit, result); + BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bit, result); SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_AND8); } void -BX_CPU_C::AND_ALIb(BxInstruction_t *i) +BX_CPU_C::AND_ALIb(bxInstruction_c *i) { Bit8u op1, op2, sum; op1 = AL; - op2 = i->Ib; + op2 = i->Ib(); sum = op1 & op2; @@ -353,16 +353,16 @@ BX_CPU_C::AND_ALIb(BxInstruction_t *i) void -BX_CPU_C::AND_EbIb(BxInstruction_t *i) +BX_CPU_C::AND_EbIb(bxInstruction_c *i) { Bit8u op2, op1, result; - op2 = i->Ib; + op2 = i->Ib(); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -372,8 +372,8 @@ BX_CPU_C::AND_EbIb(BxInstruction_t *i) result = op1 & op2; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result); } else { Write_RMW_virtual_byte(result); @@ -384,16 +384,16 @@ BX_CPU_C::AND_EbIb(BxInstruction_t *i) void -BX_CPU_C::TEST_EbGb(BxInstruction_t *i) +BX_CPU_C::TEST_EbGb(bxInstruction_c *i) { Bit8u op2, op1, result; /* op2 is a register, op2_addr is an index of a register */ - op2 = BX_READ_8BIT_REGx(i->nnn,i->extend8bit); + op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bit); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -407,7 +407,7 @@ BX_CPU_C::TEST_EbGb(BxInstruction_t *i) void -BX_CPU_C::TEST_ALIb(BxInstruction_t *i) +BX_CPU_C::TEST_ALIb(bxInstruction_c *i) { Bit8u op2, op1, result; @@ -415,7 +415,7 @@ BX_CPU_C::TEST_ALIb(BxInstruction_t *i) op1 = AL; /* op2 is imm8 */ - op2 = i->Ib; + op2 = i->Ib(); result = op1 & op2; @@ -425,15 +425,15 @@ BX_CPU_C::TEST_ALIb(BxInstruction_t *i) void -BX_CPU_C::TEST_EbIb(BxInstruction_t *i) +BX_CPU_C::TEST_EbIb(bxInstruction_c *i) { Bit8u op2, op1, result; - op2 = i->Ib; + op2 = i->Ib(); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ diff --git a/bochs/cpu/mmx.cc b/bochs/cpu/mmx.cc index ceba4b50c..7013af055 100644 --- a/bochs/cpu/mmx.cc +++ b/bochs/cpu/mmx.cc @@ -95,17 +95,17 @@ void BX_CPU_C::PrepareMmxInstruction(void) #endif /* 0F 60 */ -void BX_CPU_C::PUNPCKLBW_PqQd(BxInstruction_t *i) +void BX_CPU_C::PUNPCKLBW_PqQd(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), result; Bit32u op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -122,7 +122,7 @@ void BX_CPU_C::PUNPCKLBW_PqQd(BxInstruction_t *i) MMXUB0(result) = MMXUB0(op1); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -130,17 +130,17 @@ void BX_CPU_C::PUNPCKLBW_PqQd(BxInstruction_t *i) } /* 0F 61 */ -void BX_CPU_C::PUNPCKLWD_PqQd(BxInstruction_t *i) +void BX_CPU_C::PUNPCKLWD_PqQd(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), result; Bit32u op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -153,7 +153,7 @@ void BX_CPU_C::PUNPCKLWD_PqQd(BxInstruction_t *i) MMXUW0(result) = MMXUW0(op1); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -161,17 +161,17 @@ void BX_CPU_C::PUNPCKLWD_PqQd(BxInstruction_t *i) } /* 0F 62 */ -void BX_CPU_C::PUNPCKLDQ_PqQd(BxInstruction_t *i) +void BX_CPU_C::PUNPCKLDQ_PqQd(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn); + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()); Bit32u op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -181,7 +181,7 @@ void BX_CPU_C::PUNPCKLDQ_PqQd(BxInstruction_t *i) MMXUD1(op1) = op2; /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -189,16 +189,16 @@ void BX_CPU_C::PUNPCKLDQ_PqQd(BxInstruction_t *i) } /* 0F 63 */ -void BX_CPU_C::PACKSSWB_PqQq(BxInstruction_t *i) +void BX_CPU_C::PACKSSWB_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -215,7 +215,7 @@ void BX_CPU_C::PACKSSWB_PqQq(BxInstruction_t *i) MMXSB7(result) = SaturateWordSToByteS(MMXSW3(op2)); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -223,16 +223,16 @@ void BX_CPU_C::PACKSSWB_PqQq(BxInstruction_t *i) } /* 0F 64 */ -void BX_CPU_C::PCMPGTB_PqQq(BxInstruction_t *i) +void BX_CPU_C::PCMPGTB_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -249,7 +249,7 @@ void BX_CPU_C::PCMPGTB_PqQq(BxInstruction_t *i) MMXUB7(result) = (MMXSB7(op1) > MMXSB7(op2)) ? 0xFF : 0; /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -257,16 +257,16 @@ void BX_CPU_C::PCMPGTB_PqQq(BxInstruction_t *i) } /* 0F 65 */ -void BX_CPU_C::PCMPGTW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PCMPGTW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -279,7 +279,7 @@ void BX_CPU_C::PCMPGTW_PqQq(BxInstruction_t *i) MMXUW3(result) = (MMXSW3(op1) > MMXSW3(op2)) ? 0xFFFF : 0; /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -287,16 +287,16 @@ void BX_CPU_C::PCMPGTW_PqQq(BxInstruction_t *i) } /* 0F 66 */ -void BX_CPU_C::PCMPGTD_PqQq(BxInstruction_t *i) +void BX_CPU_C::PCMPGTD_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -307,7 +307,7 @@ void BX_CPU_C::PCMPGTD_PqQq(BxInstruction_t *i) MMXUD1(result) = (MMXSD1(op1) > MMXSD1(op2)) ? 0xFFFFFFFF : 0; /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -315,16 +315,16 @@ void BX_CPU_C::PCMPGTD_PqQq(BxInstruction_t *i) } /* 0F 67 */ -void BX_CPU_C::PACKUSWB_PqQq(BxInstruction_t *i) +void BX_CPU_C::PACKUSWB_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -341,7 +341,7 @@ void BX_CPU_C::PACKUSWB_PqQq(BxInstruction_t *i) MMXUB7(result) = SaturateWordSToByteU(MMXSW3(op2)); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -349,16 +349,16 @@ void BX_CPU_C::PACKUSWB_PqQq(BxInstruction_t *i) } /* 0F 68 */ -void BX_CPU_C::PUNPCKHBW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PUNPCKHBW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -375,7 +375,7 @@ void BX_CPU_C::PUNPCKHBW_PqQq(BxInstruction_t *i) MMXUB0(result) = MMXUB4(op1); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -383,16 +383,16 @@ void BX_CPU_C::PUNPCKHBW_PqQq(BxInstruction_t *i) } /* 0F 69 */ -void BX_CPU_C::PUNPCKHWD_PqQq(BxInstruction_t *i) +void BX_CPU_C::PUNPCKHWD_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -405,7 +405,7 @@ void BX_CPU_C::PUNPCKHWD_PqQq(BxInstruction_t *i) MMXUW0(result) = MMXUW2(op1); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -413,16 +413,16 @@ void BX_CPU_C::PUNPCKHWD_PqQq(BxInstruction_t *i) } /* 0F 6A */ -void BX_CPU_C::PUNPCKHDQ_PqQq(BxInstruction_t *i) +void BX_CPU_C::PUNPCKHDQ_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -433,7 +433,7 @@ void BX_CPU_C::PUNPCKHDQ_PqQq(BxInstruction_t *i) MMXUD0(result) = MMXUD1(op1); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -441,16 +441,16 @@ void BX_CPU_C::PUNPCKHDQ_PqQq(BxInstruction_t *i) } /* 0F 6B */ -void BX_CPU_C::PACKSSDW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PACKSSDW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -463,7 +463,7 @@ void BX_CPU_C::PACKSSDW_PqQq(BxInstruction_t *i) MMXSW3(result) = SaturateDwordSToWordS(MMXSD1(op2)); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -471,7 +471,7 @@ void BX_CPU_C::PACKSSDW_PqQq(BxInstruction_t *i) } /* 0F 6E */ -void BX_CPU_C::MOVD_PqEd(BxInstruction_t *i) +void BX_CPU_C::MOVD_PqEd(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); @@ -480,8 +480,8 @@ void BX_CPU_C::MOVD_PqEd(BxInstruction_t *i) MMXUD1(op) = 0; /* op is a register or memory reference */ - if (i->mod == 0xc0) { - MMXUD0(op) = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + MMXUD0(op) = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -489,7 +489,7 @@ void BX_CPU_C::MOVD_PqEd(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op); + BX_WRITE_MMX_REG(i->nnn(), op); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -497,7 +497,7 @@ void BX_CPU_C::MOVD_PqEd(BxInstruction_t *i) } /* 0F 6F */ -void BX_CPU_C::MOVQ_PqQq(BxInstruction_t *i) +void BX_CPU_C::MOVQ_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); @@ -505,8 +505,8 @@ void BX_CPU_C::MOVQ_PqQq(BxInstruction_t *i) BxPackedMmxRegister op; /* op is a register or memory reference */ - if (i->mod == 0xc0) { - op = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -514,7 +514,7 @@ void BX_CPU_C::MOVQ_PqQq(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op); + BX_WRITE_MMX_REG(i->nnn(), op); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -522,16 +522,16 @@ void BX_CPU_C::MOVQ_PqQq(BxInstruction_t *i) } /* 0F 74 */ -void BX_CPU_C::PCMPEQB_PqQq(BxInstruction_t *i) +void BX_CPU_C::PCMPEQB_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -548,7 +548,7 @@ void BX_CPU_C::PCMPEQB_PqQq(BxInstruction_t *i) MMXUB7(result) = (MMXUB7(op1) == MMXUB7(op2)) ? 0xFF : 0; /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -556,16 +556,16 @@ void BX_CPU_C::PCMPEQB_PqQq(BxInstruction_t *i) } /* 0F 75 */ -void BX_CPU_C::PCMPEQW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PCMPEQW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -578,7 +578,7 @@ void BX_CPU_C::PCMPEQW_PqQq(BxInstruction_t *i) MMXUW3(result) = (MMXUW3(op1) == MMXUW3(op2)) ? 0xFFFF : 0; /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -586,16 +586,16 @@ void BX_CPU_C::PCMPEQW_PqQq(BxInstruction_t *i) } /* 0F 76 */ -void BX_CPU_C::PCMPEQD_PqQq(BxInstruction_t *i) +void BX_CPU_C::PCMPEQD_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -606,7 +606,7 @@ void BX_CPU_C::PCMPEQD_PqQq(BxInstruction_t *i) MMXUD1(result) = (MMXUD1(op1) == MMXUD1(op2)) ? 0xFFFFFFFF : 0; /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -614,7 +614,7 @@ void BX_CPU_C::PCMPEQD_PqQq(BxInstruction_t *i) } /* 0F 77 */ -void BX_CPU_C::EMMS(BxInstruction_t *i) +void BX_CPU_C::EMMS(bxInstruction_c *i) { #if BX_SUPPORT_MMX @@ -635,16 +635,16 @@ void BX_CPU_C::EMMS(BxInstruction_t *i) } /* 0F 7E */ -void BX_CPU_C::MOVD_EdPd(BxInstruction_t *i) +void BX_CPU_C::MOVD_EdPd(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op = BX_READ_MMX_REG(i->nnn); + BxPackedMmxRegister op = BX_READ_MMX_REG(i->nnn()); /* op is a register or memory reference */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REG(i->rm, MMXUD0(op)); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REG(i->rm(), MMXUD0(op)); } else { write_virtual_dword(i->seg, i->rm_addr, &(MMXUD0(op))); @@ -656,16 +656,16 @@ void BX_CPU_C::MOVD_EdPd(BxInstruction_t *i) } /* 0F 7F */ -void BX_CPU_C::MOVQ_QqPq(BxInstruction_t *i) +void BX_CPU_C::MOVQ_QqPq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op = BX_READ_MMX_REG(i->nnn); + BxPackedMmxRegister op = BX_READ_MMX_REG(i->nnn()); /* op is a register or memory reference */ - if (i->mod == 0xc0) { - BX_WRITE_MMX_REG(i->rm, op); + if (i->mod() == 0xc0) { + BX_WRITE_MMX_REG(i->rm(), op); } else { write_virtual_qword(i->seg, i->rm_addr, (Bit64u *) &op); @@ -677,16 +677,16 @@ void BX_CPU_C::MOVQ_QqPq(BxInstruction_t *i) } /* 0F D1 */ -void BX_CPU_C::PSRLW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSRLW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -705,7 +705,7 @@ void BX_CPU_C::PSRLW_PqQq(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -713,16 +713,16 @@ void BX_CPU_C::PSRLW_PqQq(BxInstruction_t *i) } /* 0F D2 */ -void BX_CPU_C::PSRLD_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSRLD_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -739,7 +739,7 @@ void BX_CPU_C::PSRLD_PqQq(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -747,16 +747,16 @@ void BX_CPU_C::PSRLD_PqQq(BxInstruction_t *i) } /* 0F D3 */ -void BX_CPU_C::PSRLQ_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSRLQ_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -771,7 +771,7 @@ void BX_CPU_C::PSRLQ_PqQq(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -779,16 +779,16 @@ void BX_CPU_C::PSRLQ_PqQq(BxInstruction_t *i) } /* 0F D5 */ -void BX_CPU_C::PMULLW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PMULLW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -806,7 +806,7 @@ void BX_CPU_C::PMULLW_PqQq(BxInstruction_t *i) MMXUW3(result) = (Bit16u)(product4 & 0xFFFF); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -814,16 +814,16 @@ void BX_CPU_C::PMULLW_PqQq(BxInstruction_t *i) } /* 0F D8 */ -void BX_CPU_C::PSUBUSB_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSUBUSB_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -842,7 +842,7 @@ void BX_CPU_C::PSUBUSB_PqQq(BxInstruction_t *i) if(MMXUB7(op1) > MMXUB7(op2)) MMXUB7(result) = MMXUB7(op1) - MMXUB7(op2); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -850,16 +850,16 @@ void BX_CPU_C::PSUBUSB_PqQq(BxInstruction_t *i) } /* 0F D9 */ -void BX_CPU_C::PSUBUSW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSUBUSW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -874,7 +874,7 @@ void BX_CPU_C::PSUBUSW_PqQq(BxInstruction_t *i) if(MMXUW3(op1) > MMXUW3(op2)) MMXUW3(result) = MMXUW3(op1) - MMXUW3(op2); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -882,16 +882,16 @@ void BX_CPU_C::PSUBUSW_PqQq(BxInstruction_t *i) } /* 0F DB */ -void BX_CPU_C::PAND_PqQq(BxInstruction_t *i) +void BX_CPU_C::PAND_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -901,7 +901,7 @@ void BX_CPU_C::PAND_PqQq(BxInstruction_t *i) MMXUQ(op1) &= MMXUQ(op2); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -909,16 +909,16 @@ void BX_CPU_C::PAND_PqQq(BxInstruction_t *i) } /* 0F DC */ -void BX_CPU_C::PADDUSB_PqQq(BxInstruction_t *i) +void BX_CPU_C::PADDUSB_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -935,7 +935,7 @@ void BX_CPU_C::PADDUSB_PqQq(BxInstruction_t *i) MMXUB7(result) = SaturateWordSToByteU(Bit16s(MMXUB7(op1)) + Bit16s(MMXUB7(op2))); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -943,16 +943,16 @@ void BX_CPU_C::PADDUSB_PqQq(BxInstruction_t *i) } /* 0F DD */ -void BX_CPU_C::PADDUSW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PADDUSW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -965,7 +965,7 @@ void BX_CPU_C::PADDUSW_PqQq(BxInstruction_t *i) MMXUW3(result) = SaturateDwordSToWordU(Bit32s(MMXUW3(op1)) + Bit32s(MMXUW3(op2))); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -973,16 +973,16 @@ void BX_CPU_C::PADDUSW_PqQq(BxInstruction_t *i) } /* 0F DF */ -void BX_CPU_C::PANDN_PqQq(BxInstruction_t *i) +void BX_CPU_C::PANDN_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -992,7 +992,7 @@ void BX_CPU_C::PANDN_PqQq(BxInstruction_t *i) MMXUQ(result) = ~(MMXUQ(op1)) & MMXUQ(op2); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1000,16 +1000,16 @@ void BX_CPU_C::PANDN_PqQq(BxInstruction_t *i) } /* 0F E1 */ -void BX_CPU_C::PSRAW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSRAW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1037,7 +1037,7 @@ void BX_CPU_C::PSRAW_PqQq(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1045,16 +1045,16 @@ void BX_CPU_C::PSRAW_PqQq(BxInstruction_t *i) } /* 0F E2 */ -void BX_CPU_C::PSRAD_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSRAD_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1076,7 +1076,7 @@ void BX_CPU_C::PSRAD_PqQq(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1084,16 +1084,16 @@ void BX_CPU_C::PSRAD_PqQq(BxInstruction_t *i) } /* 0F E5 */ -void BX_CPU_C::PMULHW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PMULHW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1111,7 +1111,7 @@ void BX_CPU_C::PMULHW_PqQq(BxInstruction_t *i) MMXUW3(result) = (Bit16u)(product4 >> 16); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1119,16 +1119,16 @@ void BX_CPU_C::PMULHW_PqQq(BxInstruction_t *i) } /* 0F E8 */ -void BX_CPU_C::PSUBSB_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSUBSB_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1145,7 +1145,7 @@ void BX_CPU_C::PSUBSB_PqQq(BxInstruction_t *i) MMXSB7(result) = SaturateWordSToByteS(Bit16s(MMXSB7(op1)) - Bit16s(MMXSB7(op2))); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1153,16 +1153,16 @@ void BX_CPU_C::PSUBSB_PqQq(BxInstruction_t *i) } /* 0F E9 */ -void BX_CPU_C::PSUBSW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSUBSW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1175,7 +1175,7 @@ void BX_CPU_C::PSUBSW_PqQq(BxInstruction_t *i) MMXSW3(result) = SaturateDwordSToWordS(Bit32s(MMXSW3(op1)) - Bit32s(MMXSW3(op2))); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1183,16 +1183,16 @@ void BX_CPU_C::PSUBSW_PqQq(BxInstruction_t *i) } /* 0F EB */ -void BX_CPU_C::POR_PqQq(BxInstruction_t *i) +void BX_CPU_C::POR_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1202,7 +1202,7 @@ void BX_CPU_C::POR_PqQq(BxInstruction_t *i) MMXUQ(op1) |= MMXUQ(op2); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1210,16 +1210,16 @@ void BX_CPU_C::POR_PqQq(BxInstruction_t *i) } /* 0F EC */ -void BX_CPU_C::PADDSB_PqQq(BxInstruction_t *i) +void BX_CPU_C::PADDSB_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1236,7 +1236,7 @@ void BX_CPU_C::PADDSB_PqQq(BxInstruction_t *i) MMXSB7(result) = SaturateWordSToByteS(Bit16s(MMXSB7(op1)) + Bit16s(MMXSB7(op2))); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1244,16 +1244,16 @@ void BX_CPU_C::PADDSB_PqQq(BxInstruction_t *i) } /* 0F ED */ -void BX_CPU_C::PADDSW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PADDSW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1266,7 +1266,7 @@ void BX_CPU_C::PADDSW_PqQq(BxInstruction_t *i) MMXSW3(result) = SaturateDwordSToWordS(Bit32s(MMXSW3(op1)) + Bit32s(MMXSW3(op2))); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1274,16 +1274,16 @@ void BX_CPU_C::PADDSW_PqQq(BxInstruction_t *i) } /* 0F EF */ -void BX_CPU_C::PXOR_PqQq(BxInstruction_t *i) +void BX_CPU_C::PXOR_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1293,7 +1293,7 @@ void BX_CPU_C::PXOR_PqQq(BxInstruction_t *i) MMXUQ(op1) ^= MMXUQ(op2); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1301,16 +1301,16 @@ void BX_CPU_C::PXOR_PqQq(BxInstruction_t *i) } /* 0F F1 */ -void BX_CPU_C::PSLLW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSLLW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1329,7 +1329,7 @@ void BX_CPU_C::PSLLW_PqQq(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1337,16 +1337,16 @@ void BX_CPU_C::PSLLW_PqQq(BxInstruction_t *i) } /* 0F F2 */ -void BX_CPU_C::PSLLD_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSLLD_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1363,7 +1363,7 @@ void BX_CPU_C::PSLLD_PqQq(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1371,16 +1371,16 @@ void BX_CPU_C::PSLLD_PqQq(BxInstruction_t *i) } /* 0F F3 */ -void BX_CPU_C::PSLLQ_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSLLQ_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1395,7 +1395,7 @@ void BX_CPU_C::PSLLQ_PqQq(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1403,16 +1403,16 @@ void BX_CPU_C::PSLLQ_PqQq(BxInstruction_t *i) } /* 0F F5 */ -void BX_CPU_C::PMADDWD_PqQq(BxInstruction_t *i) +void BX_CPU_C::PMADDWD_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2, result; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1434,7 +1434,7 @@ void BX_CPU_C::PMADDWD_PqQq(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, result); + BX_WRITE_MMX_REG(i->nnn(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1442,16 +1442,16 @@ void BX_CPU_C::PMADDWD_PqQq(BxInstruction_t *i) } /* 0F F8 */ -void BX_CPU_C::PSUBB_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSUBB_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1468,7 +1468,7 @@ void BX_CPU_C::PSUBB_PqQq(BxInstruction_t *i) MMXUB7(op1) -= MMXUB7(op2); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1476,16 +1476,16 @@ void BX_CPU_C::PSUBB_PqQq(BxInstruction_t *i) } /* 0F F9 */ -void BX_CPU_C::PSUBW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSUBW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1498,7 +1498,7 @@ void BX_CPU_C::PSUBW_PqQq(BxInstruction_t *i) MMXUW3(op1) -= MMXUW3(op2); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1506,16 +1506,16 @@ void BX_CPU_C::PSUBW_PqQq(BxInstruction_t *i) } /* 0F FA */ -void BX_CPU_C::PSUBD_PqQq(BxInstruction_t *i) +void BX_CPU_C::PSUBD_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1526,7 +1526,7 @@ void BX_CPU_C::PSUBD_PqQq(BxInstruction_t *i) MMXUD1(op1) -= MMXUD1(op2); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1534,16 +1534,16 @@ void BX_CPU_C::PSUBD_PqQq(BxInstruction_t *i) } /* 0F FC */ -void BX_CPU_C::PADDB_PqQq(BxInstruction_t *i) +void BX_CPU_C::PADDB_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1561,7 +1561,7 @@ void BX_CPU_C::PADDB_PqQq(BxInstruction_t *i) MMXUB7(op1) += MMXUB7(op2); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1569,16 +1569,16 @@ void BX_CPU_C::PADDB_PqQq(BxInstruction_t *i) } /* 0F FD */ -void BX_CPU_C::PADDW_PqQq(BxInstruction_t *i) +void BX_CPU_C::PADDW_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1591,7 +1591,7 @@ void BX_CPU_C::PADDW_PqQq(BxInstruction_t *i) MMXUW3(op1) += MMXUW3(op2); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1599,16 +1599,16 @@ void BX_CPU_C::PADDW_PqQq(BxInstruction_t *i) } /* 0F FE */ -void BX_CPU_C::PADDD_PqQq(BxInstruction_t *i) +void BX_CPU_C::PADDD_PqQq(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn), op2; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_MMX_REG(i->rm); + if (i->mod() == 0xc0) { + op2 = BX_READ_MMX_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -1619,7 +1619,7 @@ void BX_CPU_C::PADDD_PqQq(BxInstruction_t *i) MMXUD1(op1) += MMXUD1(op2); /* now write result back to destination */ - BX_WRITE_MMX_REG(i->nnn, op1); + BX_WRITE_MMX_REG(i->nnn(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1627,13 +1627,13 @@ void BX_CPU_C::PADDD_PqQq(BxInstruction_t *i) } /* 0F 71 GrpA 010 */ -void BX_CPU_C::PSRLW_PqIb(BxInstruction_t *i) +void BX_CPU_C::PSRLW_PqIb(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm); - Bit8u shift = i->Ib; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm()); + Bit8u shift = i->Ib(); if(shift > 15) MMXUQ(op1) = 0; else @@ -1645,7 +1645,7 @@ void BX_CPU_C::PSRLW_PqIb(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->rm, op1); + BX_WRITE_MMX_REG(i->rm(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1653,13 +1653,13 @@ void BX_CPU_C::PSRLW_PqIb(BxInstruction_t *i) } /* 0F 71 GrpA 100 */ -void BX_CPU_C::PSRAW_PqIb(BxInstruction_t *i) +void BX_CPU_C::PSRAW_PqIb(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm), result; - Bit8u shift = i->Ib; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm()), result; + Bit8u shift = i->Ib(); if(shift > 15) { MMXUW0(result) = (MMXUW0(op1) & 0x8000) ? 0xFFFF : 0; @@ -1680,7 +1680,7 @@ void BX_CPU_C::PSRAW_PqIb(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->rm, result); + BX_WRITE_MMX_REG(i->rm(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1688,13 +1688,13 @@ void BX_CPU_C::PSRAW_PqIb(BxInstruction_t *i) } /* 0F 71 GrpA 110 */ -void BX_CPU_C::PSLLW_PqIb(BxInstruction_t *i) +void BX_CPU_C::PSLLW_PqIb(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm); - Bit8u shift = i->Ib; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm()); + Bit8u shift = i->Ib(); if(shift > 15) MMXUQ(op1) = 0; else @@ -1706,7 +1706,7 @@ void BX_CPU_C::PSLLW_PqIb(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->rm, op1); + BX_WRITE_MMX_REG(i->rm(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1715,13 +1715,13 @@ void BX_CPU_C::PSLLW_PqIb(BxInstruction_t *i) /* 0F 72 GrpA 010 */ -void BX_CPU_C::PSRLD_PqIb(BxInstruction_t *i) +void BX_CPU_C::PSRLD_PqIb(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm); - Bit8u shift = i->Ib; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm()); + Bit8u shift = i->Ib(); if(shift > 31) MMXUQ(op1) = 0; else @@ -1731,7 +1731,7 @@ void BX_CPU_C::PSRLD_PqIb(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->rm, op1); + BX_WRITE_MMX_REG(i->rm(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1739,13 +1739,13 @@ void BX_CPU_C::PSRLD_PqIb(BxInstruction_t *i) } /* 0F 72 GrpA 100 */ -void BX_CPU_C::PSRAD_PqIb(BxInstruction_t *i) +void BX_CPU_C::PSRAD_PqIb(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm), result; - Bit8u shift = i->Ib; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm()), result; + Bit8u shift = i->Ib(); if(shift > 31) { MMXUD0(result) = (MMXUD0(op1) & 0x80000000) ? 0xFFFFFFFF : 0; @@ -1760,7 +1760,7 @@ void BX_CPU_C::PSRAD_PqIb(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->rm, result); + BX_WRITE_MMX_REG(i->rm(), result); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1768,13 +1768,13 @@ void BX_CPU_C::PSRAD_PqIb(BxInstruction_t *i) } /* 0F 72 GrpA 110 */ -void BX_CPU_C::PSLLD_PqIb(BxInstruction_t *i) +void BX_CPU_C::PSLLD_PqIb(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm); - Bit8u shift = i->Ib; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm()); + Bit8u shift = i->Ib(); if(shift > 31) MMXUQ(op1) = 0; else @@ -1784,7 +1784,7 @@ void BX_CPU_C::PSLLD_PqIb(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->rm, op1); + BX_WRITE_MMX_REG(i->rm(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1792,13 +1792,13 @@ void BX_CPU_C::PSLLD_PqIb(BxInstruction_t *i) } /* 0F 73 GrpA 010 */ -void BX_CPU_C::PSRLQ_PqIb(BxInstruction_t *i) +void BX_CPU_C::PSRLQ_PqIb(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm); - Bit8u shift = i->Ib; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm()); + Bit8u shift = i->Ib(); if(shift > 63) { MMXUQ(op1) = 0; @@ -1808,7 +1808,7 @@ void BX_CPU_C::PSRLQ_PqIb(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->rm, op1); + BX_WRITE_MMX_REG(i->rm(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); @@ -1816,13 +1816,13 @@ void BX_CPU_C::PSRLQ_PqIb(BxInstruction_t *i) } /* 0F 73 GrpA 110 */ -void BX_CPU_C::PSLLQ_PqIb(BxInstruction_t *i) +void BX_CPU_C::PSLLQ_PqIb(bxInstruction_c *i) { #if BX_SUPPORT_MMX BX_CPU_THIS_PTR PrepareMmxInstruction(); - BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm); - Bit8u shift = i->Ib; + BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->rm()); + Bit8u shift = i->Ib(); if(shift > 63) { MMXUQ(op1) = 0; @@ -1832,7 +1832,7 @@ void BX_CPU_C::PSLLQ_PqIb(BxInstruction_t *i) } /* now write result back to destination */ - BX_WRITE_MMX_REG(i->rm, op1); + BX_WRITE_MMX_REG(i->rm(), op1); #else BX_INFO(("MMX Instructions Set Not Implemented")); UndefinedOpcode(i); diff --git a/bochs/cpu/mult16.cc b/bochs/cpu/mult16.cc index 7c83dd47f..9d817d4cc 100644 --- a/bochs/cpu/mult16.cc +++ b/bochs/cpu/mult16.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: mult16.cc,v 1.6 2001-10-03 13:10:37 bdenney Exp $ +// $Id: mult16.cc,v 1.7 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -37,7 +37,7 @@ void -BX_CPU_C::MUL_AXEw(BxInstruction_t *i) +BX_CPU_C::MUL_AXEw(bxInstruction_c *i) { Bit16u op1_16, op2_16, product_16h, product_16l; Bit32u product_32; @@ -46,8 +46,8 @@ BX_CPU_C::MUL_AXEw(BxInstruction_t *i) op1_16 = AX; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -75,7 +75,7 @@ BX_CPU_C::MUL_AXEw(BxInstruction_t *i) void -BX_CPU_C::IMUL_AXEw(BxInstruction_t *i) +BX_CPU_C::IMUL_AXEw(bxInstruction_c *i) { Bit16s op1_16, op2_16; Bit32s product_32; @@ -84,8 +84,8 @@ BX_CPU_C::IMUL_AXEw(BxInstruction_t *i) op1_16 = AX; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -121,7 +121,7 @@ BX_CPU_C::IMUL_AXEw(BxInstruction_t *i) void -BX_CPU_C::DIV_AXEw(BxInstruction_t *i) +BX_CPU_C::DIV_AXEw(bxInstruction_c *i) { Bit16u op2_16, remainder_16, quotient_16l; Bit32u op1_32, quotient_32; @@ -129,8 +129,8 @@ BX_CPU_C::DIV_AXEw(BxInstruction_t *i) op1_32 = (((Bit32u) DX) << 16) | ((Bit32u) AX); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -164,7 +164,7 @@ BX_CPU_C::DIV_AXEw(BxInstruction_t *i) void -BX_CPU_C::IDIV_AXEw(BxInstruction_t *i) +BX_CPU_C::IDIV_AXEw(bxInstruction_c *i) { Bit16s op2_16, remainder_16, quotient_16l; Bit32s op1_32, quotient_32; @@ -172,8 +172,8 @@ BX_CPU_C::IDIV_AXEw(BxInstruction_t *i) op1_32 = ((((Bit32u) DX) << 16) | ((Bit32u) AX)); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -207,7 +207,7 @@ BX_CPU_C::IDIV_AXEw(BxInstruction_t *i) void -BX_CPU_C::IMUL_GwEwIw(BxInstruction_t *i) +BX_CPU_C::IMUL_GwEwIw(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("IMUL_GvEvIv() unsupported on 8086!")); @@ -218,11 +218,11 @@ BX_CPU_C::IMUL_GwEwIw(BxInstruction_t *i) Bit16s op2_16, op3_16; Bit32s product_32; - op3_16 = i->Iw; + op3_16 = i->Iw(); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -234,7 +234,7 @@ BX_CPU_C::IMUL_GwEwIw(BxInstruction_t *i) product_16l = (product_32 & 0xFFFF); /* now write product back to destination */ - BX_WRITE_16BIT_REG(i->nnn, product_16l); + BX_WRITE_16BIT_REG(i->nnn(), product_16l); /* set eflags: * IMUL affects the following flags: C,O @@ -252,7 +252,7 @@ BX_CPU_C::IMUL_GwEwIw(BxInstruction_t *i) } void -BX_CPU_C::IMUL_GwEw(BxInstruction_t *i) +BX_CPU_C::IMUL_GwEw(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("IMUL_GvEv() unsupported on 8086!")); @@ -263,22 +263,22 @@ BX_CPU_C::IMUL_GwEw(BxInstruction_t *i) Bit32s product_32; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_virtual_word(i->seg, i->rm_addr, (Bit16u *) &op2_16); } - op1_16 = BX_READ_16BIT_REG(i->nnn); + op1_16 = BX_READ_16BIT_REG(i->nnn()); product_32 = op1_16 * op2_16; product_16l = (product_32 & 0xFFFF); /* now write product back to destination */ - BX_WRITE_16BIT_REG(i->nnn, product_16l); + BX_WRITE_16BIT_REG(i->nnn(), product_16l); /* set eflags: * IMUL affects the following flags: C,O diff --git a/bochs/cpu/mult32.cc b/bochs/cpu/mult32.cc index d46ed3699..779b5cee9 100644 --- a/bochs/cpu/mult32.cc +++ b/bochs/cpu/mult32.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: mult32.cc,v 1.7 2002-09-15 01:00:19 kevinlawton Exp $ +// $Id: mult32.cc,v 1.8 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -42,7 +42,7 @@ void -BX_CPU_C::MUL_EAXEd(BxInstruction_t *i) +BX_CPU_C::MUL_EAXEd(bxInstruction_c *i) { Bit32u op1_32, op2_32, product_32h, product_32l; Bit64u product_64; @@ -51,8 +51,8 @@ BX_CPU_C::MUL_EAXEd(BxInstruction_t *i) op1_32 = EAX; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -80,7 +80,7 @@ BX_CPU_C::MUL_EAXEd(BxInstruction_t *i) void -BX_CPU_C::IMUL_EAXEd(BxInstruction_t *i) +BX_CPU_C::IMUL_EAXEd(bxInstruction_c *i) { Bit32s op1_32, op2_32; Bit64s product_64; @@ -89,8 +89,8 @@ BX_CPU_C::IMUL_EAXEd(BxInstruction_t *i) op1_32 = EAX; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -126,7 +126,7 @@ BX_CPU_C::IMUL_EAXEd(BxInstruction_t *i) void -BX_CPU_C::DIV_EAXEd(BxInstruction_t *i) +BX_CPU_C::DIV_EAXEd(bxInstruction_c *i) { Bit32u op2_32, remainder_32, quotient_32l; Bit64u op1_64, quotient_64; @@ -134,8 +134,8 @@ BX_CPU_C::DIV_EAXEd(BxInstruction_t *i) op1_64 = (((Bit64u) EDX) << 32) + ((Bit64u) EAX); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -165,7 +165,7 @@ BX_CPU_C::DIV_EAXEd(BxInstruction_t *i) void -BX_CPU_C::IDIV_EAXEd(BxInstruction_t *i) +BX_CPU_C::IDIV_EAXEd(bxInstruction_c *i) { Bit32s op2_32, remainder_32, quotient_32l; Bit64s op1_64, quotient_64; @@ -173,8 +173,8 @@ BX_CPU_C::IDIV_EAXEd(BxInstruction_t *i) op1_64 = (((Bit64u) EDX) << 32) | ((Bit64u) EAX); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -204,7 +204,7 @@ BX_CPU_C::IDIV_EAXEd(BxInstruction_t *i) void -BX_CPU_C::IMUL_GdEdId(BxInstruction_t *i) +BX_CPU_C::IMUL_GdEdId(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("IMUL_GdEdId() unsupported on 8086!")); @@ -214,11 +214,11 @@ BX_CPU_C::IMUL_GdEdId(BxInstruction_t *i) Bit32s op2_32, op3_32, product_32; Bit64s product_64; - op3_32 = i->Id; + op3_32 = i->Id(); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -229,7 +229,7 @@ BX_CPU_C::IMUL_GdEdId(BxInstruction_t *i) product_64 = ((Bit64s) op2_32) * ((Bit64s) op3_32); /* now write product back to destination */ - BX_WRITE_32BIT_REGZ(i->nnn, product_32); + BX_WRITE_32BIT_REGZ(i->nnn(), product_32); /* set eflags: * IMUL affects the following flags: C,O @@ -248,7 +248,7 @@ BX_CPU_C::IMUL_GdEdId(BxInstruction_t *i) void -BX_CPU_C::IMUL_GdEd(BxInstruction_t *i) +BX_CPU_C::IMUL_GdEd(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("IMUL_GvEv() unsupported on 8086!")); @@ -258,21 +258,21 @@ BX_CPU_C::IMUL_GdEd(BxInstruction_t *i) Bit64s product_64; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_virtual_dword(i->seg, i->rm_addr, (Bit32u *) &op2_32); } - op1_32 = BX_READ_32BIT_REG(i->nnn); + op1_32 = BX_READ_32BIT_REG(i->nnn()); product_32 = op1_32 * op2_32; product_64 = ((Bit64s) op1_32) * ((Bit64s) op2_32); /* now write product back to destination */ - BX_WRITE_32BIT_REGZ(i->nnn, product_32); + BX_WRITE_32BIT_REGZ(i->nnn(), product_32); /* set eflags: * IMUL affects the following flags: C,O diff --git a/bochs/cpu/mult64.cc b/bochs/cpu/mult64.cc index a7064c6e0..d0d31c468 100644 --- a/bochs/cpu/mult64.cc +++ b/bochs/cpu/mult64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: mult64.cc,v 1.1 2002-09-13 15:53:22 kevinlawton Exp $ +// $Id: mult64.cc,v 1.2 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -231,7 +231,7 @@ long_idiv(Bit128s *quotient,Bit64s *remainder,Bit128s *dividend,Bit64s divisor) } void -BX_CPU_C::MUL_RAXEq(BxInstruction_t *i) +BX_CPU_C::MUL_RAXEq(bxInstruction_c *i) { Bit64u op1_64, op2_64; Bit128u product_128; @@ -240,8 +240,8 @@ BX_CPU_C::MUL_RAXEq(BxInstruction_t *i) op1_64 = RAX; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -270,7 +270,7 @@ BX_CPU_C::MUL_RAXEq(BxInstruction_t *i) void -BX_CPU_C::IMUL_RAXEq(BxInstruction_t *i) +BX_CPU_C::IMUL_RAXEq(bxInstruction_c *i) { Bit64s op1_64, op2_64; Bit128s product_128; @@ -279,8 +279,8 @@ BX_CPU_C::IMUL_RAXEq(BxInstruction_t *i) op1_64 = RAX; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -317,7 +317,7 @@ BX_CPU_C::IMUL_RAXEq(BxInstruction_t *i) void -BX_CPU_C::DIV_RAXEq(BxInstruction_t *i) +BX_CPU_C::DIV_RAXEq(bxInstruction_c *i) { Bit64u op2_64, remainder_64, quotient_64l; Bit128u op1_128, quotient_128; @@ -326,8 +326,8 @@ BX_CPU_C::DIV_RAXEq(BxInstruction_t *i) op1_128.hi = RDX; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -360,7 +360,7 @@ BX_CPU_C::DIV_RAXEq(BxInstruction_t *i) void -BX_CPU_C::IDIV_RAXEq(BxInstruction_t *i) +BX_CPU_C::IDIV_RAXEq(bxInstruction_c *i) { Bit64s op2_64, remainder_64, quotient_64l; Bit128s op1_128, quotient_128; @@ -369,8 +369,8 @@ BX_CPU_C::IDIV_RAXEq(BxInstruction_t *i) op1_128.hi = RDX; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -403,7 +403,7 @@ BX_CPU_C::IDIV_RAXEq(BxInstruction_t *i) void -BX_CPU_C::IMUL_GqEqId(BxInstruction_t *i) +BX_CPU_C::IMUL_GqEqId(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("IMUL_GdEdId() unsupported on 8086!")); @@ -413,11 +413,11 @@ BX_CPU_C::IMUL_GqEqId(BxInstruction_t *i) Bit64s op2_64, op3_64, product_64; Bit128s product_128; - op3_64 = (Bit32s) i->Id; + op3_64 = (Bit32s) i->Id(); /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -429,7 +429,7 @@ BX_CPU_C::IMUL_GqEqId(BxInstruction_t *i) long_imul(&product_128,op2_64,op3_64); /* now write product back to destination */ - BX_WRITE_64BIT_REG(i->nnn, product_64); + BX_WRITE_64BIT_REG(i->nnn(), product_64); /* set eflags: * IMUL affects the following flags: C,O @@ -448,7 +448,7 @@ BX_CPU_C::IMUL_GqEqId(BxInstruction_t *i) void -BX_CPU_C::IMUL_GqEq(BxInstruction_t *i) +BX_CPU_C::IMUL_GqEq(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("IMUL_GvEv() unsupported on 8086!")); @@ -458,22 +458,22 @@ BX_CPU_C::IMUL_GqEq(BxInstruction_t *i) Bit128s product_128; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op2_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_virtual_qword(i->seg, i->rm_addr, (Bit64u *) &op2_64); } - op1_64 = BX_READ_64BIT_REG(i->nnn); + op1_64 = BX_READ_64BIT_REG(i->nnn()); product_64 = op1_64 * op2_64; //product_128 = ((Bit128s) op1_64) * ((Bit128s) op2_64); long_imul(&product_128,op1_64,op2_64); /* now write product back to destination */ - BX_WRITE_64BIT_REG(i->nnn, product_64); + BX_WRITE_64BIT_REG(i->nnn(), product_64); /* set eflags: * IMUL affects the following flags: C,O diff --git a/bochs/cpu/mult8.cc b/bochs/cpu/mult8.cc index 97fb82f19..41b7efd97 100644 --- a/bochs/cpu/mult8.cc +++ b/bochs/cpu/mult8.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: mult8.cc,v 1.7 2002-09-13 21:34:00 kevinlawton Exp $ +// $Id: mult8.cc,v 1.8 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -36,7 +36,7 @@ void -BX_CPU_C::MUL_ALEb(BxInstruction_t *i) +BX_CPU_C::MUL_ALEb(bxInstruction_c *i) { Bit8u op2, op1; Bit16u product_16; @@ -45,8 +45,8 @@ BX_CPU_C::MUL_ALEb(BxInstruction_t *i) op1 = AL; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -69,7 +69,7 @@ BX_CPU_C::MUL_ALEb(BxInstruction_t *i) void -BX_CPU_C::IMUL_ALEb(BxInstruction_t *i) +BX_CPU_C::IMUL_ALEb(bxInstruction_c *i) { Bit8s op2, op1; Bit16s product_16; @@ -79,8 +79,8 @@ BX_CPU_C::IMUL_ALEb(BxInstruction_t *i) op1 = AL; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -110,7 +110,7 @@ BX_CPU_C::IMUL_ALEb(BxInstruction_t *i) void -BX_CPU_C::DIV_ALEb(BxInstruction_t *i) +BX_CPU_C::DIV_ALEb(bxInstruction_c *i) { Bit8u op2, quotient_8l, remainder_8; Bit16u quotient_16, op1; @@ -119,8 +119,8 @@ BX_CPU_C::DIV_ALEb(BxInstruction_t *i) op1 = AX; /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -154,7 +154,7 @@ BX_CPU_C::DIV_ALEb(BxInstruction_t *i) void -BX_CPU_C::IDIV_ALEb(BxInstruction_t *i) +BX_CPU_C::IDIV_ALEb(bxInstruction_c *i) { Bit8s op2, quotient_8l, remainder_8; Bit16s quotient_16, op1; @@ -164,8 +164,8 @@ BX_CPU_C::IDIV_ALEb(BxInstruction_t *i) /* op2 is a register or memory reference */ - if (i->mod == 0xc0) { - op2 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ diff --git a/bochs/cpu/paging.cc b/bochs/cpu/paging.cc index eb4cbca3f..23f570056 100644 --- a/bochs/cpu/paging.cc +++ b/bochs/cpu/paging.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: paging.cc,v 1.26 2002-09-16 21:55:57 kevinlawton Exp $ +// $Id: paging.cc,v 1.27 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -514,7 +514,7 @@ BX_CPU_C::TLB_flush(Boolean invalidateGlobal) } void -BX_CPU_C::INVLPG(BxInstruction_t* i) +BX_CPU_C::INVLPG(bxInstruction_c* i) { #if BX_CPU_LEVEL >= 4 Bit32u TLB_index; @@ -523,7 +523,7 @@ BX_CPU_C::INVLPG(BxInstruction_t* i) invalidate_prefetch_q(); // Operand must not be a register - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_INFO(("INVLPG: op is a register")); UndefinedOpcode(i); } @@ -1383,7 +1383,7 @@ BX_CPU_C::access_linear(Bit32u laddr, unsigned length, unsigned pl, } void -BX_CPU_C::INVLPG(BxInstruction_t* i) +BX_CPU_C::INVLPG(bxInstruction_c* i) {} #endif // BX_SUPPORT_PAGING diff --git a/bochs/cpu/proc_ctrl.cc b/bochs/cpu/proc_ctrl.cc index 6fb003736..0ffa08952 100644 --- a/bochs/cpu/proc_ctrl.cc +++ b/bochs/cpu/proc_ctrl.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: proc_ctrl.cc,v 1.39 2002-09-17 22:14:33 bdenney Exp $ +// $Id: proc_ctrl.cc,v 1.40 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -45,7 +45,7 @@ void -BX_CPU_C::UndefinedOpcode(BxInstruction_t *i) +BX_CPU_C::UndefinedOpcode(bxInstruction_c *i) { BX_DEBUG(("UndefinedOpcode: %02x causes exception 6", (unsigned) i->b1)); @@ -53,12 +53,12 @@ BX_CPU_C::UndefinedOpcode(BxInstruction_t *i) } void -BX_CPU_C::NOP(BxInstruction_t *i) +BX_CPU_C::NOP(bxInstruction_c *i) { } void -BX_CPU_C::HLT(BxInstruction_t *i) +BX_CPU_C::HLT(bxInstruction_c *i) { // hack to panic if HLT comes from BIOS if ( BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value == 0xf000 ) @@ -94,7 +94,7 @@ BX_CPU_C::HLT(BxInstruction_t *i) void -BX_CPU_C::CLTS(BxInstruction_t *i) +BX_CPU_C::CLTS(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("CLTS: not implemented for < 286")); @@ -118,7 +118,7 @@ BX_CPU_C::CLTS(BxInstruction_t *i) } void -BX_CPU_C::INVD(BxInstruction_t *i) +BX_CPU_C::INVD(bxInstruction_c *i) { BX_INFO(("---------------")); BX_INFO(("- INVD called -")); @@ -140,7 +140,7 @@ BX_CPU_C::INVD(BxInstruction_t *i) } void -BX_CPU_C::WBINVD(BxInstruction_t *i) +BX_CPU_C::WBINVD(bxInstruction_c *i) { BX_INFO(("WBINVD: (ignoring)")); @@ -160,7 +160,7 @@ BX_CPU_C::WBINVD(BxInstruction_t *i) } void -BX_CPU_C::MOV_DdRd(BxInstruction_t *i) +BX_CPU_C::MOV_DdRd(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOV_DdRd: not supported on < 386")); @@ -176,7 +176,7 @@ BX_CPU_C::MOV_DdRd(BxInstruction_t *i) * reg field specifies which special register */ - if (i->mod != 0xc0) { + if (i->mod() != 0xc0) { BX_PANIC(("MOV_DdRd(): rm field not a register!")); } @@ -188,12 +188,12 @@ BX_CPU_C::MOV_DdRd(BxInstruction_t *i) exception(BX_GP_EXCEPTION, 0, 0); } - val_32 = BX_READ_32BIT_REG(i->rm); + val_32 = BX_READ_32BIT_REG(i->rm()); if (bx_dbg.dreg) BX_INFO(("MOV_DdRd: DR[%u]=%08xh unhandled", - (unsigned) i->nnn, (unsigned) val_32)); + (unsigned) i->nnn(), (unsigned) val_32)); - switch (i->nnn) { + switch (i->nnn()) { case 0: // DR0 BX_CPU_THIS_PTR dr0 = val_32; break; @@ -212,7 +212,7 @@ BX_CPU_C::MOV_DdRd(BxInstruction_t *i) // DR4 aliased to DR6 by default. With Debug Extensions on, // access to DR4 causes #UD #if BX_CPU_LEVEL >= 4 - if ( (i->nnn == 4) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { + if ( (i->nnn() == 4) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { // Debug extensions on BX_INFO(("MOV_DdRd: access to DR4 causes #UD")); UndefinedOpcode(i); @@ -238,7 +238,7 @@ BX_CPU_C::MOV_DdRd(BxInstruction_t *i) // DR5 aliased to DR7 by default. With Debug Extensions on, // access to DR5 causes #UD #if BX_CPU_LEVEL >= 4 - if ( (i->nnn == 5) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { + if ( (i->nnn() == 5) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { // Debug extensions (CR4.DE) on BX_INFO(("MOV_DdRd: access to DR5 causes #UD")); UndefinedOpcode(i); @@ -291,7 +291,7 @@ BX_CPU_C::MOV_DdRd(BxInstruction_t *i) } void -BX_CPU_C::MOV_RdDd(BxInstruction_t *i) +BX_CPU_C::MOV_RdDd(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOV_RdDd: not supported on < 386")); @@ -303,7 +303,7 @@ BX_CPU_C::MOV_RdDd(BxInstruction_t *i) exception(BX_GP_EXCEPTION, 0, 0); } - if (i->mod != 0xc0) { + if (i->mod() != 0xc0) { BX_PANIC(("MOV_RdDd(): rm field not a register!")); UndefinedOpcode(i); } @@ -315,9 +315,9 @@ BX_CPU_C::MOV_RdDd(BxInstruction_t *i) } if (bx_dbg.dreg) - BX_INFO(("MOV_RdDd: DR%u not implemented yet", i->nnn)); + BX_INFO(("MOV_RdDd: DR%u not implemented yet", i->nnn())); - switch (i->nnn) { + switch (i->nnn()) { case 0: // DR0 val_32 = BX_CPU_THIS_PTR dr0; break; @@ -336,7 +336,7 @@ BX_CPU_C::MOV_RdDd(BxInstruction_t *i) // DR4 aliased to DR6 by default. With Debug Extensions on, // access to DR4 causes #UD #if BX_CPU_LEVEL >= 4 - if ( (i->nnn == 4) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { + if ( (i->nnn() == 4) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { // Debug extensions on BX_INFO(("MOV_RdDd: access to DR4 causes #UD")); UndefinedOpcode(i); @@ -350,7 +350,7 @@ BX_CPU_C::MOV_RdDd(BxInstruction_t *i) // DR5 aliased to DR7 by default. With Debug Extensions on, // access to DR5 causes #UD #if BX_CPU_LEVEL >= 4 - if ( (i->nnn == 5) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { + if ( (i->nnn() == 5) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { // Debug extensions on BX_INFO(("MOV_RdDd: access to DR5 causes #UD")); UndefinedOpcode(i); @@ -363,13 +363,13 @@ BX_CPU_C::MOV_RdDd(BxInstruction_t *i) BX_PANIC(("MOV_RdDd: control register index out of range")); val_32 = 0; } - BX_WRITE_32BIT_REGZ(i->rm, val_32); + BX_WRITE_32BIT_REGZ(i->rm(), val_32); #endif } #if BX_SUPPORT_X86_64 void -BX_CPU_C::MOV_DqRq(BxInstruction_t *i) +BX_CPU_C::MOV_DqRq(bxInstruction_c *i) { Bit64u val_64; @@ -382,7 +382,7 @@ BX_CPU_C::MOV_DqRq(BxInstruction_t *i) * reg field specifies which special register */ - if (i->mod != 0xc0) { + if (i->mod() != 0xc0) { BX_PANIC(("MOV_DqRq(): rm field not a register!")); } @@ -394,12 +394,12 @@ BX_CPU_C::MOV_DqRq(BxInstruction_t *i) exception(BX_GP_EXCEPTION, 0, 0); } - val_64 = BX_READ_64BIT_REG(i->rm); + val_64 = BX_READ_64BIT_REG(i->rm()); if (bx_dbg.dreg) BX_INFO(("MOV_DqRq: DR[%u]=%08xh unhandled", - (unsigned) i->nnn, (unsigned) val_64)); + (unsigned) i->nnn(), (unsigned) val_64)); - switch (i->nnn) { + switch (i->nnn()) { case 0: // DR0 BX_CPU_THIS_PTR dr0 = val_64; break; @@ -418,7 +418,7 @@ BX_CPU_C::MOV_DqRq(BxInstruction_t *i) // DR4 aliased to DR6 by default. With Debug Extensions on, // access to DR4 causes #UD #if BX_CPU_LEVEL >= 4 - if ( (i->nnn == 4) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { + if ( (i->nnn() == 4) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { // Debug extensions on BX_INFO(("MOV_DqRq: access to DR4 causes #UD")); UndefinedOpcode(i); @@ -444,7 +444,7 @@ BX_CPU_C::MOV_DqRq(BxInstruction_t *i) // DR5 aliased to DR7 by default. With Debug Extensions on, // access to DR5 causes #UD #if BX_CPU_LEVEL >= 4 - if ( (i->nnn == 5) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { + if ( (i->nnn() == 5) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { // Debug extensions (CR4.DE) on BX_INFO(("MOV_DqRq: access to DR5 causes #UD")); UndefinedOpcode(i); @@ -498,7 +498,7 @@ BX_CPU_C::MOV_DqRq(BxInstruction_t *i) #if BX_SUPPORT_X86_64 void -BX_CPU_C::MOV_RqDq(BxInstruction_t *i) +BX_CPU_C::MOV_RqDq(bxInstruction_c *i) { Bit64u val_64; @@ -507,7 +507,7 @@ BX_CPU_C::MOV_RqDq(BxInstruction_t *i) exception(BX_GP_EXCEPTION, 0, 0); } - if (i->mod != 0xc0) { + if (i->mod() != 0xc0) { BX_PANIC(("MOV_RqDq(): rm field not a register!")); UndefinedOpcode(i); } @@ -519,9 +519,9 @@ BX_CPU_C::MOV_RqDq(BxInstruction_t *i) } if (bx_dbg.dreg) - BX_INFO(("MOV_RqDq: DR%u not implemented yet", i->nnn)); + BX_INFO(("MOV_RqDq: DR%u not implemented yet", i->nnn())); - switch (i->nnn) { + switch (i->nnn()) { case 0: // DR0 val_64 = BX_CPU_THIS_PTR dr0; break; @@ -540,7 +540,7 @@ BX_CPU_C::MOV_RqDq(BxInstruction_t *i) // DR4 aliased to DR6 by default. With Debug Extensions on, // access to DR4 causes #UD #if BX_CPU_LEVEL >= 4 - if ( (i->nnn == 4) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { + if ( (i->nnn() == 4) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { // Debug extensions on BX_INFO(("MOV_RqDq: access to DR4 causes #UD")); UndefinedOpcode(i); @@ -554,7 +554,7 @@ BX_CPU_C::MOV_RqDq(BxInstruction_t *i) // DR5 aliased to DR7 by default. With Debug Extensions on, // access to DR5 causes #UD #if BX_CPU_LEVEL >= 4 - if ( (i->nnn == 5) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { + if ( (i->nnn() == 5) && (BX_CPU_THIS_PTR cr4.get_DE()) ) { // Debug extensions on BX_INFO(("MOV_RqDq: access to DR5 causes #UD")); UndefinedOpcode(i); @@ -567,14 +567,14 @@ BX_CPU_C::MOV_RqDq(BxInstruction_t *i) BX_PANIC(("MOV_RqDq: control register index out of range")); val_64 = 0; } - BX_WRITE_64BIT_REG(i->rm, val_64); + BX_WRITE_64BIT_REG(i->rm(), val_64); } #endif // #if BX_SUPPORT_X86_64 void -BX_CPU_C::LMSW_Ew(BxInstruction_t *i) +BX_CPU_C::LMSW_Ew(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("LMSW_Ew(): not supported on 8086!")); @@ -594,8 +594,8 @@ BX_CPU_C::LMSW_Ew(BxInstruction_t *i) } } - if (i->mod == 0xc0) { - msw = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + msw = BX_READ_16BIT_REG(i->rm()); } else { read_virtual_word(i->seg, i->rm_addr, &msw); @@ -615,7 +615,7 @@ BX_CPU_C::LMSW_Ew(BxInstruction_t *i) } void -BX_CPU_C::SMSW_Ew(BxInstruction_t *i) +BX_CPU_C::SMSW_Ew(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("SMSW_Ew: not supported yet!")); @@ -640,12 +640,12 @@ BX_CPU_C::SMSW_Ew(BxInstruction_t *i) #endif - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { if (i->os_32) { - BX_WRITE_32BIT_REGZ(i->rm, msw); // zeros out high 16bits + BX_WRITE_32BIT_REGZ(i->rm(), msw); // zeros out high 16bits } else { - BX_WRITE_16BIT_REG(i->rm, msw); + BX_WRITE_16BIT_REG(i->rm(), msw); } } else { @@ -657,7 +657,7 @@ BX_CPU_C::SMSW_Ew(BxInstruction_t *i) void -BX_CPU_C::MOV_CdRd(BxInstruction_t *i) +BX_CPU_C::MOV_CdRd(bxInstruction_c *i) { // mov general register data to control register #if BX_CPU_LEVEL < 3 @@ -675,7 +675,7 @@ BX_CPU_C::MOV_CdRd(BxInstruction_t *i) * reg field specifies which special register */ - if (i->mod != 0xc0) { + if (i->mod() != 0xc0) { BX_PANIC(("MOV_CdRd(): rm field not a register!")); } @@ -688,9 +688,9 @@ BX_CPU_C::MOV_CdRd(BxInstruction_t *i) return; } - val_32 = BX_READ_32BIT_REG(i->rm); + val_32 = BX_READ_32BIT_REG(i->rm()); - switch (i->nnn) { + switch (i->nnn()) { case 0: // CR0 (MSW) // BX_INFO(("MOV_CdRd:CR0: R32 = %08x @CS:EIP %04x:%04x ", // (unsigned) val_32, @@ -738,7 +738,7 @@ BX_CPU_C::MOV_CdRd(BxInstruction_t *i) } void -BX_CPU_C::MOV_RdCd(BxInstruction_t *i) +BX_CPU_C::MOV_RdCd(bxInstruction_c *i) { // mov control register data to register #if BX_CPU_LEVEL < 3 @@ -755,7 +755,7 @@ BX_CPU_C::MOV_RdCd(BxInstruction_t *i) * reg field specifies which special register */ - if (i->mod != 0xc0) { + if (i->mod() != 0xc0) { BX_PANIC(("MOV_RdCd(): rm field not a register!")); } @@ -765,7 +765,7 @@ BX_CPU_C::MOV_RdCd(BxInstruction_t *i) return; } - switch (i->nnn) { + switch (i->nnn()) { case 0: // CR0 (MSW) val_32 = BX_CPU_THIS_PTR cr0.val32; #if 0 @@ -803,14 +803,14 @@ BX_CPU_C::MOV_RdCd(BxInstruction_t *i) BX_PANIC(("MOV_RdCd: control register index out of range")); val_32 = 0; } - BX_WRITE_32BIT_REGZ(i->rm, val_32); + BX_WRITE_32BIT_REGZ(i->rm(), val_32); #endif } #if BX_SUPPORT_X86_64 void -BX_CPU_C::MOV_CqRq(BxInstruction_t *i) +BX_CPU_C::MOV_CqRq(bxInstruction_c *i) { // mov general register data to control register #if BX_CPU_LEVEL < 3 @@ -828,7 +828,7 @@ BX_CPU_C::MOV_CqRq(BxInstruction_t *i) * reg field specifies which special register */ - if (i->mod != 0xc0) { + if (i->mod() != 0xc0) { BX_PANIC(("MOV_CqRq(): rm field not a register!")); } @@ -841,9 +841,9 @@ BX_CPU_C::MOV_CqRq(BxInstruction_t *i) return; } - val_64 = BX_READ_64BIT_REG(i->rm); + val_64 = BX_READ_64BIT_REG(i->rm()); - switch (i->nnn) { + switch (i->nnn()) { case 0: // CR0 (MSW) // BX_INFO(("MOV_CqRq:CR0: R64 = %08x @CS:EIP %04x:%04x ", // (unsigned) val_64, @@ -899,7 +899,7 @@ BX_CPU_C::MOV_CqRq(BxInstruction_t *i) #if BX_SUPPORT_X86_64 void -BX_CPU_C::MOV_RqCq(BxInstruction_t *i) +BX_CPU_C::MOV_RqCq(bxInstruction_c *i) { // mov control register data to register #if BX_CPU_LEVEL < 3 @@ -916,7 +916,7 @@ BX_CPU_C::MOV_RqCq(BxInstruction_t *i) * reg field specifies which special register */ - if (i->mod != 0xc0) { + if (i->mod() != 0xc0) { BX_PANIC(("MOV_RqC(): rm field not a register!")); } @@ -927,7 +927,7 @@ BX_CPU_C::MOV_RqCq(BxInstruction_t *i) return; } - switch (i->nnn) { + switch (i->nnn()) { case 0: // CR0 (MSW) val_64 = BX_CPU_THIS_PTR cr0.val32; #if 0 @@ -965,13 +965,13 @@ BX_CPU_C::MOV_RqCq(BxInstruction_t *i) BX_PANIC(("MOV_RqCq: control register index out of range")); val_64 = 0; } - BX_WRITE_64BIT_REG(i->rm, val_64); + BX_WRITE_64BIT_REG(i->rm(), val_64); #endif } #endif // #if BX_SUPPORT_X86_64 void -BX_CPU_C::MOV_TdRd(BxInstruction_t *i) +BX_CPU_C::MOV_TdRd(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOV_TdRd:")); @@ -985,7 +985,7 @@ BX_CPU_C::MOV_TdRd(BxInstruction_t *i) } void -BX_CPU_C::MOV_RdTd(BxInstruction_t *i) +BX_CPU_C::MOV_RdTd(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("MOV_RdTd:")); @@ -999,7 +999,7 @@ BX_CPU_C::MOV_RdTd(BxInstruction_t *i) } void -BX_CPU_C::LOADALL(BxInstruction_t *i) +BX_CPU_C::LOADALL(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("undocumented LOADALL instruction not supported on 8086")); @@ -1328,7 +1328,7 @@ BX_PANIC(("LOADALL: handle CR0.val32")); void -BX_CPU_C::CPUID(BxInstruction_t *i) +BX_CPU_C::CPUID(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 4 unsigned type, family, model, stepping, features; @@ -1604,7 +1604,7 @@ BX_CPU_C::SetCR4(Bit32u val_32) void -BX_CPU_C::RSM(BxInstruction_t *i) +BX_CPU_C::RSM(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 4 invalidate_prefetch_q(); @@ -1616,7 +1616,7 @@ BX_CPU_C::RSM(BxInstruction_t *i) } void -BX_CPU_C::RDTSC(BxInstruction_t *i) +BX_CPU_C::RDTSC(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 5 Boolean tsd = BX_CPU_THIS_PTR cr4.get_TSD(); @@ -1637,7 +1637,7 @@ BX_CPU_C::RDTSC(BxInstruction_t *i) } void -BX_CPU_C::RDMSR(BxInstruction_t *i) +BX_CPU_C::RDMSR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 5 invalidate_prefetch_q(); @@ -1757,7 +1757,7 @@ do_exception: } void -BX_CPU_C::WRMSR(BxInstruction_t *i) +BX_CPU_C::WRMSR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 5 invalidate_prefetch_q(); diff --git a/bochs/cpu/protect_ctrl.cc b/bochs/cpu/protect_ctrl.cc index 6f9e6cd68..f399d0f0a 100644 --- a/bochs/cpu/protect_ctrl.cc +++ b/bochs/cpu/protect_ctrl.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: protect_ctrl.cc,v 1.12 2002-09-13 21:08:54 kevinlawton Exp $ +// $Id: protect_ctrl.cc,v 1.13 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -38,7 +38,7 @@ void -BX_CPU_C::ARPL_EwGw(BxInstruction_t *i) +BX_CPU_C::ARPL_EwGw(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("ARPL_EwRw: not supported on 8086!")); @@ -49,32 +49,32 @@ BX_CPU_C::ARPL_EwGw(BxInstruction_t *i) if (protected_mode()) { /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16); } - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); if ( (op1_16 & 0x03) < (op2_16 & 0x03) ) { op1_16 = (op1_16 & 0xfffc) | (op2_16 & 0x03); /* now write back to destination */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { if (i->os_32) { // if 32bit opsize, then 0xff3f is or'd into // upper 16bits of register Bit32u op1_32; - op1_32 = BX_READ_32BIT_REG(i->rm); + op1_32 = BX_READ_32BIT_REG(i->rm()); op1_32 = (op1_32 & 0xffff0000) | op1_16; op1_32 |= 0xff3f0000; - BX_WRITE_32BIT_REGZ(i->rm, op1_32); + BX_WRITE_32BIT_REGZ(i->rm(), op1_32); } else { - BX_WRITE_16BIT_REG(i->rm, op1_16); + BX_WRITE_16BIT_REG(i->rm(), op1_16); } } else { @@ -95,7 +95,7 @@ BX_CPU_C::ARPL_EwGw(BxInstruction_t *i) } void -BX_CPU_C::LAR_GvEw(BxInstruction_t *i) +BX_CPU_C::LAR_GvEw(bxInstruction_c *i) { /* for 16 bit operand size mode */ Bit16u raw_selector; @@ -113,8 +113,8 @@ BX_CPU_C::LAR_GvEw(BxInstruction_t *i) } - if (i->mod == 0xc0) { - raw_selector = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + raw_selector = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -161,10 +161,10 @@ BX_CPU_C::LAR_GvEw(BxInstruction_t *i) set_ZF(1); if (i->os_32) { /* masked by 00FxFF00, where x is undefined */ - BX_WRITE_32BIT_REGZ(i->nnn, dword2 & 0x00ffff00); + BX_WRITE_32BIT_REGZ(i->nnn(), dword2 & 0x00ffff00); } else { - BX_WRITE_16BIT_REG(i->nnn, dword2 & 0xff00); + BX_WRITE_16BIT_REG(i->nnn(), dword2 & 0xff00); } return; } @@ -195,17 +195,17 @@ BX_CPU_C::LAR_GvEw(BxInstruction_t *i) set_ZF(1); if (i->os_32) { /* masked by 00FxFF00, where x is undefined ??? */ - BX_WRITE_32BIT_REGZ(i->nnn, dword2 & 0x00ffff00); + BX_WRITE_32BIT_REGZ(i->nnn(), dword2 & 0x00ffff00); } else { - BX_WRITE_16BIT_REG(i->nnn, dword2 & 0xff00); + BX_WRITE_16BIT_REG(i->nnn(), dword2 & 0xff00); } return; } } void -BX_CPU_C::LSL_GvEw(BxInstruction_t *i) +BX_CPU_C::LSL_GvEw(bxInstruction_c *i) { /* for 16 bit operand size mode */ Bit16u raw_selector; @@ -224,8 +224,8 @@ BX_CPU_C::LSL_GvEw(BxInstruction_t *i) return; } - if (i->mod == 0xc0) { - raw_selector = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + raw_selector = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -296,14 +296,14 @@ lsl_ok: set_ZF(1); if (i->os_32) - BX_WRITE_32BIT_REGZ(i->nnn, limit32) + BX_WRITE_32BIT_REGZ(i->nnn(), limit32) else // chop off upper 16 bits - BX_WRITE_16BIT_REG(i->nnn, (Bit16u) limit32) + BX_WRITE_16BIT_REG(i->nnn(), (Bit16u) limit32) } void -BX_CPU_C::SLDT_Ew(BxInstruction_t *i) +BX_CPU_C::SLDT_Ew(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("SLDT_Ew: not supported on 8086!")); @@ -319,8 +319,8 @@ BX_CPU_C::SLDT_Ew(BxInstruction_t *i) Bit16u val16; val16 = BX_CPU_THIS_PTR ldtr.selector.value; - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, val16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), val16); } else { write_virtual_word(i->seg, i->rm_addr, &val16); @@ -330,7 +330,7 @@ BX_CPU_C::SLDT_Ew(BxInstruction_t *i) } void -BX_CPU_C::STR_Ew(BxInstruction_t *i) +BX_CPU_C::STR_Ew(bxInstruction_c *i) { if (v8086_mode()) BX_PANIC(("protect_ctrl: v8086 mode unsupported")); @@ -343,8 +343,8 @@ BX_CPU_C::STR_Ew(BxInstruction_t *i) Bit16u val16; val16 = BX_CPU_THIS_PTR tr.selector.value; - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, val16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), val16); } else { write_virtual_word(i->seg, i->rm_addr, &val16); @@ -353,7 +353,7 @@ BX_CPU_C::STR_Ew(BxInstruction_t *i) } void -BX_CPU_C::LLDT_Ew(BxInstruction_t *i) +BX_CPU_C::LLDT_Ew(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("LLDT_Ew: not supported on 8086!")); @@ -381,8 +381,8 @@ BX_CPU_C::LLDT_Ew(BxInstruction_t *i) return; } - if (i->mod == 0xc0) { - raw_selector = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + raw_selector = BX_READ_16BIT_REG(i->rm()); } else { read_virtual_word(i->seg, i->rm_addr, &raw_selector); @@ -445,7 +445,7 @@ BX_CPU_C::LLDT_Ew(BxInstruction_t *i) } void -BX_CPU_C::LTR_Ew(BxInstruction_t *i) +BX_CPU_C::LTR_Ew(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("LTR_Ew: not supported on 8086!")); @@ -469,8 +469,8 @@ BX_CPU_C::LTR_Ew(BxInstruction_t *i) return; } - if (i->mod == 0xc0) { - raw_selector = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + raw_selector = BX_READ_16BIT_REG(i->rm()); } else { read_virtual_word(i->seg, i->rm_addr, &raw_selector); @@ -544,7 +544,7 @@ BX_CPU_C::LTR_Ew(BxInstruction_t *i) } void -BX_CPU_C::VERR_Ew(BxInstruction_t *i) +BX_CPU_C::VERR_Ew(bxInstruction_c *i) { /* for 16 bit operand size mode */ Bit16u raw_selector; @@ -561,8 +561,8 @@ BX_CPU_C::VERR_Ew(BxInstruction_t *i) return; } - if (i->mod == 0xc0) { - raw_selector = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + raw_selector = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -639,7 +639,7 @@ BX_CPU_C::VERR_Ew(BxInstruction_t *i) } void -BX_CPU_C::VERW_Ew(BxInstruction_t *i) +BX_CPU_C::VERW_Ew(bxInstruction_c *i) { /* for 16 bit operand size mode */ Bit16u raw_selector; @@ -656,8 +656,8 @@ BX_CPU_C::VERW_Ew(BxInstruction_t *i) return; } - if (i->mod == 0xc0) { - raw_selector = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + raw_selector = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -716,7 +716,7 @@ BX_CPU_C::VERW_Ew(BxInstruction_t *i) } void -BX_CPU_C::SGDT_Ms(BxInstruction_t *i) +BX_CPU_C::SGDT_Ms(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("SGDT_Ms: not supported on 8086!")); @@ -728,7 +728,7 @@ BX_CPU_C::SGDT_Ms(BxInstruction_t *i) /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { /* undefined opcode exception */ BX_PANIC(("SGDT_Ms: use of register is undefined opcode.")); UndefinedOpcode(i); @@ -764,7 +764,7 @@ BX_CPU_C::SGDT_Ms(BxInstruction_t *i) } void -BX_CPU_C::SIDT_Ms(BxInstruction_t *i) +BX_CPU_C::SIDT_Ms(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("SIDT_Ms: not supported on 8086!")); @@ -775,7 +775,7 @@ BX_CPU_C::SIDT_Ms(BxInstruction_t *i) if (v8086_mode()) BX_PANIC(("protect_ctrl: v8086 mode unsupported")); /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { /* undefined opcode exception */ BX_PANIC(("SIDT: use of register is undefined opcode.")); UndefinedOpcode(i); @@ -813,7 +813,7 @@ BX_CPU_C::SIDT_Ms(BxInstruction_t *i) } void -BX_CPU_C::LGDT_Ms(BxInstruction_t *i) +BX_CPU_C::LGDT_Ms(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("LGDT_Ms: not supported on 8086!")); @@ -830,7 +830,7 @@ BX_CPU_C::LGDT_Ms(BxInstruction_t *i) } /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_PANIC(("LGDT generating exception 6")); UndefinedOpcode(i); return; @@ -881,7 +881,7 @@ BX_CPU_C::LGDT_Ms(BxInstruction_t *i) } void -BX_CPU_C::LIDT_Ms(BxInstruction_t *i) +BX_CPU_C::LIDT_Ms(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("LIDT_Ms: not supported on 8086!")); @@ -903,7 +903,7 @@ BX_CPU_C::LIDT_Ms(BxInstruction_t *i) } /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { /* undefined opcode exception */ BX_PANIC(("LIDT generating exception 6")); UndefinedOpcode(i); diff --git a/bochs/cpu/resolve16.cc b/bochs/cpu/resolve16.cc index 272b1c0ba..325752a90 100644 --- a/bochs/cpu/resolve16.cc +++ b/bochs/cpu/resolve16.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: resolve16.cc,v 1.5 2001-10-03 13:10:37 bdenney Exp $ +// $Id: resolve16.cc,v 1.6 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -36,78 +36,78 @@ void -BX_CPU_C::Resolve16Mod0Rm0(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod0Rm0(bxInstruction_c *i) { i->rm_addr = (Bit16u) (BX + SI); } void -BX_CPU_C::Resolve16Mod0Rm1(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod0Rm1(bxInstruction_c *i) { i->rm_addr = (Bit16u) (BX + DI); } void -BX_CPU_C::Resolve16Mod0Rm2(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod0Rm2(bxInstruction_c *i) { i->rm_addr = (Bit16u) (BP + SI); } void -BX_CPU_C::Resolve16Mod0Rm3(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod0Rm3(bxInstruction_c *i) { i->rm_addr = (Bit16u) (BP + DI); } void -BX_CPU_C::Resolve16Mod0Rm4(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod0Rm4(bxInstruction_c *i) { i->rm_addr = (Bit16u) SI; } void -BX_CPU_C::Resolve16Mod0Rm5(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod0Rm5(bxInstruction_c *i) { i->rm_addr = (Bit16u) DI; } void -BX_CPU_C::Resolve16Mod0Rm7(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod0Rm7(bxInstruction_c *i) { i->rm_addr = (Bit16u) BX; } void -BX_CPU_C::Resolve16Mod1or2Rm0(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod1or2Rm0(bxInstruction_c *i) { - i->rm_addr = (Bit16u) (BX + SI + (Bit16s) i->displ16u); + i->rm_addr = (Bit16u) (BX + SI + (Bit16s) i->displ16u()); } void -BX_CPU_C::Resolve16Mod1or2Rm1(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod1or2Rm1(bxInstruction_c *i) { - i->rm_addr = (Bit16u) (BX + DI + (Bit16s) i->displ16u); + i->rm_addr = (Bit16u) (BX + DI + (Bit16s) i->displ16u()); } void -BX_CPU_C::Resolve16Mod1or2Rm2(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod1or2Rm2(bxInstruction_c *i) { - i->rm_addr = (Bit16u) (BP + SI + (Bit16s) i->displ16u); + i->rm_addr = (Bit16u) (BP + SI + (Bit16s) i->displ16u()); } void -BX_CPU_C::Resolve16Mod1or2Rm3(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod1or2Rm3(bxInstruction_c *i) { - i->rm_addr = (Bit16u) (BP + DI + (Bit16s) i->displ16u); + i->rm_addr = (Bit16u) (BP + DI + (Bit16s) i->displ16u()); } void -BX_CPU_C::Resolve16Mod1or2Rm4(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod1or2Rm4(bxInstruction_c *i) { - i->rm_addr = (Bit16u) (SI + (Bit16s) i->displ16u); + i->rm_addr = (Bit16u) (SI + (Bit16s) i->displ16u()); } void -BX_CPU_C::Resolve16Mod1or2Rm5(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod1or2Rm5(bxInstruction_c *i) { - i->rm_addr = (Bit16u) (DI + (Bit16s) i->displ16u); + i->rm_addr = (Bit16u) (DI + (Bit16s) i->displ16u()); } void -BX_CPU_C::Resolve16Mod1or2Rm6(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod1or2Rm6(bxInstruction_c *i) { - i->rm_addr = (Bit16u) (BP + (Bit16s) i->displ16u); + i->rm_addr = (Bit16u) (BP + (Bit16s) i->displ16u()); } void -BX_CPU_C::Resolve16Mod1or2Rm7(BxInstruction_t *i) +BX_CPU_C::Resolve16Mod1or2Rm7(bxInstruction_c *i) { - i->rm_addr = (Bit16u) (BX + (Bit16s) i->displ16u); + i->rm_addr = (Bit16u) (BX + (Bit16s) i->displ16u()); } diff --git a/bochs/cpu/resolve32.cc b/bochs/cpu/resolve32.cc index 306236df8..9a939ef89 100644 --- a/bochs/cpu/resolve32.cc +++ b/bochs/cpu/resolve32.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: resolve32.cc,v 1.5 2001-10-03 13:10:37 bdenney Exp $ +// $Id: resolve32.cc,v 1.6 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -36,158 +36,158 @@ void -BX_CPU_C::Resolve32Mod0Rm0(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Rm0(bxInstruction_c *i) { i->rm_addr = EAX; } void -BX_CPU_C::Resolve32Mod0Rm1(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Rm1(bxInstruction_c *i) { i->rm_addr = ECX; } void -BX_CPU_C::Resolve32Mod0Rm2(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Rm2(bxInstruction_c *i) { i->rm_addr = EDX; } void -BX_CPU_C::Resolve32Mod0Rm3(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Rm3(bxInstruction_c *i) { i->rm_addr = EBX; } void -BX_CPU_C::Resolve32Mod0Rm6(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Rm6(bxInstruction_c *i) { i->rm_addr = ESI; } void -BX_CPU_C::Resolve32Mod0Rm7(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Rm7(bxInstruction_c *i) { i->rm_addr = EDI; } void -BX_CPU_C::Resolve32Mod1or2Rm0(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Rm0(bxInstruction_c *i) { - i->rm_addr = EAX + i->displ32u; + i->rm_addr = EAX + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Rm1(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Rm1(bxInstruction_c *i) { - i->rm_addr = ECX + i->displ32u; + i->rm_addr = ECX + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Rm2(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Rm2(bxInstruction_c *i) { - i->rm_addr = EDX + i->displ32u; + i->rm_addr = EDX + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Rm3(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Rm3(bxInstruction_c *i) { - i->rm_addr = EBX + i->displ32u; + i->rm_addr = EBX + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Rm5(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Rm5(bxInstruction_c *i) { - i->rm_addr = EBP + i->displ32u; + i->rm_addr = EBP + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Rm6(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Rm6(bxInstruction_c *i) { - i->rm_addr = ESI + i->displ32u; + i->rm_addr = ESI + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Rm7(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Rm7(bxInstruction_c *i) { - i->rm_addr = EDI + i->displ32u; + i->rm_addr = EDI + i->displ32u(); } void -BX_CPU_C::Resolve32Mod0Base0(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Base0(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; i->rm_addr = EAX + scaled_index; } void -BX_CPU_C::Resolve32Mod0Base1(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Base1(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; i->rm_addr = ECX + scaled_index; } void -BX_CPU_C::Resolve32Mod0Base2(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Base2(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; i->rm_addr = EDX + scaled_index; } void -BX_CPU_C::Resolve32Mod0Base3(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Base3(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; i->rm_addr = EBX + scaled_index; } void -BX_CPU_C::Resolve32Mod0Base4(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Base4(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; i->rm_addr = ESP + scaled_index; } void -BX_CPU_C::Resolve32Mod0Base5(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Base5(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; - i->rm_addr = i->displ32u + scaled_index; + i->rm_addr = i->displ32u() + scaled_index; } void -BX_CPU_C::Resolve32Mod0Base6(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Base6(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; i->rm_addr = ESI + scaled_index; } void -BX_CPU_C::Resolve32Mod0Base7(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod0Base7(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; i->rm_addr = EDI + scaled_index; @@ -197,90 +197,90 @@ BX_CPU_C::Resolve32Mod0Base7(BxInstruction_t *i) void -BX_CPU_C::Resolve32Mod1or2Base0(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Base0(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; - i->rm_addr = EAX + scaled_index + i->displ32u; + i->rm_addr = EAX + scaled_index + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Base1(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Base1(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; - i->rm_addr = ECX + scaled_index + i->displ32u; + i->rm_addr = ECX + scaled_index + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Base2(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Base2(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; - i->rm_addr = EDX + scaled_index + i->displ32u; + i->rm_addr = EDX + scaled_index + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Base3(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Base3(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; - i->rm_addr = EBX + scaled_index + i->displ32u; + i->rm_addr = EBX + scaled_index + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Base4(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Base4(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; - i->rm_addr = ESP + scaled_index + i->displ32u; + i->rm_addr = ESP + scaled_index + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Base5(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Base5(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; - i->rm_addr = EBP + scaled_index + i->displ32u; + i->rm_addr = EBP + scaled_index + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Base6(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Base6(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; - i->rm_addr = ESI + scaled_index + i->displ32u; + i->rm_addr = ESI + scaled_index + i->displ32u(); } void -BX_CPU_C::Resolve32Mod1or2Base7(BxInstruction_t *i) +BX_CPU_C::Resolve32Mod1or2Base7(bxInstruction_c *i) { Bit32u scaled_index; - if (i->index != 4) - scaled_index = BX_READ_32BIT_REG(i->index) << i->scale; + if (i->sibIndex() != 4) + scaled_index = BX_READ_32BIT_REG(i->sibIndex()) << i->sibScale(); else scaled_index = 0; - i->rm_addr = EDI + scaled_index + i->displ32u; + i->rm_addr = EDI + scaled_index + i->displ32u(); } diff --git a/bochs/cpu/resolve64.cc b/bochs/cpu/resolve64.cc index 36ab48f76..8e97ac331 100644 --- a/bochs/cpu/resolve64.cc +++ b/bochs/cpu/resolve64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: resolve64.cc,v 1.1 2002-09-13 15:53:22 kevinlawton Exp $ +// $Id: resolve64.cc,v 1.2 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -36,289 +36,289 @@ void -BX_CPU_C::Resolve64Mod0Rm0(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm0(bxInstruction_c *i) { i->rm_addr = RAX; } void -BX_CPU_C::Resolve64Mod0Rm1(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm1(bxInstruction_c *i) { i->rm_addr = RCX; } void -BX_CPU_C::Resolve64Mod0Rm2(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm2(bxInstruction_c *i) { i->rm_addr = RDX; } void -BX_CPU_C::Resolve64Mod0Rm3(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm3(bxInstruction_c *i) { i->rm_addr = RBX; } void -BX_CPU_C::Resolve64Mod0Rm5(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm5(bxInstruction_c *i) { // eip hasn't been bumped yet when this is called. must choose the saved value. - i->rm_addr = BX_CPU_THIS_PTR prev_eip + i->ilen + (Bit32s)i->displ32u; + i->rm_addr = BX_CPU_THIS_PTR prev_eip + i->ilen + (Bit32s)i->displ32u(); } void -BX_CPU_C::Resolve64Mod0Rm6(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm6(bxInstruction_c *i) { i->rm_addr = RSI; } void -BX_CPU_C::Resolve64Mod0Rm7(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm7(bxInstruction_c *i) { i->rm_addr = RDI; } void -BX_CPU_C::Resolve64Mod0Rm8(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm8(bxInstruction_c *i) { i->rm_addr = R8; } void -BX_CPU_C::Resolve64Mod0Rm9(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm9(bxInstruction_c *i) { i->rm_addr = R9; } void -BX_CPU_C::Resolve64Mod0Rm10(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm10(bxInstruction_c *i) { i->rm_addr = R10; } void -BX_CPU_C::Resolve64Mod0Rm11(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm11(bxInstruction_c *i) { i->rm_addr = R11; } void -BX_CPU_C::Resolve64Mod0Rm12(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm12(bxInstruction_c *i) { i->rm_addr = R12; } void -BX_CPU_C::Resolve64Mod0Rm13(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm13(bxInstruction_c *i) { i->rm_addr = R13; } void -BX_CPU_C::Resolve64Mod0Rm14(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm14(bxInstruction_c *i) { i->rm_addr = R14; } void -BX_CPU_C::Resolve64Mod0Rm15(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Rm15(bxInstruction_c *i) { i->rm_addr = R15; } void -BX_CPU_C::Resolve64Mod1or2Rm0(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm0(bxInstruction_c *i) { - i->rm_addr = RAX + (Bit32s) i->displ32u; + i->rm_addr = RAX + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm1(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm1(bxInstruction_c *i) { - i->rm_addr = RCX + (Bit32s) i->displ32u; + i->rm_addr = RCX + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm2(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm2(bxInstruction_c *i) { - i->rm_addr = RDX + (Bit32s) i->displ32u; + i->rm_addr = RDX + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm3(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm3(bxInstruction_c *i) { - i->rm_addr = RBX + (Bit32s) i->displ32u; + i->rm_addr = RBX + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm5(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm5(bxInstruction_c *i) { - i->rm_addr = RBP + (Bit32s) i->displ32u; + i->rm_addr = RBP + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm6(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm6(bxInstruction_c *i) { - i->rm_addr = RSI + (Bit32s) i->displ32u; + i->rm_addr = RSI + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm7(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm7(bxInstruction_c *i) { - i->rm_addr = RDI + (Bit32s) i->displ32u; + i->rm_addr = RDI + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm8(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm8(bxInstruction_c *i) { - i->rm_addr = R8 + (Bit32s) i->displ32u; + i->rm_addr = R8 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm9(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm9(bxInstruction_c *i) { - i->rm_addr = R9 + (Bit32s) i->displ32u; + i->rm_addr = R9 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm10(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm10(bxInstruction_c *i) { - i->rm_addr = R10 + (Bit32s) i->displ32u; + i->rm_addr = R10 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm11(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm11(bxInstruction_c *i) { - i->rm_addr = R11 + (Bit32s) i->displ32u; + i->rm_addr = R11 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm12(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm12(bxInstruction_c *i) { - i->rm_addr = R12 + (Bit32s) i->displ32u; + i->rm_addr = R12 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm13(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm13(bxInstruction_c *i) { - i->rm_addr = R13 + (Bit32s) i->displ32u; + i->rm_addr = R13 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm14(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm14(bxInstruction_c *i) { - i->rm_addr = R14 + (Bit32s) i->displ32u; + i->rm_addr = R14 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Rm15(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Rm15(bxInstruction_c *i) { - i->rm_addr = R15 + (Bit32s) i->displ32u; + i->rm_addr = R15 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod0Base0(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base0(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RAX + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = RAX + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = RAX; } void -BX_CPU_C::Resolve64Mod0Base1(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base1(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RCX + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = RCX + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = RCX; } void -BX_CPU_C::Resolve64Mod0Base2(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base2(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RDX + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = RDX + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = RDX; } void -BX_CPU_C::Resolve64Mod0Base3(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base3(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RBX + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = RBX + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = RBX; } void -BX_CPU_C::Resolve64Mod0Base4(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base4(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RSP + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = RSP + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = RSP; } void -BX_CPU_C::Resolve64Mod0Base5(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base5(bxInstruction_c *i) { - if (i->index != 4) { - i->rm_addr = (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) { + i->rm_addr = (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); } else - i->rm_addr = (Bit32s) i->displ32u; + i->rm_addr = (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod0Base6(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base6(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RSI + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = RSI + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = RSI; } void -BX_CPU_C::Resolve64Mod0Base7(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base7(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RDI + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = RDI + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = RDI; } void -BX_CPU_C::Resolve64Mod0Base8(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base8(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R8 + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = R8 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = R8; } void -BX_CPU_C::Resolve64Mod0Base9(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base9(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R9 + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = R9 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = R9; } void -BX_CPU_C::Resolve64Mod0Base10(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base10(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R10 + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = R10 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = R10; } void -BX_CPU_C::Resolve64Mod0Base11(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base11(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R11 + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = R11 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = R11; } void -BX_CPU_C::Resolve64Mod0Base12(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base12(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R12 + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = R12 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = R12; } void -BX_CPU_C::Resolve64Mod0Base13(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base13(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R13 + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = R13 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = R13; } void -BX_CPU_C::Resolve64Mod0Base14(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base14(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R14 + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = R14 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = R14; } void -BX_CPU_C::Resolve64Mod0Base15(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod0Base15(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R15 + (BX_READ_64BIT_REG(i->index) << i->scale); + if (i->sibIndex() != 4) + i->rm_addr = R15 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()); else i->rm_addr = R15; } @@ -327,131 +327,131 @@ BX_CPU_C::Resolve64Mod0Base15(BxInstruction_t *i) void -BX_CPU_C::Resolve64Mod1or2Base0(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base0(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RAX + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = RAX + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = RAX + (Bit32s) i->displ32u; + i->rm_addr = RAX + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base1(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base1(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RCX + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = RCX + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = RCX + (Bit32s) i->displ32u; + i->rm_addr = RCX + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base2(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base2(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RDX + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = RDX + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = RDX + (Bit32s) i->displ32u; + i->rm_addr = RDX + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base3(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base3(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RBX + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = RBX + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = RBX + (Bit32s) i->displ32u; + i->rm_addr = RBX + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base4(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base4(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RSP + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = RSP + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = RSP + (Bit32s) i->displ32u; + i->rm_addr = RSP + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base5(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base5(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RBP + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = RBP + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = RBP + (Bit32s) i->displ32u; + i->rm_addr = RBP + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base6(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base6(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RSI + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = RSI + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = RSI + (Bit32s) i->displ32u; + i->rm_addr = RSI + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base7(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base7(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = RDI + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = RDI + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = RDI + (Bit32s) i->displ32u; + i->rm_addr = RDI + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base8(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base8(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R8 + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = R8 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = R8 + (Bit32s) i->displ32u; + i->rm_addr = R8 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base9(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base9(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R9 + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = R9 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = R9 + (Bit32s) i->displ32u; + i->rm_addr = R9 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base10(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base10(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R10 + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = R10 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = R10 + (Bit32s) i->displ32u; + i->rm_addr = R10 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base11(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base11(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R11 + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = R11 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = R11 + (Bit32s) i->displ32u; + i->rm_addr = R11 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base12(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base12(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R12 + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = R12 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = R12 + (Bit32s) i->displ32u; + i->rm_addr = R12 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base13(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base13(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R13 + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = R13 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = R13 + (Bit32s) i->displ32u; + i->rm_addr = R13 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base14(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base14(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R14 + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = R14 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = R14 + (Bit32s) i->displ32u; + i->rm_addr = R14 + (Bit32s) i->displ32u(); } void -BX_CPU_C::Resolve64Mod1or2Base15(BxInstruction_t *i) +BX_CPU_C::Resolve64Mod1or2Base15(bxInstruction_c *i) { - if (i->index != 4) - i->rm_addr = R15 + (BX_READ_64BIT_REG(i->index) << i->scale) + (Bit32s) i->displ32u; + if (i->sibIndex() != 4) + i->rm_addr = R15 + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale()) + (Bit32s) i->displ32u(); else - i->rm_addr = R15 + (Bit32s) i->displ32u; + i->rm_addr = R15 + (Bit32s) i->displ32u(); } diff --git a/bochs/cpu/segment_ctrl.cc b/bochs/cpu/segment_ctrl.cc index 7152a281b..f04694774 100644 --- a/bochs/cpu/segment_ctrl.cc +++ b/bochs/cpu/segment_ctrl.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: segment_ctrl.cc,v 1.7 2002-09-14 03:31:50 kevinlawton Exp $ +// $Id: segment_ctrl.cc,v 1.8 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -42,9 +42,9 @@ void -BX_CPU_C::LES_GvMp(BxInstruction_t *i) +BX_CPU_C::LES_GvMp(bxInstruction_c *i) { - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { // (BW) NT seems to use this when booting. BX_INFO(("invalid use of LES, must use memory reference!")); UndefinedOpcode(i); @@ -60,7 +60,7 @@ BX_CPU_C::LES_GvMp(BxInstruction_t *i) load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es); - BX_WRITE_32BIT_REGZ(i->nnn, reg_32); + BX_WRITE_32BIT_REGZ(i->nnn(), reg_32); } else #endif /* BX_CPU_LEVEL > 2 */ @@ -72,14 +72,14 @@ BX_CPU_C::LES_GvMp(BxInstruction_t *i) load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es); - BX_WRITE_16BIT_REG(i->nnn, reg_16); + BX_WRITE_16BIT_REG(i->nnn(), reg_16); } } void -BX_CPU_C::LDS_GvMp(BxInstruction_t *i) +BX_CPU_C::LDS_GvMp(bxInstruction_c *i) { - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_PANIC(("invalid use of LDS, must use memory reference!")); UndefinedOpcode(i); } @@ -94,7 +94,7 @@ BX_CPU_C::LDS_GvMp(BxInstruction_t *i) load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds); - BX_WRITE_32BIT_REGZ(i->nnn, reg_32); + BX_WRITE_32BIT_REGZ(i->nnn(), reg_32); } else #endif /* BX_CPU_LEVEL > 2 */ @@ -106,18 +106,18 @@ BX_CPU_C::LDS_GvMp(BxInstruction_t *i) load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds); - BX_WRITE_16BIT_REG(i->nnn, reg_16); + BX_WRITE_16BIT_REG(i->nnn(), reg_16); } } void -BX_CPU_C::LFS_GvMp(BxInstruction_t *i) +BX_CPU_C::LFS_GvMp(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("lfs_gvmp: not supported on 8086")); #else /* 386+ */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_PANIC(("invalid use of LFS, must use memory reference!")); UndefinedOpcode(i); } @@ -131,7 +131,7 @@ BX_CPU_C::LFS_GvMp(BxInstruction_t *i) load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs); - BX_WRITE_32BIT_REGZ(i->nnn, reg_32); + BX_WRITE_32BIT_REGZ(i->nnn(), reg_32); } else { /* 16 bit operand size */ Bit16u reg_16; @@ -142,19 +142,19 @@ BX_CPU_C::LFS_GvMp(BxInstruction_t *i) load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs); - BX_WRITE_16BIT_REG(i->nnn, reg_16); + BX_WRITE_16BIT_REG(i->nnn(), reg_16); } #endif } void -BX_CPU_C::LGS_GvMp(BxInstruction_t *i) +BX_CPU_C::LGS_GvMp(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("lgs_gvmp: not supported on 8086")); #else /* 386+ */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_PANIC(("invalid use of LGS, must use memory reference!")); UndefinedOpcode(i); } @@ -168,7 +168,7 @@ BX_CPU_C::LGS_GvMp(BxInstruction_t *i) load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs); - BX_WRITE_32BIT_REGZ(i->nnn, reg_32); + BX_WRITE_32BIT_REGZ(i->nnn(), reg_32); } else { /* 16 bit operand size */ Bit16u reg_16; @@ -179,19 +179,19 @@ BX_CPU_C::LGS_GvMp(BxInstruction_t *i) load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs); - BX_WRITE_16BIT_REG(i->nnn, reg_16); + BX_WRITE_16BIT_REG(i->nnn(), reg_16); } #endif } void -BX_CPU_C::LSS_GvMp(BxInstruction_t *i) +BX_CPU_C::LSS_GvMp(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("lss_gvmp: not supported on 8086")); #else /* 386+ */ - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { BX_PANIC(("invalid use of LSS, must use memory reference!")); UndefinedOpcode(i); } @@ -205,7 +205,7 @@ BX_CPU_C::LSS_GvMp(BxInstruction_t *i) load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss_raw); - BX_WRITE_32BIT_REGZ(i->nnn, reg_32); + BX_WRITE_32BIT_REGZ(i->nnn(), reg_32); } else { /* 16 bit operand size */ Bit16u reg_16; @@ -216,7 +216,7 @@ BX_CPU_C::LSS_GvMp(BxInstruction_t *i) load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss_raw); - BX_WRITE_16BIT_REG(i->nnn, reg_16); + BX_WRITE_16BIT_REG(i->nnn(), reg_16); } #endif } diff --git a/bochs/cpu/shift16.cc b/bochs/cpu/shift16.cc index 0b508d9e0..2de56c416 100644 --- a/bochs/cpu/shift16.cc +++ b/bochs/cpu/shift16.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: shift16.cc,v 1.7 2002-09-06 21:54:58 kevinlawton Exp $ +// $Id: shift16.cc,v 1.8 2002-09-17 22:50:52 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -36,7 +36,7 @@ void -BX_CPU_C::SHLD_EwGw(BxInstruction_t *i) +BX_CPU_C::SHLD_EwGw(bxInstruction_c *i) { Bit16u op1_16, op2_16, result_16; Bit32u temp_32, result_32; @@ -44,7 +44,7 @@ BX_CPU_C::SHLD_EwGw(BxInstruction_t *i) /* op1:op2 << count. result stored in op1 */ if (i->b1 == 0x1a4) - count = i->Ib; + count = i->Ib(); else // 0x1a5 count = CL; @@ -55,14 +55,14 @@ BX_CPU_C::SHLD_EwGw(BxInstruction_t *i) // count is 1..31 /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16); } - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); temp_32 = (op1_16 << 16) | (op2_16); // double formed by op1:op2 result_32 = temp_32 << count; @@ -74,8 +74,8 @@ BX_CPU_C::SHLD_EwGw(BxInstruction_t *i) result_16 = result_32 >> 16; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -94,7 +94,7 @@ BX_CPU_C::SHLD_EwGw(BxInstruction_t *i) void -BX_CPU_C::SHRD_EwGw(BxInstruction_t *i) +BX_CPU_C::SHRD_EwGw(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("shrd_evgvib: not supported on < 386")); @@ -104,7 +104,7 @@ BX_CPU_C::SHRD_EwGw(BxInstruction_t *i) unsigned count; if (i->b1 == 0x1ac) - count = i->Ib; + count = i->Ib(); else // 0x1ad count = CL; count &= 0x1F; /* use only 5 LSB's */ @@ -114,14 +114,14 @@ BX_CPU_C::SHRD_EwGw(BxInstruction_t *i) // count is 1..31 /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16); } - op2_16 = BX_READ_16BIT_REG(i->nnn); + op2_16 = BX_READ_16BIT_REG(i->nnn()); temp_32 = (op2_16 << 16) | op1_16; // double formed by op2:op1 result_32 = temp_32 >> count; @@ -133,8 +133,8 @@ BX_CPU_C::SHRD_EwGw(BxInstruction_t *i) result_16 = result_32; /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -157,14 +157,14 @@ BX_CPU_C::SHRD_EwGw(BxInstruction_t *i) void -BX_CPU_C::ROL_Ew(BxInstruction_t *i) +BX_CPU_C::ROL_Ew(bxInstruction_c *i) { Bit16u op1_16, result_16; unsigned count; if ( i->b1 == 0xc1 ) - count = i->Ib; + count = i->Ib(); else if ( i->b1 == 0xd1 ) count = 1; else // 0xd3 @@ -173,8 +173,8 @@ BX_CPU_C::ROL_Ew(BxInstruction_t *i) count &= 0x0f; // only use bottom 4 bits /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -185,8 +185,8 @@ BX_CPU_C::ROL_Ew(BxInstruction_t *i) result_16 = (op1_16 << count) | (op1_16 >> (16 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -206,13 +206,13 @@ BX_CPU_C::ROL_Ew(BxInstruction_t *i) void -BX_CPU_C::ROR_Ew(BxInstruction_t *i) +BX_CPU_C::ROR_Ew(bxInstruction_c *i) { Bit16u op1_16, result_16, result_b15; unsigned count; if ( i->b1 == 0xc1 ) - count = i->Ib; + count = i->Ib(); else if ( i->b1 == 0xd1 ) count = 1; else // 0xd3 @@ -221,8 +221,8 @@ BX_CPU_C::ROR_Ew(BxInstruction_t *i) count &= 0x0f; // use only 4 LSB's /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -233,8 +233,8 @@ BX_CPU_C::ROR_Ew(BxInstruction_t *i) result_16 = (op1_16 >> count) | (op1_16 << (16 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -254,13 +254,13 @@ BX_CPU_C::ROR_Ew(BxInstruction_t *i) void -BX_CPU_C::RCL_Ew(BxInstruction_t *i) +BX_CPU_C::RCL_Ew(bxInstruction_c *i) { Bit16u op1_16, result_16; unsigned count; if ( i->b1 == 0xc1 ) - count = i->Ib; + count = i->Ib(); else if ( i->b1 == 0xd1 ) count = 1; else // 0xd3 @@ -269,8 +269,8 @@ BX_CPU_C::RCL_Ew(BxInstruction_t *i) count &= 0x1F; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -295,8 +295,8 @@ BX_CPU_C::RCL_Ew(BxInstruction_t *i) } /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -314,13 +314,13 @@ BX_CPU_C::RCL_Ew(BxInstruction_t *i) void -BX_CPU_C::RCR_Ew(BxInstruction_t *i) +BX_CPU_C::RCR_Ew(bxInstruction_c *i) { Bit16u op1_16, result_16; unsigned count; if ( i->b1 == 0xc1 ) - count = i->Ib; + count = i->Ib(); else if ( i->b1 == 0xd1 ) count = 1; else // 0xd3 @@ -329,8 +329,8 @@ BX_CPU_C::RCR_Ew(BxInstruction_t *i) count = count & 0x1F; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -344,8 +344,8 @@ BX_CPU_C::RCR_Ew(BxInstruction_t *i) (op1_16 << (17 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -365,13 +365,13 @@ BX_CPU_C::RCR_Ew(BxInstruction_t *i) void -BX_CPU_C::SHL_Ew(BxInstruction_t *i) +BX_CPU_C::SHL_Ew(bxInstruction_c *i) { Bit16u op1_16, result_16; unsigned count; if ( i->b1 == 0xc1 ) - count = i->Ib; + count = i->Ib(); else if ( i->b1 == 0xd1 ) count = 1; else // 0xd3 @@ -380,8 +380,8 @@ BX_CPU_C::SHL_Ew(BxInstruction_t *i) count &= 0x1F; /* use only 5 LSB's */ /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -393,8 +393,8 @@ BX_CPU_C::SHL_Ew(BxInstruction_t *i) result_16 = (op1_16 << count); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -407,13 +407,13 @@ BX_CPU_C::SHL_Ew(BxInstruction_t *i) void -BX_CPU_C::SHR_Ew(BxInstruction_t *i) +BX_CPU_C::SHR_Ew(bxInstruction_c *i) { Bit16u op1_16, result_16; unsigned count; if ( i->b1 == 0xc1 ) - count = i->Ib; + count = i->Ib(); else if ( i->b1 == 0xd1 ) count = 1; else // 0xd3 @@ -422,8 +422,8 @@ BX_CPU_C::SHR_Ew(BxInstruction_t *i) count &= 0x1F; /* use only 5 LSB's */ /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -436,8 +436,8 @@ BX_CPU_C::SHR_Ew(BxInstruction_t *i) /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); @@ -449,13 +449,13 @@ BX_CPU_C::SHR_Ew(BxInstruction_t *i) void -BX_CPU_C::SAR_Ew(BxInstruction_t *i) +BX_CPU_C::SAR_Ew(bxInstruction_c *i) { Bit16u op1_16, result_16; unsigned count; if ( i->b1 == 0xc1 ) - count = i->Ib; + count = i->Ib(); else if ( i->b1 == 0xd1 ) count = 1; else // 0xd3 @@ -464,8 +464,8 @@ BX_CPU_C::SAR_Ew(BxInstruction_t *i) count &= 0x1F; /* use only 5 LSB's */ /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -494,8 +494,8 @@ BX_CPU_C::SAR_Ew(BxInstruction_t *i) /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, result_16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), result_16); } else { Write_RMW_virtual_word(result_16); diff --git a/bochs/cpu/shift32.cc b/bochs/cpu/shift32.cc index ead33d8cb..0cc914319 100644 --- a/bochs/cpu/shift32.cc +++ b/bochs/cpu/shift32.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: shift32.cc,v 1.8 2002-09-13 17:04:13 kevinlawton Exp $ +// $Id: shift32.cc,v 1.9 2002-09-17 22:50:53 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -35,7 +35,7 @@ void -BX_CPU_C::SHLD_EdGd(BxInstruction_t *i) +BX_CPU_C::SHLD_EdGd(bxInstruction_c *i) { Bit32u op1_32, op2_32, result_32; unsigned count; @@ -43,27 +43,27 @@ BX_CPU_C::SHLD_EdGd(BxInstruction_t *i) /* op1:op2 << count. result stored in op1 */ if (i->b1 == 0x1a4) - count = i->Ib & 0x1f; + count = i->Ib() & 0x1f; else // 0x1a5 count = CL & 0x1f; if (!count) return; /* NOP */ /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32); } - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); result_32 = (op1_32 << count) | (op2_32 >> (32 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -82,7 +82,7 @@ BX_CPU_C::SHLD_EdGd(BxInstruction_t *i) void -BX_CPU_C::SHRD_EdGd(BxInstruction_t *i) +BX_CPU_C::SHRD_EdGd(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("shrd_evgvib: not supported on < 386")); @@ -91,7 +91,7 @@ BX_CPU_C::SHRD_EdGd(BxInstruction_t *i) unsigned count; if (i->b1 == 0x1ac) - count = i->Ib & 0x1f; + count = i->Ib() & 0x1f; else // 0x1ad count = CL & 0x1f; @@ -99,20 +99,20 @@ BX_CPU_C::SHRD_EdGd(BxInstruction_t *i) /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32); } - op2_32 = BX_READ_32BIT_REG(i->nnn); + op2_32 = BX_READ_32BIT_REG(i->nnn()); result_32 = (op2_32 << (32 - count)) | (op1_32 >> count); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -135,22 +135,22 @@ BX_CPU_C::SHRD_EdGd(BxInstruction_t *i) void -BX_CPU_C::ROL_Ed(BxInstruction_t *i) +BX_CPU_C::ROL_Ed(bxInstruction_c *i) { Bit32u op1_32, result_32; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x1f; + count = i->Ib() & 0x1f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) count = CL & 0x1f; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -161,8 +161,8 @@ BX_CPU_C::ROL_Ed(BxInstruction_t *i) result_32 = (op1_32 << count) | (op1_32 >> (32 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -182,21 +182,21 @@ BX_CPU_C::ROL_Ed(BxInstruction_t *i) void -BX_CPU_C::ROR_Ed(BxInstruction_t *i) +BX_CPU_C::ROR_Ed(bxInstruction_c *i) { Bit32u op1_32, result_32, result_b31; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x1f; + count = i->Ib() & 0x1f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) count = CL & 0x1f; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -207,8 +207,8 @@ BX_CPU_C::ROR_Ed(BxInstruction_t *i) result_32 = (op1_32 >> count) | (op1_32 << (32 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -228,13 +228,13 @@ BX_CPU_C::ROR_Ed(BxInstruction_t *i) void -BX_CPU_C::RCL_Ed(BxInstruction_t *i) +BX_CPU_C::RCL_Ed(bxInstruction_c *i) { Bit32u op1_32, result_32; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x1f; + count = i->Ib() & 0x1f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) @@ -242,8 +242,8 @@ BX_CPU_C::RCL_Ed(BxInstruction_t *i) /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -262,8 +262,8 @@ BX_CPU_C::RCL_Ed(BxInstruction_t *i) } /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -280,13 +280,13 @@ BX_CPU_C::RCL_Ed(BxInstruction_t *i) void -BX_CPU_C::RCR_Ed(BxInstruction_t *i) +BX_CPU_C::RCR_Ed(bxInstruction_c *i) { Bit32u op1_32, result_32; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x1f; + count = i->Ib() & 0x1f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) @@ -294,8 +294,8 @@ BX_CPU_C::RCR_Ed(BxInstruction_t *i) /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -314,8 +314,8 @@ BX_CPU_C::RCR_Ed(BxInstruction_t *i) } /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -334,21 +334,21 @@ BX_CPU_C::RCR_Ed(BxInstruction_t *i) void -BX_CPU_C::SHL_Ed(BxInstruction_t *i) +BX_CPU_C::SHL_Ed(bxInstruction_c *i) { Bit32u op1_32, result_32; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x1f; + count = i->Ib() & 0x1f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) count = CL & 0x1f; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -360,8 +360,8 @@ BX_CPU_C::SHL_Ed(BxInstruction_t *i) result_32 = (op1_32 << count); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -374,21 +374,21 @@ BX_CPU_C::SHL_Ed(BxInstruction_t *i) void -BX_CPU_C::SHR_Ed(BxInstruction_t *i) +BX_CPU_C::SHR_Ed(bxInstruction_c *i) { Bit32u op1_32, result_32; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x1f; + count = i->Ib() & 0x1f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) count = CL & 0x1f; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -400,8 +400,8 @@ BX_CPU_C::SHR_Ed(BxInstruction_t *i) result_32 = (op1_32 >> count); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); @@ -413,21 +413,21 @@ BX_CPU_C::SHR_Ed(BxInstruction_t *i) void -BX_CPU_C::SAR_Ed(BxInstruction_t *i) +BX_CPU_C::SAR_Ed(bxInstruction_c *i) { Bit32u op1_32, result_32; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x1f; + count = i->Ib() & 0x1f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) count = CL & 0x1f; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -445,8 +445,8 @@ BX_CPU_C::SAR_Ed(BxInstruction_t *i) } /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, result_32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), result_32); } else { Write_RMW_virtual_dword(result_32); diff --git a/bochs/cpu/shift64.cc b/bochs/cpu/shift64.cc index b9da41791..56d270151 100644 --- a/bochs/cpu/shift64.cc +++ b/bochs/cpu/shift64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: shift64.cc,v 1.1 2002-09-13 15:53:22 kevinlawton Exp $ +// $Id: shift64.cc,v 1.2 2002-09-17 22:50:53 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -35,7 +35,7 @@ void -BX_CPU_C::SHLD_EqGq(BxInstruction_t *i) +BX_CPU_C::SHLD_EqGq(bxInstruction_c *i) { Bit64u op1_64, op2_64, result_64; unsigned count; @@ -43,27 +43,27 @@ BX_CPU_C::SHLD_EqGq(BxInstruction_t *i) /* op1:op2 << count. result stored in op1 */ if (i->b1 == 0x1a4) - count = i->Ib & 0x3f; + count = i->Ib() & 0x3f; else // 0x1a5 count = CL & 0x3f; if (!count) return; /* NOP */ /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_RMW_virtual_qword(i->seg, i->rm_addr, &op1_64); } - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); result_64 = (op1_64 << count) | (op2_64 >> (64 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -82,7 +82,7 @@ BX_CPU_C::SHLD_EqGq(BxInstruction_t *i) void -BX_CPU_C::SHRD_EqGq(BxInstruction_t *i) +BX_CPU_C::SHRD_EqGq(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 BX_PANIC(("shrd_evgvib: not supported on < 386")); @@ -91,7 +91,7 @@ BX_CPU_C::SHRD_EqGq(BxInstruction_t *i) unsigned count; if (i->b1 == 0x1ac) - count = i->Ib & 0x3f; + count = i->Ib() & 0x3f; else // 0x1ad count = CL & 0x3f; @@ -99,20 +99,20 @@ BX_CPU_C::SHRD_EqGq(BxInstruction_t *i) /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ read_RMW_virtual_qword(i->seg, i->rm_addr, &op1_64); } - op2_64 = BX_READ_64BIT_REG(i->nnn); + op2_64 = BX_READ_64BIT_REG(i->nnn()); result_64 = (op2_64 << (64 - count)) | (op1_64 >> count); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -135,22 +135,22 @@ BX_CPU_C::SHRD_EqGq(BxInstruction_t *i) void -BX_CPU_C::ROL_Eq(BxInstruction_t *i) +BX_CPU_C::ROL_Eq(bxInstruction_c *i) { Bit64u op1_64, result_64; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x3f; + count = i->Ib() & 0x3f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) count = CL & 0x3f; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -161,8 +161,8 @@ BX_CPU_C::ROL_Eq(BxInstruction_t *i) result_64 = (op1_64 << count) | (op1_64 >> (64 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -182,21 +182,21 @@ BX_CPU_C::ROL_Eq(BxInstruction_t *i) void -BX_CPU_C::ROR_Eq(BxInstruction_t *i) +BX_CPU_C::ROR_Eq(bxInstruction_c *i) { Bit64u op1_64, result_64, result_b63; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x3f; + count = i->Ib() & 0x3f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) count = CL & 0x3f; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -207,8 +207,8 @@ BX_CPU_C::ROR_Eq(BxInstruction_t *i) result_64 = (op1_64 >> count) | (op1_64 << (64 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -228,13 +228,13 @@ BX_CPU_C::ROR_Eq(BxInstruction_t *i) void -BX_CPU_C::RCL_Eq(BxInstruction_t *i) +BX_CPU_C::RCL_Eq(bxInstruction_c *i) { Bit64u op1_64, result_64; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x3f; + count = i->Ib() & 0x3f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) @@ -242,8 +242,8 @@ BX_CPU_C::RCL_Eq(BxInstruction_t *i) /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -262,8 +262,8 @@ BX_CPU_C::RCL_Eq(BxInstruction_t *i) } /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -280,13 +280,13 @@ BX_CPU_C::RCL_Eq(BxInstruction_t *i) void -BX_CPU_C::RCR_Eq(BxInstruction_t *i) +BX_CPU_C::RCR_Eq(bxInstruction_c *i) { Bit64u op1_64, result_64; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x3f; + count = i->Ib() & 0x3f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) @@ -294,8 +294,8 @@ BX_CPU_C::RCR_Eq(BxInstruction_t *i) /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -314,8 +314,8 @@ BX_CPU_C::RCR_Eq(BxInstruction_t *i) } /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -334,21 +334,21 @@ BX_CPU_C::RCR_Eq(BxInstruction_t *i) void -BX_CPU_C::SHL_Eq(BxInstruction_t *i) +BX_CPU_C::SHL_Eq(bxInstruction_c *i) { Bit64u op1_64, result_64; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x3f; + count = i->Ib() & 0x3f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) count = CL & 0x3f; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -360,8 +360,8 @@ BX_CPU_C::SHL_Eq(BxInstruction_t *i) result_64 = (op1_64 << count); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -374,21 +374,21 @@ BX_CPU_C::SHL_Eq(BxInstruction_t *i) void -BX_CPU_C::SHR_Eq(BxInstruction_t *i) +BX_CPU_C::SHR_Eq(bxInstruction_c *i) { Bit64u op1_64, result_64; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x3f; + count = i->Ib() & 0x3f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) count = CL & 0x3f; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -400,8 +400,8 @@ BX_CPU_C::SHR_Eq(BxInstruction_t *i) result_64 = (op1_64 >> count); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); @@ -413,21 +413,21 @@ BX_CPU_C::SHR_Eq(BxInstruction_t *i) void -BX_CPU_C::SAR_Eq(BxInstruction_t *i) +BX_CPU_C::SAR_Eq(bxInstruction_c *i) { Bit64u op1_64, result_64; unsigned count; if (i->b1 == 0xc1) - count = i->Ib & 0x3f; + count = i->Ib() & 0x3f; else if (i->b1 == 0xd1) count = 1; else // (i->b1 == 0xd3) count = CL & 0x3f; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -445,8 +445,8 @@ BX_CPU_C::SAR_Eq(BxInstruction_t *i) } /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, result_64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), result_64); } else { write_RMW_virtual_qword(result_64); diff --git a/bochs/cpu/shift8.cc b/bochs/cpu/shift8.cc index 308bcf6f4..8d117b238 100644 --- a/bochs/cpu/shift8.cc +++ b/bochs/cpu/shift8.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: shift8.cc,v 1.7 2002-09-13 17:04:14 kevinlawton Exp $ +// $Id: shift8.cc,v 1.8 2002-09-17 22:50:53 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -38,13 +38,13 @@ void -BX_CPU_C::ROL_Eb(BxInstruction_t *i) +BX_CPU_C::ROL_Eb(bxInstruction_c *i) { Bit8u op1_8, result_8; unsigned count; if (i->b1 == 0xc0) - count = i->Ib; + count = i->Ib(); else if (i->b1 == 0xd0) count = 1; else // 0xd2 @@ -53,8 +53,8 @@ BX_CPU_C::ROL_Eb(BxInstruction_t *i) count &= 0x07; // use only lowest 3 bits /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -65,8 +65,8 @@ BX_CPU_C::ROL_Eb(BxInstruction_t *i) result_8 = (op1_8 << count) | (op1_8 >> (8 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { Write_RMW_virtual_byte(result_8); @@ -86,14 +86,14 @@ BX_CPU_C::ROL_Eb(BxInstruction_t *i) void -BX_CPU_C::ROR_Eb(BxInstruction_t *i) +BX_CPU_C::ROR_Eb(bxInstruction_c *i) { Bit8u op1_8, result_8; Bit8u result_b7; unsigned count; if (i->b1 == 0xc0) - count = i->Ib; + count = i->Ib(); else if (i->b1 == 0xd0) count = 1; else // 0xd2 @@ -103,8 +103,8 @@ BX_CPU_C::ROR_Eb(BxInstruction_t *i) count &= 0x07; /* use only bottom 3 bits */ /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -115,8 +115,8 @@ BX_CPU_C::ROR_Eb(BxInstruction_t *i) result_8 = (op1_8 >> count) | (op1_8 << (8 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { Write_RMW_virtual_byte(result_8); @@ -136,13 +136,13 @@ BX_CPU_C::ROR_Eb(BxInstruction_t *i) void -BX_CPU_C::RCL_Eb(BxInstruction_t *i) +BX_CPU_C::RCL_Eb(bxInstruction_c *i) { Bit8u op1_8, result_8; unsigned count; if (i->b1 == 0xc0) - count = i->Ib; + count = i->Ib(); else if (i->b1 == 0xd0) count = 1; else // 0xd2 @@ -152,8 +152,8 @@ BX_CPU_C::RCL_Eb(BxInstruction_t *i) /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -166,8 +166,8 @@ BX_CPU_C::RCL_Eb(BxInstruction_t *i) (op1_8 >> (9 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { Write_RMW_virtual_byte(result_8); @@ -185,13 +185,13 @@ BX_CPU_C::RCL_Eb(BxInstruction_t *i) void -BX_CPU_C::RCR_Eb(BxInstruction_t *i) +BX_CPU_C::RCR_Eb(bxInstruction_c *i) { Bit8u op1_8, result_8; unsigned count; if (i->b1 == 0xc0) - count = i->Ib; + count = i->Ib(); else if (i->b1 == 0xd0) count = 1; else // 0xd2 @@ -200,8 +200,8 @@ BX_CPU_C::RCR_Eb(BxInstruction_t *i) count = ( count & 0x1F ) % 9; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -214,8 +214,8 @@ BX_CPU_C::RCR_Eb(BxInstruction_t *i) (op1_8 << (9 - count)); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { Write_RMW_virtual_byte(result_8); @@ -235,13 +235,13 @@ BX_CPU_C::RCR_Eb(BxInstruction_t *i) void -BX_CPU_C::SHL_Eb(BxInstruction_t *i) +BX_CPU_C::SHL_Eb(bxInstruction_c *i) { Bit8u op1_8, result_8; unsigned count; if (i->b1 == 0xc0) - count = i->Ib; + count = i->Ib(); else if (i->b1 == 0xd0) count = 1; else // 0xd2 @@ -250,8 +250,8 @@ BX_CPU_C::SHL_Eb(BxInstruction_t *i) count &= 0x1F; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -263,8 +263,8 @@ BX_CPU_C::SHL_Eb(BxInstruction_t *i) result_8 = (op1_8 << count); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { Write_RMW_virtual_byte(result_8); @@ -276,13 +276,13 @@ BX_CPU_C::SHL_Eb(BxInstruction_t *i) void -BX_CPU_C::SHR_Eb(BxInstruction_t *i) +BX_CPU_C::SHR_Eb(bxInstruction_c *i) { Bit8u op1_8, result_8; unsigned count; if (i->b1 == 0xc0) - count = i->Ib; + count = i->Ib(); else if (i->b1 == 0xd0) count = 1; else // 0xd2 @@ -291,8 +291,8 @@ BX_CPU_C::SHR_Eb(BxInstruction_t *i) count &= 0x1F; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -304,8 +304,8 @@ BX_CPU_C::SHR_Eb(BxInstruction_t *i) result_8 = (op1_8 >> count); /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { Write_RMW_virtual_byte(result_8); @@ -318,13 +318,13 @@ BX_CPU_C::SHR_Eb(BxInstruction_t *i) void -BX_CPU_C::SAR_Eb(BxInstruction_t *i) +BX_CPU_C::SAR_Eb(bxInstruction_c *i) { Bit8u op1_8, result_8; unsigned count; if (i->b1 == 0xc0) - count = i->Ib; + count = i->Ib(); else if (i->b1 == 0xd0) count = 1; else // 0xd2 @@ -333,8 +333,8 @@ BX_CPU_C::SAR_Eb(BxInstruction_t *i) count &= 0x1F; /* op1 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_8 = BX_READ_8BIT_REGx(i->rm,i->extend8bit); + if (i->mod() == 0xc0) { + op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bit); } else { /* pointer, segment address pair */ @@ -361,8 +361,8 @@ BX_CPU_C::SAR_Eb(BxInstruction_t *i) } /* now write result back to destination */ - if (i->mod == 0xc0) { - BX_WRITE_8BIT_REGx(i->rm, i->extend8bit, result_8); + if (i->mod() == 0xc0) { + BX_WRITE_8BIT_REGx(i->rm(), i->extend8bit, result_8); } else { Write_RMW_virtual_byte(result_8); diff --git a/bochs/cpu/soft_int.cc b/bochs/cpu/soft_int.cc index c3210348a..98ca3b817 100644 --- a/bochs/cpu/soft_int.cc +++ b/bochs/cpu/soft_int.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: soft_int.cc,v 1.8 2002-09-13 00:15:23 kevinlawton Exp $ +// $Id: soft_int.cc,v 1.9 2002-09-17 22:50:53 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -40,13 +40,13 @@ void -BX_CPU_C::BOUND_GvMa(BxInstruction_t *i) +BX_CPU_C::BOUND_GvMa(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("BOUND_GvMa: not supported on 8086!")); #else - if (i->mod == 0xc0) { + if (i->mod() == 0xc0) { /* undefined opcode exception */ BX_PANIC(("bound: op2 must be mem ref")); UndefinedOpcode(i); @@ -56,7 +56,7 @@ BX_CPU_C::BOUND_GvMa(BxInstruction_t *i) Bit32s bound_min, bound_max; Bit32s op1_32; - op1_32 = BX_READ_32BIT_REG(i->nnn); + op1_32 = BX_READ_32BIT_REG(i->nnn()); read_virtual_dword(i->seg, i->rm_addr, (Bit32u *) &bound_min); read_virtual_dword(i->seg, i->rm_addr+4, (Bit32u *) &bound_max); @@ -71,7 +71,7 @@ BX_CPU_C::BOUND_GvMa(BxInstruction_t *i) Bit16s bound_min, bound_max; Bit16s op1_16; - op1_16 = BX_READ_16BIT_REG(i->nnn); + op1_16 = BX_READ_16BIT_REG(i->nnn()); read_virtual_word(i->seg, i->rm_addr, (Bit16u *) &bound_min); read_virtual_word(i->seg, i->rm_addr+2, (Bit16u *) &bound_max); @@ -87,7 +87,7 @@ BX_CPU_C::BOUND_GvMa(BxInstruction_t *i) } void -BX_CPU_C::INT1(BxInstruction_t *i) +BX_CPU_C::INT1(bxInstruction_c *i) { // This is an undocumented instrucion (opcode 0xf1) // which is useful for an ICE system. @@ -103,7 +103,7 @@ BX_CPU_C::INT1(BxInstruction_t *i) } void -BX_CPU_C::INT3(BxInstruction_t *i) +BX_CPU_C::INT3(bxInstruction_c *i) { // INT 3 is not IOPL sensitive @@ -120,7 +120,7 @@ BX_CPU_C::INT3(BxInstruction_t *i) void -BX_CPU_C::INT_Ib(BxInstruction_t *i) +BX_CPU_C::INT_Ib(bxInstruction_c *i) { Bit8u imm8; @@ -128,7 +128,7 @@ BX_CPU_C::INT_Ib(BxInstruction_t *i) BX_CPU_THIS_PTR show_flag |= Flag_int; #endif - imm8 = i->Ib; + imm8 = i->Ib(); if (v8086_mode() && (BX_CPU_THIS_PTR get_IOPL()<3)) { //BX_INFO(("int_ib: v8086: IOPL<3")); @@ -149,7 +149,7 @@ if ( (imm8 == 0x21) && (AH == 0x4c) ) { void -BX_CPU_C::INTO(BxInstruction_t *i) +BX_CPU_C::INTO(bxInstruction_c *i) { #if BX_DEBUGGER diff --git a/bochs/cpu/stack16.cc b/bochs/cpu/stack16.cc index e1f1a4fa6..45dc17ea7 100644 --- a/bochs/cpu/stack16.cc +++ b/bochs/cpu/stack16.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: stack16.cc,v 1.8 2002-09-13 17:28:14 kevinlawton Exp $ +// $Id: stack16.cc,v 1.9 2002-09-17 22:50:53 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -37,44 +37,46 @@ void -BX_CPU_C::PUSH_RX(BxInstruction_t *i) +BX_CPU_C::PUSH_RX(bxInstruction_c *i) { -#if BX_SUPPORT_X86_64 - push_16( BX_CPU_THIS_PTR gen_reg[i->nnn].word.rx ); -#else - push_16( BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx ); -#endif + push_16( BX_CPU_THIS_PTR gen_reg[(i->b1 & 0x07) + i->rex_b()].word.rx ); +//#if BX_SUPPORT_X86_64 +// push_16( BX_CPU_THIS_PTR gen_reg[i->nnn()].word.rx ); +//#else +// push_16( BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx ); +//#endif } void -BX_CPU_C::POP_RX(BxInstruction_t *i) +BX_CPU_C::POP_RX(bxInstruction_c *i) { Bit16u rx; pop_16(&rx); -#if BX_SUPPORT_X86_64 - BX_CPU_THIS_PTR gen_reg[i->nnn].word.rx = rx; -#else - BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx = rx; -#endif + BX_CPU_THIS_PTR gen_reg[(i->b1 & 0x07) + i->rex_b()].word.rx = rx; +//#if BX_SUPPORT_X86_64 +// BX_CPU_THIS_PTR gen_reg[i->nnn()].word.rx = rx; +//#else +// BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx = rx; +//#endif } void -BX_CPU_C::POP_Ew(BxInstruction_t *i) +BX_CPU_C::POP_Ew(bxInstruction_c *i) { Bit16u val16; pop_16(&val16); - if (i->mod == 0xc0) { - BX_WRITE_16BIT_REG(i->rm, val16); + if (i->mod() == 0xc0) { + BX_WRITE_16BIT_REG(i->rm(), val16); } else { // Note: there is one little weirdism here. When 32bit addressing // is used, it is possible to use ESP in the modrm addressing. // If used, the value of ESP after the pop is used to calculate // the address. - if (i->as_32 && (i->mod!=0xc0) && (i->rm==4) && (i->base==4)) { + if (i->as_32 && (i->mod()!=0xc0) && (i->rm()==4) && (i->sibBase()==4)) { BX_CPU_CALL_METHOD (i->ResolveModrm, (i)); } write_virtual_word(i->seg, i->rm_addr, &val16); @@ -82,7 +84,7 @@ BX_CPU_C::POP_Ew(BxInstruction_t *i) } void -BX_CPU_C::PUSHAD16(BxInstruction_t *i) +BX_CPU_C::PUSHAD16(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("PUSHAD: not supported on an 8086")); @@ -126,7 +128,7 @@ BX_CPU_C::PUSHAD16(BxInstruction_t *i) } void -BX_CPU_C::POPAD16(BxInstruction_t *i) +BX_CPU_C::POPAD16(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("POPAD not supported on an 8086")); @@ -163,7 +165,7 @@ BX_CPU_C::POPAD16(BxInstruction_t *i) } void -BX_CPU_C::PUSH_Iw(BxInstruction_t *i) +BX_CPU_C::PUSH_Iw(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("PUSH_Iv: not supported on 8086!")); @@ -171,20 +173,20 @@ BX_CPU_C::PUSH_Iw(BxInstruction_t *i) Bit16u imm16; - imm16 = i->Iw; + imm16 = i->Iw(); push_16(imm16); #endif } void -BX_CPU_C::PUSH_Ew(BxInstruction_t *i) +BX_CPU_C::PUSH_Ew(bxInstruction_c *i) { Bit16u op1_16; /* op1_16 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_16 = BX_READ_16BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_16 = BX_READ_16BIT_REG(i->rm()); } else { /* pointer, segment address pair */ diff --git a/bochs/cpu/stack32.cc b/bochs/cpu/stack32.cc index c64d22200..32b5bfcc8 100644 --- a/bochs/cpu/stack32.cc +++ b/bochs/cpu/stack32.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: stack32.cc,v 1.10 2002-09-15 01:00:20 kevinlawton Exp $ +// $Id: stack32.cc,v 1.11 2002-09-17 22:50:53 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -45,21 +45,21 @@ void -BX_CPU_C::POP_Ed(BxInstruction_t *i) +BX_CPU_C::POP_Ed(bxInstruction_c *i) { Bit32u val32; pop_32(&val32); - if (i->mod == 0xc0) { - BX_WRITE_32BIT_REGZ(i->rm, val32); + if (i->mod() == 0xc0) { + BX_WRITE_32BIT_REGZ(i->rm(), val32); } else { // Note: there is one little weirdism here. When 32bit addressing // is used, it is possible to use ESP in the modrm addressing. // If used, the value of ESP after the pop is used to calculate // the address. - if (i->as_32 && (i->mod!=0xc0) && (i->rm==4) && (i->base==4)) { + if (i->as_32 && (i->mod()!=0xc0) && (i->rm()==4) && (i->sibBase()==4)) { // call method on BX_CPU_C object BX_CPU_CALL_METHOD (i->ResolveModrm, (i)); } @@ -68,31 +68,33 @@ BX_CPU_C::POP_Ed(BxInstruction_t *i) } void -BX_CPU_C::PUSH_ERX(BxInstruction_t *i) +BX_CPU_C::PUSH_ERX(bxInstruction_c *i) { -#if BX_SUPPORT_X86_64 - push_32(BX_CPU_THIS_PTR gen_reg[i->nnn].dword.erx); -#else - push_32(BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx); -#endif + push_32(BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].dword.erx); +//#if BX_SUPPORT_X86_64 +// push_32(BX_CPU_THIS_PTR gen_reg[i->nnn()].dword.erx); +//#else +// push_32(BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx); +//#endif } void -BX_CPU_C::POP_ERX(BxInstruction_t *i) +BX_CPU_C::POP_ERX(bxInstruction_c *i) { Bit32u erx; pop_32(&erx); -#if BX_SUPPORT_X86_64 - BX_CPU_THIS_PTR gen_reg[i->nnn].dword.erx = erx; -#else - BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx = erx; -#endif + BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].dword.erx = erx; +//#if BX_SUPPORT_X86_64 +// BX_CPU_THIS_PTR gen_reg[i->nnn()].dword.erx = erx; +//#else +// BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].dword.erx = erx; +//#endif } void -BX_CPU_C::PUSH_CS(BxInstruction_t *i) +BX_CPU_C::PUSH_CS(bxInstruction_c *i) { if (i->os_32) push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value); @@ -100,7 +102,7 @@ BX_CPU_C::PUSH_CS(BxInstruction_t *i) push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value); } void -BX_CPU_C::PUSH_DS(BxInstruction_t *i) +BX_CPU_C::PUSH_DS(bxInstruction_c *i) { if (i->os_32) push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value); @@ -108,7 +110,7 @@ BX_CPU_C::PUSH_DS(BxInstruction_t *i) push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value); } void -BX_CPU_C::PUSH_ES(BxInstruction_t *i) +BX_CPU_C::PUSH_ES(bxInstruction_c *i) { if (i->os_32) push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value); @@ -116,7 +118,7 @@ BX_CPU_C::PUSH_ES(BxInstruction_t *i) push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value); } void -BX_CPU_C::PUSH_FS(BxInstruction_t *i) +BX_CPU_C::PUSH_FS(bxInstruction_c *i) { if (i->os_32) push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value); @@ -124,7 +126,7 @@ BX_CPU_C::PUSH_FS(BxInstruction_t *i) push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value); } void -BX_CPU_C::PUSH_GS(BxInstruction_t *i) +BX_CPU_C::PUSH_GS(bxInstruction_c *i) { if (i->os_32) push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value); @@ -132,7 +134,7 @@ BX_CPU_C::PUSH_GS(BxInstruction_t *i) push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value); } void -BX_CPU_C::PUSH_SS(BxInstruction_t *i) +BX_CPU_C::PUSH_SS(bxInstruction_c *i) { if (i->os_32) push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value); @@ -142,7 +144,7 @@ BX_CPU_C::PUSH_SS(BxInstruction_t *i) void -BX_CPU_C::POP_DS(BxInstruction_t *i) +BX_CPU_C::POP_DS(bxInstruction_c *i) { if (i->os_32) { Bit32u ds; @@ -156,7 +158,7 @@ BX_CPU_C::POP_DS(BxInstruction_t *i) } } void -BX_CPU_C::POP_ES(BxInstruction_t *i) +BX_CPU_C::POP_ES(bxInstruction_c *i) { if (i->os_32) { Bit32u es; @@ -170,7 +172,7 @@ BX_CPU_C::POP_ES(BxInstruction_t *i) } } void -BX_CPU_C::POP_FS(BxInstruction_t *i) +BX_CPU_C::POP_FS(bxInstruction_c *i) { if (i->os_32) { Bit32u fs; @@ -184,7 +186,7 @@ BX_CPU_C::POP_FS(BxInstruction_t *i) } } void -BX_CPU_C::POP_GS(BxInstruction_t *i) +BX_CPU_C::POP_GS(bxInstruction_c *i) { if (i->os_32) { Bit32u gs; @@ -198,7 +200,7 @@ BX_CPU_C::POP_GS(BxInstruction_t *i) } } void -BX_CPU_C::POP_SS(BxInstruction_t *i) +BX_CPU_C::POP_SS(bxInstruction_c *i) { if (i->os_32) { Bit32u ss; @@ -222,7 +224,7 @@ BX_CPU_C::POP_SS(BxInstruction_t *i) void -BX_CPU_C::PUSHAD32(BxInstruction_t *i) +BX_CPU_C::PUSHAD32(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("PUSHAD: not supported on an 8086")); @@ -263,7 +265,7 @@ BX_CPU_C::PUSHAD32(BxInstruction_t *i) } void -BX_CPU_C::POPAD32(BxInstruction_t *i) +BX_CPU_C::POPAD32(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("POPAD not supported on an 8086")); @@ -299,7 +301,7 @@ BX_CPU_C::POPAD32(BxInstruction_t *i) } void -BX_CPU_C::PUSH_Id(BxInstruction_t *i) +BX_CPU_C::PUSH_Id(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("PUSH_Iv: not supported on 8086!")); @@ -307,20 +309,20 @@ BX_CPU_C::PUSH_Id(BxInstruction_t *i) Bit32u imm32; - imm32 = i->Id; + imm32 = i->Id(); push_32(imm32); #endif } void -BX_CPU_C::PUSH_Ed(BxInstruction_t *i) +BX_CPU_C::PUSH_Ed(bxInstruction_c *i) { Bit32u op1_32; /* op1_32 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_32 = BX_READ_32BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_32 = BX_READ_32BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -332,7 +334,7 @@ BX_CPU_C::PUSH_Ed(BxInstruction_t *i) void -BX_CPU_C::ENTER_IwIb(BxInstruction_t *i) +BX_CPU_C::ENTER_IwIb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("ENTER_IwIb: not supported by 8086!")); @@ -342,7 +344,7 @@ BX_CPU_C::ENTER_IwIb(BxInstruction_t *i) Bit8u level; static Bit8u first_time = 1; - level = i->Ib2; + level = i->Ib2(); invalidate_prefetch_q(); @@ -362,15 +364,15 @@ BX_CPU_C::ENTER_IwIb(BxInstruction_t *i) if (level == 0) { if (i->os_32) - bytes_to_push = 4 + i->Iw; + bytes_to_push = 4 + i->Iw(); else - bytes_to_push = 2 + i->Iw; + bytes_to_push = 2 + i->Iw(); } else { /* level > 0 */ if (i->os_32) - bytes_to_push = 4 + (level-1)*4 + 4 + i->Iw; + bytes_to_push = 4 + (level-1)*4 + 4 + i->Iw(); else - bytes_to_push = 2 + (level-1)*2 + 2 + i->Iw; + bytes_to_push = 2 + (level-1)*2 + 2 + i->Iw(); } if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) temp_ESP = ESP; @@ -461,16 +463,16 @@ BX_CPU_C::ENTER_IwIb(BxInstruction_t *i) BP = frame_ptr32; if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) { /* 32bit stacksize */ - ESP = ESP - i->Iw; + ESP = ESP - i->Iw(); } else { /* 16bit stack */ - SP = SP - i->Iw; + SP = SP - i->Iw(); } #endif } void -BX_CPU_C::LEAVE(BxInstruction_t *i) +BX_CPU_C::LEAVE(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("LEAVE: not supported by 8086!")); diff --git a/bochs/cpu/stack64.cc b/bochs/cpu/stack64.cc index 7ef82af3a..0d880babb 100644 --- a/bochs/cpu/stack64.cc +++ b/bochs/cpu/stack64.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: stack64.cc,v 1.1 2002-09-13 15:53:22 kevinlawton Exp $ +// $Id: stack64.cc,v 1.2 2002-09-17 22:50:53 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -38,21 +38,21 @@ void -BX_CPU_C::POP_Eq(BxInstruction_t *i) +BX_CPU_C::POP_Eq(bxInstruction_c *i) { Bit64u val64; pop_64(&val64); - if (i->mod == 0xc0) { - BX_WRITE_64BIT_REG(i->rm, val64); + if (i->mod() == 0xc0) { + BX_WRITE_64BIT_REG(i->rm(), val64); } else { // Note: there is one little weirdism here. When 64bit addressing // is used, it is possible to use RSP in the modrm addressing. // If used, the value of RSP after the pop is used to calculate // the address. - if (i->as_64 && (i->mod!=0xc0) && (i->rm==4) && (i->base==4)) { + if (i->as_64 && (i->mod()!=0xc0) && (i->rm()==4) && (i->sibBase()==4)) { // call method on BX_CPU_C object BX_CPU_CALL_METHOD (i->ResolveModrm, (i)); } @@ -61,83 +61,85 @@ BX_CPU_C::POP_Eq(BxInstruction_t *i) } void -BX_CPU_C::PUSH_RRX(BxInstruction_t *i) +BX_CPU_C::PUSH_RRX(bxInstruction_c *i) { - push_64(BX_CPU_THIS_PTR gen_reg[i->nnn].rrx); + push_64(BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].rrx); + //push_64(BX_CPU_THIS_PTR gen_reg[i->nnn()].rrx); } void -BX_CPU_C::POP_RRX(BxInstruction_t *i) +BX_CPU_C::POP_RRX(bxInstruction_c *i) { Bit64u rrx; pop_64(&rrx); - BX_CPU_THIS_PTR gen_reg[i->nnn].rrx = rrx; + BX_CPU_THIS_PTR gen_reg[(i->b1 & 7) + i->rex_b()].rrx = rrx; + //BX_CPU_THIS_PTR gen_reg[i->nnn()].rrx = rrx; } void -BX_CPU_C::PUSH64_CS(BxInstruction_t *i) +BX_CPU_C::PUSH64_CS(bxInstruction_c *i) { push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value); } void -BX_CPU_C::PUSH64_DS(BxInstruction_t *i) +BX_CPU_C::PUSH64_DS(bxInstruction_c *i) { push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value); } void -BX_CPU_C::PUSH64_ES(BxInstruction_t *i) +BX_CPU_C::PUSH64_ES(bxInstruction_c *i) { push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value); } void -BX_CPU_C::PUSH64_FS(BxInstruction_t *i) +BX_CPU_C::PUSH64_FS(bxInstruction_c *i) { push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value); } void -BX_CPU_C::PUSH64_GS(BxInstruction_t *i) +BX_CPU_C::PUSH64_GS(bxInstruction_c *i) { push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value); } void -BX_CPU_C::PUSH64_SS(BxInstruction_t *i) +BX_CPU_C::PUSH64_SS(bxInstruction_c *i) { push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value); } void -BX_CPU_C::POP64_DS(BxInstruction_t *i) +BX_CPU_C::POP64_DS(bxInstruction_c *i) { Bit64u ds; pop_64(&ds); load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], (Bit16u) ds); } void -BX_CPU_C::POP64_ES(BxInstruction_t *i) +BX_CPU_C::POP64_ES(bxInstruction_c *i) { Bit64u es; pop_64(&es); load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], (Bit16u) es); } void -BX_CPU_C::POP64_FS(BxInstruction_t *i) +BX_CPU_C::POP64_FS(bxInstruction_c *i) { Bit64u fs; pop_64(&fs); load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], (Bit16u) fs); } void -BX_CPU_C::POP64_GS(BxInstruction_t *i) +BX_CPU_C::POP64_GS(bxInstruction_c *i) { Bit64u gs; pop_64(&gs); load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], (Bit16u) gs); } void -BX_CPU_C::POP64_SS(BxInstruction_t *i) +BX_CPU_C::POP64_SS(bxInstruction_c *i) { Bit64u ss; pop_64(&ss); @@ -154,7 +156,7 @@ BX_CPU_C::POP64_SS(BxInstruction_t *i) void -BX_CPU_C::PUSHAD64(BxInstruction_t *i) +BX_CPU_C::PUSHAD64(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("PUSHAD: not supported on an 8086")); @@ -184,7 +186,7 @@ BX_CPU_C::PUSHAD64(BxInstruction_t *i) } void -BX_CPU_C::POPAD64(BxInstruction_t *i) +BX_CPU_C::POPAD64(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("POPAD not supported on an 8086")); @@ -218,7 +220,7 @@ BX_CPU_C::POPAD64(BxInstruction_t *i) } void -BX_CPU_C::PUSH64_Id(BxInstruction_t *i) +BX_CPU_C::PUSH64_Id(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("PUSH_Id: not supported on 8086!")); @@ -226,20 +228,20 @@ BX_CPU_C::PUSH64_Id(BxInstruction_t *i) Bit64u imm64; - imm64 = (Bit32s) i->Id; + imm64 = (Bit32s) i->Id(); push_64(imm64); #endif } void -BX_CPU_C::PUSH_Eq(BxInstruction_t *i) +BX_CPU_C::PUSH_Eq(bxInstruction_c *i) { Bit64u op1_64; /* op1_64 is a register or memory reference */ - if (i->mod == 0xc0) { - op1_64 = BX_READ_64BIT_REG(i->rm); + if (i->mod() == 0xc0) { + op1_64 = BX_READ_64BIT_REG(i->rm()); } else { /* pointer, segment address pair */ @@ -251,7 +253,7 @@ BX_CPU_C::PUSH_Eq(BxInstruction_t *i) void -BX_CPU_C::ENTER64_IwIb(BxInstruction_t *i) +BX_CPU_C::ENTER64_IwIb(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("ENTER_IwIb: not supported by 8086!")); @@ -261,7 +263,7 @@ BX_CPU_C::ENTER64_IwIb(BxInstruction_t *i) Bit8u level; static Bit8u first_time = 1; - level = i->Ib2; + level = i->Ib2(); invalidate_prefetch_q(); @@ -280,10 +282,10 @@ BX_CPU_C::ENTER64_IwIb(BxInstruction_t *i) Bit64u bytes_to_push, temp_RSP; if (level == 0) { - bytes_to_push = 8 + i->Iw; + bytes_to_push = 8 + i->Iw(); } else { /* level > 0 */ - bytes_to_push = 8 + (level-1)*8 + 8 + i->Iw; + bytes_to_push = 8 + (level-1)*8 + 8 + i->Iw(); } temp_RSP = RSP; if ( !can_push(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache, temp_RSP, bytes_to_push) ) { @@ -314,12 +316,12 @@ BX_CPU_C::ENTER64_IwIb(BxInstruction_t *i) RBP = frame_ptr64; - RSP = RSP - i->Iw; + RSP = RSP - i->Iw(); #endif } void -BX_CPU_C::LEAVE64(BxInstruction_t *i) +BX_CPU_C::LEAVE64(bxInstruction_c *i) { #if BX_CPU_LEVEL < 2 BX_PANIC(("LEAVE: not supported by 8086!")); diff --git a/bochs/cpu/string.cc b/bochs/cpu/string.cc index 79a1f75a2..890d13f9e 100644 --- a/bochs/cpu/string.cc +++ b/bochs/cpu/string.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: string.cc,v 1.11 2002-09-15 05:09:18 kevinlawton Exp $ +// $Id: string.cc,v 1.12 2002-09-17 22:50:53 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -47,7 +47,7 @@ */ void -BX_CPU_C::MOVSB_XbYb(BxInstruction_t *i) +BX_CPU_C::MOVSB_XbYb(bxInstruction_c *i) { unsigned seg; Bit8u temp8; @@ -307,7 +307,7 @@ doIncr16: } void -BX_CPU_C::MOVSW_XvYv(BxInstruction_t *i) +BX_CPU_C::MOVSW_XvYv(bxInstruction_c *i) { unsigned seg; unsigned incr; @@ -855,7 +855,7 @@ doIncr16: } void -BX_CPU_C::CMPSB_XbYb(BxInstruction_t *i) +BX_CPU_C::CMPSB_XbYb(bxInstruction_c *i) { unsigned seg; Bit8u op1_8, op2_8, diff_8; @@ -963,7 +963,7 @@ BX_CPU_C::CMPSB_XbYb(BxInstruction_t *i) } void -BX_CPU_C::CMPSW_XvYv(BxInstruction_t *i) +BX_CPU_C::CMPSW_XvYv(bxInstruction_c *i) { unsigned seg; @@ -1202,7 +1202,7 @@ BX_CPU_C::CMPSW_XvYv(BxInstruction_t *i) } void -BX_CPU_C::SCASB_ALXb(BxInstruction_t *i) +BX_CPU_C::SCASB_ALXb(bxInstruction_c *i) { Bit8u op1_8, op2_8, diff_8; @@ -1294,7 +1294,7 @@ BX_CPU_C::SCASB_ALXb(BxInstruction_t *i) } void -BX_CPU_C::SCASW_eAXXv(BxInstruction_t *i) +BX_CPU_C::SCASW_eAXXv(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 3 #if BX_SUPPORT_X86_64 @@ -1490,7 +1490,7 @@ BX_CPU_C::SCASW_eAXXv(BxInstruction_t *i) } void -BX_CPU_C::STOSB_YbAL(BxInstruction_t *i) +BX_CPU_C::STOSB_YbAL(bxInstruction_c *i) { Bit8u al; @@ -1691,7 +1691,7 @@ doIncr16: } void -BX_CPU_C::STOSW_YveAX(BxInstruction_t *i) +BX_CPU_C::STOSW_YveAX(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 3 #if BX_SUPPORT_X86_64 @@ -1858,7 +1858,7 @@ BX_CPU_C::STOSW_YveAX(BxInstruction_t *i) void -BX_CPU_C::LODSB_ALXb(BxInstruction_t *i) +BX_CPU_C::LODSB_ALXb(bxInstruction_c *i) { unsigned seg; Bit8u al; @@ -1938,7 +1938,7 @@ BX_CPU_C::LODSB_ALXb(BxInstruction_t *i) } void -BX_CPU_C::LODSW_eAXXv(BxInstruction_t *i) +BX_CPU_C::LODSW_eAXXv(bxInstruction_c *i) { unsigned seg; diff --git a/bochs/cpu/vm8086.cc b/bochs/cpu/vm8086.cc index 9ea011e27..2d5afa08f 100644 --- a/bochs/cpu/vm8086.cc +++ b/bochs/cpu/vm8086.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: vm8086.cc,v 1.13 2002-09-13 22:02:11 kevinlawton Exp $ +// $Id: vm8086.cc,v 1.14 2002-09-17 22:50:53 kevinlawton Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -127,7 +127,7 @@ BX_CPU_C::stack_return_to_v86(Bit32u new_eip, Bit32u raw_cs_selector, void -BX_CPU_C::stack_return_from_v86(BxInstruction_t *i) +BX_CPU_C::stack_return_from_v86(bxInstruction_c *i) { if (BX_CPU_THIS_PTR get_IOPL() != 3) { // trap to virtual 8086 monitor diff --git a/bochs/fpu/fpu.cc b/bochs/fpu/fpu.cc index cb7dd9651..99fae9a72 100644 --- a/bochs/fpu/fpu.cc +++ b/bochs/fpu/fpu.cc @@ -39,7 +39,7 @@ void -BX_CPU_C::ESC0(BxInstruction_t *i) +BX_CPU_C::ESC0(bxInstruction_c *i) { if ( BX_CPU_THIS_PTR cr0.em || BX_CPU_THIS_PTR cr0.ts ) { exception(BX_NM_EXCEPTION, 0, 0); @@ -52,7 +52,7 @@ BX_CPU_C::ESC0(BxInstruction_t *i) } void -BX_CPU_C::ESC1(BxInstruction_t *i) +BX_CPU_C::ESC1(bxInstruction_c *i) { if ( BX_CPU_THIS_PTR cr0.em || BX_CPU_THIS_PTR cr0.ts ) { exception(BX_NM_EXCEPTION, 0, 0); @@ -65,7 +65,7 @@ BX_CPU_C::ESC1(BxInstruction_t *i) } void -BX_CPU_C::ESC2(BxInstruction_t *i) +BX_CPU_C::ESC2(bxInstruction_c *i) { if ( BX_CPU_THIS_PTR cr0.em || BX_CPU_THIS_PTR cr0.ts ) { exception(BX_NM_EXCEPTION, 0, 0); @@ -78,7 +78,7 @@ BX_CPU_C::ESC2(BxInstruction_t *i) } void -BX_CPU_C::ESC3(BxInstruction_t *i) +BX_CPU_C::ESC3(bxInstruction_c *i) { if ( BX_CPU_THIS_PTR cr0.em || BX_CPU_THIS_PTR cr0.ts ) { exception(BX_NM_EXCEPTION, 0, 0); @@ -95,7 +95,7 @@ BX_CPU_C::ESC3(BxInstruction_t *i) } void -BX_CPU_C::ESC4(BxInstruction_t *i) +BX_CPU_C::ESC4(bxInstruction_c *i) { if ( BX_CPU_THIS_PTR cr0.em || BX_CPU_THIS_PTR cr0.ts ) { exception(BX_NM_EXCEPTION, 0, 0); @@ -108,7 +108,7 @@ BX_CPU_C::ESC4(BxInstruction_t *i) } void -BX_CPU_C::ESC5(BxInstruction_t *i) +BX_CPU_C::ESC5(bxInstruction_c *i) { if ( BX_CPU_THIS_PTR cr0.em || BX_CPU_THIS_PTR cr0.ts ) { exception(BX_NM_EXCEPTION, 0, 0); @@ -121,7 +121,7 @@ BX_CPU_C::ESC5(BxInstruction_t *i) } void -BX_CPU_C::ESC6(BxInstruction_t *i) +BX_CPU_C::ESC6(bxInstruction_c *i) { if ( BX_CPU_THIS_PTR cr0.em || BX_CPU_THIS_PTR cr0.ts ) { exception(BX_NM_EXCEPTION, 0, 0); @@ -134,7 +134,7 @@ BX_CPU_C::ESC6(BxInstruction_t *i) } void -BX_CPU_C::ESC7(BxInstruction_t *i) +BX_CPU_C::ESC7(bxInstruction_c *i) { if ( BX_CPU_THIS_PTR cr0.em || BX_CPU_THIS_PTR cr0.ts ) { exception(BX_NM_EXCEPTION, 0, 0); @@ -147,7 +147,7 @@ BX_CPU_C::ESC7(BxInstruction_t *i) } void -BX_CPU_C::FWAIT(BxInstruction_t *i) +BX_CPU_C::FWAIT(bxInstruction_c *i) { #if BX_CPU_LEVEL < 3 // WAIT doesn't generate single steps on 8086. diff --git a/bochs/fpu/wmFPUemu_glue.cc b/bochs/fpu/wmFPUemu_glue.cc index f42fb8ebf..396ac8231 100644 --- a/bochs/fpu/wmFPUemu_glue.cc +++ b/bochs/fpu/wmFPUemu_glue.cc @@ -42,7 +42,7 @@ extern "C" { // Use this to hold a pointer to the instruction since // we can't pass this to the FPU emulation routines, which // will ultimately call routines here. -static BxInstruction_t *fpu_iptr = NULL; +static bxInstruction_c *fpu_iptr = NULL; static BX_CPU_C *fpu_cpu_ptr = NULL; i387_t *current_i387; @@ -67,7 +67,7 @@ BX_CPU_C::fpu_init(void) } void -BX_CPU_C::fpu_execute(BxInstruction_t *i) +BX_CPU_C::fpu_execute(bxInstruction_c *i) { fpu_addr_modes addr_modes; void *data_address; @@ -126,7 +126,7 @@ access_limit = 0xff; data_sel_off.offset = i->rm_addr; data_sel_off.selector = BX_CPU_THIS_PTR sregs[i->seg].selector.value; - math_emulate2(addr_modes, i->modrm, i->b1, data_address, + math_emulate2(addr_modes, i->modrm(), i->b1, data_address, data_sel_off, entry_sel_off); }