added atom n270 cpuid + small fixes
This commit is contained in:
Stanislav Shwartsman
parent
b889e91898
commit
075db389a9
@ -7,7 +7,7 @@ Bochs repository moved to the SVN version control !
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The option selects CPU configuration to emulate from pre-defined list
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of supported configurations. When this option is used, Bochs CPU emulation
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engine is automatically configured to emulate a specific real hardware CPU,
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including exact CPUID matching reference hardware. Check .bochrc example
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including exact CPUID matching reference hardware. Check .bochsrc example
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or read docs for list of supported configurations or more details.
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- Implemented Supervisor Mode Execution Protection (SMEP), the feature can
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be enabled using .bochsrc CPUID option.
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@ -131,7 +131,8 @@ CPUDB_OBJS = cpudb/corei7_sandy_bridge_2600K.o \
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cpudb/p4_prescott_celeron_336.o \
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cpudb/athlon64_clawhammer.o \
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cpudb/p3_katmai.o \
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cpudb/p4_willamette.o
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cpudb/p4_willamette.o \
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cpudb/atom_n270.o
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BX_INCLUDES = ../bochs.h ../config.h
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@ -840,3 +841,10 @@ cpudb/p4_willamette.o: cpudb/p4_willamette.@CPP_SUFFIX@ ../bochs.h ../config.h .
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cpuid.h crregs.h descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h \
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apic.h ../cpu/i387.h ../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h \
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../fpu/control_w.h ../cpu/xmm.h vmx.h stack.h cpudb/p4_willamette.h
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cpudb/atom_n270.o: cpudb/atom_n270.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h \
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../bx_debug/debug.h ../bxversion.h ../gui/siminterface.h \
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../gui/paramtree.h ../memory/memory.h ../pc_system.h ../plugin.h \
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../extplugin.h ../gui/gui.h ../instrument/stubs/instrument.h cpu.h \
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cpuid.h crregs.h descriptor.h instr.h ia_opcodes.h lazy_flags.h icache.h \
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apic.h ../cpu/i387.h ../fpu/softfloat.h ../fpu/tag_w.h ../fpu/status_w.h \
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../fpu/control_w.h ../cpu/xmm.h vmx.h stack.h cpudb/atom_n270.h
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@ -3468,7 +3468,6 @@ public: // for now...
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BX_SMF BX_CPP_INLINE int bx_cpuid_support_pae(void);
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BX_SMF BX_CPP_INLINE int bx_cpuid_support_pge(void);
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BX_SMF BX_CPP_INLINE int bx_cpuid_support_pse(void);
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BX_SMF BX_CPP_INLINE int bx_cpuid_support_pse36(void);
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BX_SMF BX_CPP_INLINE int bx_cpuid_support_mmx(void);
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BX_SMF BX_CPP_INLINE int bx_cpuid_support_sse(void);
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BX_SMF BX_CPP_INLINE int bx_cpuid_support_sep(void);
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@ -3968,11 +3967,6 @@ BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_pge(void)
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return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_PGE);
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}
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BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_pse36(void)
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{
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return (BX_CPU_THIS_PTR cpu_extensions_bitmask & BX_CPU_PSE36);
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}
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BX_CPP_INLINE int BX_CPU_C::bx_cpuid_support_mmx(void)
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{
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return (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_MMX);
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594
bochs/cpu/cpudb/atom_n270.cc
Normal file
594
bochs/cpu/cpudb/atom_n270.cc
Normal file
@ -0,0 +1,594 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2011 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#include "bochs.h"
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#include "cpu/cpu.h"
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#include "param_names.h"
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#include "atom_n270.h"
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#define LOG_THIS cpu->
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#if BX_CPU_LEVEL >= 6 && BX_SUPPORT_X86_64 == 0
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atom_n270_t::atom_n270_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
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{
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#if BX_SUPPORT_SMP
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nthreads = SIM->get_param_num(BXPN_CPU_NTHREADS)->get();
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ncores = SIM->get_param_num(BXPN_CPU_NCORES)->get();
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nprocessors = SIM->get_param_num(BXPN_CPU_NPROCESSORS)->get();
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#endif
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if (BX_SUPPORT_X86_64)
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BX_PANIC(("x86-64 should be disabled for Intel Atom N270 (Diamondville) configuration"));
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}
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void atom_n270_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const
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{
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static bx_bool cpuid_limit_winnt = SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get();
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if (cpuid_limit_winnt)
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if (function > 2 && function < 0x80000000) function = 2;
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switch(function) {
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case 0x80000000:
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get_ext_cpuid_leaf_0(leaf);
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return;
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case 0x80000001:
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get_ext_cpuid_leaf_1(leaf);
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return;
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case 0x80000002:
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case 0x80000003:
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case 0x80000004:
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get_ext_cpuid_brand_string_leaf(function, leaf);
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return;
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case 0x80000005:
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get_ext_cpuid_leaf_5(leaf);
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return;
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case 0x80000006:
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get_ext_cpuid_leaf_6(leaf);
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return;
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case 0x80000007:
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get_ext_cpuid_leaf_7(leaf);
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return;
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case 0x80000008:
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get_ext_cpuid_leaf_8(leaf);
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return;
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case 0x00000000:
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get_std_cpuid_leaf_0(leaf);
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return;
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case 0x00000001:
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get_std_cpuid_leaf_1(leaf);
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return;
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case 0x00000002:
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get_std_cpuid_leaf_2(leaf);
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return;
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case 0x00000003:
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get_std_cpuid_leaf_3(leaf);
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return;
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case 0x00000004:
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get_std_cpuid_leaf_4(subfunction, leaf);
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return;
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case 0x00000005:
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get_std_cpuid_leaf_5(leaf);
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return;
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case 0x00000006:
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get_std_cpuid_leaf_6(leaf);
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return;
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case 0x00000007:
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get_std_cpuid_leaf_7(subfunction, leaf);
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return;
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case 0x00000008:
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get_std_cpuid_leaf_8(leaf);
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return;
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case 0x00000009:
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get_std_cpuid_leaf_9(leaf);
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return;
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case 0x0000000A:
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default:
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get_std_cpuid_leaf_A(leaf);
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return;
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}
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}
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Bit32u atom_n270_t::get_isa_extensions_bitmask(void) const
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{
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return BX_CPU_X87 |
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BX_CPU_486 |
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BX_CPU_PENTIUM |
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BX_CPU_P6 |
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BX_CPU_MMX |
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BX_CPU_FXSAVE_FXRSTOR |
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BX_CPU_SYSENTER_SYSEXIT |
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BX_CPU_CLFLUSH |
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BX_CPU_SSE |
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BX_CPU_SSE2 |
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BX_CPU_SSE3 |
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BX_CPU_SSSE3 |
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#if BX_SUPPORT_MONITOR_MWAIT
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BX_CPU_MONITOR_MWAIT |
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#endif
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BX_CPU_MOVBE |
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}
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Bit32u atom_n270_t::get_cpu_extensions_bitmask(void) const
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{
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return BX_CPU_DEBUG_EXTENSIONS |
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BX_CPU_VME |
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BX_CPU_PSE |
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#if BX_PHY_ADDRESS_LONG
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BX_CPU_PSE36 |
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#endif
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BX_CPU_PAE |
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BX_CPU_PGE |
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BX_CPU_PAT_MTRR |
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BX_CPU_XAPIC;
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}
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// leaf 0x00000000 //
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void atom_n270_t::get_std_cpuid_leaf_0(cpuid_function_t *leaf) const
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{
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static const char* vendor_string = "GenuineIntel";
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// EAX: highest std function understood by CPUID
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// EBX: vendor ID string
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// EDX: vendor ID string
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// ECX: vendor ID string
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leaf->eax = 0xA;
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// CPUID vendor string (e.g. GenuineIntel, AuthenticAMD, CentaurHauls, ...)
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memcpy(&(leaf->ebx), vendor_string, 4);
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memcpy(&(leaf->edx), vendor_string + 4, 4);
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memcpy(&(leaf->ecx), vendor_string + 8, 4);
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#ifdef BX_BIG_ENDIAN
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leaf->ebx = bx_bswap32(leaf->ebx);
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leaf->ecx = bx_bswap32(leaf->ecx);
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leaf->edx = bx_bswap32(leaf->edx);
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#endif
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}
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// leaf 0x00000001 //
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void atom_n270_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf) const
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{
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// EAX: CPU Version Information
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// [3:0] Stepping ID
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// [7:4] Model: starts at 1
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// [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
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// [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved
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// [19:16] Extended Model
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// [27:20] Extended Family
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leaf->eax = 0x000106C2;
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// EBX:
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// [7:0] Brand ID
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// [15:8] CLFLUSH cache line size (value*8 = cache line size in bytes)
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// [23:16] Number of logical processors in one physical processor
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// [31:24] Local Apic ID
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#if BX_SUPPORT_SMP
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unsigned n_logical_processors = ncores*nthreads;
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#else
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unsigned n_logical_processors = 1;
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#endif
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leaf->ebx = ((CACHE_LINE_SIZE / 8) << 8) |
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(n_logical_processors << 16);
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#if BX_SUPPORT_APIC
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leaf->ebx |= ((cpu->get_apic_id() & 0xff) << 24);
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#endif
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// ECX: Extended Feature Flags
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// * [0:0] SSE3: SSE3 Instructions
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// [1:1] PCLMULQDQ Instruction support
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// * [2:2] DTES64: 64-bit DS area
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// * [3:3] MONITOR/MWAIT support
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// * [4:4] DS-CPL: CPL qualified debug store
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// [5:5] VMX: Virtual Machine Technology
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// [6:6] SMX: Secure Virtual Machine Technology
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// * [7:7] EST: Enhanced Intel SpeedStep Technology
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// * [8:8] TM2: Thermal Monitor 2
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// * [9:9] SSSE3: SSSE3 Instructions
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// [10:10] CNXT-ID: L1 context ID
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// [11:11] reserved
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// [12:12] FMA Instructions support
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// [13:13] CMPXCHG16B: CMPXCHG16B instruction support
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// * [14:14] xTPR update control
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// * [15:15] PDCM - Perfon and Debug Capability MSR
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// [16:16] reserved
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// [17:17] PCID: Process Context Identifiers
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// [18:18] DCA - Direct Cache Access
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// [19:19] SSE4.1 Instructions
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// [20:20] SSE4.2 Instructions
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// [21:21] X2APIC
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// * [22:22] MOVBE instruction
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// [23:23] POPCNT instruction
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// [24:24] TSC Deadline
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// [25:25] AES Instructions
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// [26:26] XSAVE extensions support
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// [27:27] OSXSAVE support
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// [28:28] AVX extensions support
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// [29:29] AVX F16C - Float16 conversion support
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// [30:30] RDRAND instruction
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// [31:31] reserved
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leaf->ecx = BX_CPUID_EXT_SSE3 |
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BX_CPUID_EXT_DTES64 |
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#if BX_SUPPORT_MONITOR_MWAIT
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BX_CPUID_EXT_MONITOR_MWAIT |
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#endif
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BX_CPUID_EXT_DS_CPL |
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BX_CPUID_EXT_EST |
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BX_CPUID_EXT_THERMAL_MONITOR2 |
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BX_CPUID_EXT_SSSE3 |
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BX_CPUID_EXT_xTPR |
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BX_CPUID_EXT_PDCM |
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BX_CPUID_EXT_MOVBE;
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// EDX: Standard Feature Flags
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// * [0:0] FPU on chip
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// * [1:1] VME: Virtual-8086 Mode enhancements
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// * [2:2] DE: Debug Extensions (I/O breakpoints)
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// * [3:3] PSE: Page Size Extensions
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// * [4:4] TSC: Time Stamp Counter
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// * [5:5] MSR: RDMSR and WRMSR support
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// * [6:6] PAE: Physical Address Extensions
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// * [7:7] MCE: Machine Check Exception
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// * [8:8] CXS: CMPXCHG8B instruction
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// * [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// * [11:11] SYSENTER/SYSEXIT support
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// * [12:12] MTRR: Memory Type Range Reg
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// * [13:13] PGE/PTE Global Bit
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// * [14:14] MCA: Machine Check Architecture
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// * [15:15] CMOV: Cond Mov/Cmp Instructions
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// * [16:16] PAT: Page Attribute Table
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// - [17:17] PSE-36: Physical Address Extensions
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// [18:18] PSN: Processor Serial Number
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// * [19:19] CLFLUSH: CLFLUSH Instruction support
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// [20:20] Reserved
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// * [21:21] DS: Debug Store
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// * [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
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// * [23:23] MMX Technology
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// * [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// * [25:25] SSE: SSE Extensions
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// * [26:26] SSE2: SSE2 Extensions
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// * [27:27] Self Snoop
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// * [28:28] Hyper Threading Technology
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// * [29:29] TM: Thermal Monitor
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// [30:30] Reserved
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// * [31:31] PBE: Pending Break Enable
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leaf->edx = BX_CPUID_STD_X87 |
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BX_CPUID_STD_VME |
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BX_CPUID_STD_DEBUG_EXTENSIONS |
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BX_CPUID_STD_PSE |
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BX_CPUID_STD_TSC |
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BX_CPUID_STD_MSR |
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BX_CPUID_STD_PAE |
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BX_CPUID_STD_MCE |
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BX_CPUID_STD_CMPXCHG8B |
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BX_CPUID_STD_SYSENTER_SYSEXIT |
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BX_CPUID_STD_MTRR |
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BX_CPUID_STD_GLOBAL_PAGES |
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BX_CPUID_STD_MCA |
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BX_CPUID_STD_CMOV |
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BX_CPUID_STD_PAT |
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#if BX_PHY_ADDRESS_LONG
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BX_CPUID_STD_PSE36 |
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#endif
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BX_CPUID_STD_CLFLUSH |
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BX_CPUID_STD_DEBUG_STORE |
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BX_CPUID_STD_ACPI |
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BX_CPUID_STD_MMX |
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BX_CPUID_STD_FXSAVE_FXRSTOR |
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BX_CPUID_STD_SSE |
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BX_CPUID_STD_SSE2 |
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BX_CPUID_STD_SELF_SNOOP |
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BX_CPUID_STD_HT |
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BX_CPUID_STD_THERMAL_MONITOR |
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BX_CPUID_STD_PBE;
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#if BX_SUPPORT_APIC
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// if MSR_APICBASE APIC Global Enable bit has been cleared,
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// the CPUID feature flag for the APIC is set to 0.
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if (cpu->msr.apicbase & 0x800)
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leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip
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#endif
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}
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// leaf 0x00000002 //
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void atom_n270_t::get_std_cpuid_leaf_2(cpuid_function_t *leaf) const
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{
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// CPUID function 0x00000002 - Cache and TLB Descriptors
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leaf->eax = 0x4FBA5901;
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leaf->ebx = 0x0E3080C0;
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leaf->ecx = 0x00000000;
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leaf->edx = 0x00000000;
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}
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// leaf 0x00000003 //
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void core2_extreme_x9770_t::get_std_cpuid_leaf_3(cpuid_function_t *leaf) const
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{
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// CPUID function 0x00000003 - Processor Serial Number
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leaf->eax = 0;
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leaf->ebx = 0;
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leaf->ecx = 0;
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leaf->edx = 0;
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}
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// leaf 0x00000004 //
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void core2_extreme_x9770_t::get_std_cpuid_leaf_4(Bit32u subfunction, cpuid_function_t *leaf) const
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{
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// CPUID function 0x00000004 - Deterministic Cache Parameters
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switch(subfunction) {
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case 0:
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leaf->eax = 0x00004121;
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leaf->ebx = 0x0140003F;
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leaf->ecx = 0x0000003F;
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leaf->edx = 0x00000001;
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return;
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case 1:
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leaf->eax = 0x00004122;
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leaf->ebx = 0x01C0003F;
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leaf->ecx = 0x0000003F;
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leaf->edx = 0x00000001;
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return;
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case 2:
|
||||
leaf->eax = 0x00004143;
|
||||
leaf->ebx = 0x01C0003F;
|
||||
leaf->ecx = 0x000003FF;
|
||||
leaf->edx = 0x00000001;
|
||||
return;
|
||||
default:
|
||||
leaf->eax = 0;
|
||||
leaf->ebx = 0;
|
||||
leaf->ecx = 0;
|
||||
leaf->edx = 0;
|
||||
}
|
||||
}
|
||||
|
||||
// leaf 0x00000005 //
|
||||
void core2_extreme_x9770_t::get_std_cpuid_leaf_5(cpuid_function_t *leaf) const
|
||||
{
|
||||
// CPUID function 0x00000005 - MONITOR/MWAIT Leaf
|
||||
|
||||
#if BX_SUPPORT_MONITOR_MWAIT
|
||||
// EAX - Smallest monitor-line size in bytes
|
||||
// EBX - Largest monitor-line size in bytes
|
||||
// ECX -
|
||||
// [31:2] - reserved
|
||||
// [1:1] - exit MWAIT even with EFLAGS.IF = 0
|
||||
// [0:0] - MONITOR/MWAIT extensions are supported
|
||||
// EDX - Reserved
|
||||
leaf->eax = CACHE_LINE_SIZE;
|
||||
leaf->ebx = CACHE_LINE_SIZE;
|
||||
leaf->ecx = 3;
|
||||
leaf->edx = 0;
|
||||
#else
|
||||
leaf->eax = 0;
|
||||
leaf->ebx = 0;
|
||||
leaf->ecx = 0;
|
||||
leaf->edx = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
// leaf 0x00000006 //
|
||||
void core2_extreme_x9770_t::get_std_cpuid_leaf_6(cpuid_function_t *leaf) const
|
||||
{
|
||||
// CPUID function 0x00000006 - Thermal and Power Management Leaf
|
||||
leaf->eax = 0x00000001;
|
||||
leaf->ebx = 0x00000002;
|
||||
leaf->ecx = 0x00000001;
|
||||
leaf->edx = 0x00000000;
|
||||
}
|
||||
|
||||
// leaf 0x00000007 //
|
||||
void core2_extreme_x9770_t::get_std_cpuid_leaf_7(Bit32u subfunction, cpuid_function_t *leaf) const
|
||||
{
|
||||
leaf->eax = 0; /* leaf 7 not supported */
|
||||
leaf->ebx = 0;
|
||||
leaf->ecx = 0;
|
||||
leaf->edx = 0;
|
||||
}
|
||||
|
||||
// leaf 0x00000008 //
|
||||
void core2_extreme_x9770_t::get_std_cpuid_leaf_8(cpuid_function_t *leaf) const
|
||||
{
|
||||
// CPUID function 0x00000008 - reserved
|
||||
leaf->eax = 0;
|
||||
leaf->ebx = 0;
|
||||
leaf->ecx = 0;
|
||||
leaf->edx = 0;
|
||||
}
|
||||
|
||||
// leaf 0x00000009 //
|
||||
void core2_extreme_x9770_t::get_std_cpuid_leaf_9(cpuid_function_t *leaf) const
|
||||
{
|
||||
// CPUID function 0x00000009 - Direct Cache Access Information
|
||||
leaf->eax = 0;
|
||||
leaf->ebx = 0;
|
||||
leaf->ecx = 0;
|
||||
leaf->edx = 0;
|
||||
}
|
||||
|
||||
// leaf 0x0000000A //
|
||||
void core2_extreme_x9770_t::get_std_cpuid_leaf_A(cpuid_function_t *leaf) const
|
||||
{
|
||||
// CPUID function 0x0000000A - Architectural Performance Monitoring Leaf
|
||||
leaf->eax = 0x07280203;
|
||||
leaf->ebx = 0x00000000;
|
||||
leaf->ecx = 0x00000000;
|
||||
leaf->edx = 0x00002501;
|
||||
|
||||
BX_INFO(("WARNING: Architectural Performance Monitoring is not implemented"));
|
||||
}
|
||||
|
||||
// leaf 0x80000000 //
|
||||
void core2_extreme_x9770_t::get_ext_cpuid_leaf_0(cpuid_function_t *leaf) const
|
||||
{
|
||||
// EAX: highest extended function understood by CPUID
|
||||
// EBX: reserved
|
||||
// EDX: reserved
|
||||
// ECX: reserved
|
||||
leaf->eax = 0x80000008;
|
||||
leaf->ebx = 0;
|
||||
leaf->edx = 0; // Reserved for Intel
|
||||
leaf->ecx = 0;
|
||||
}
|
||||
|
||||
// leaf 0x80000001 //
|
||||
void core2_extreme_x9770_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
|
||||
{
|
||||
// EAX: CPU Version Information (reserved for Intel)
|
||||
leaf->eax = 0;
|
||||
|
||||
// EBX: Brand ID (reserved for Intel)
|
||||
leaf->ebx = 0;
|
||||
|
||||
// ECX:
|
||||
// ? [0:0] LAHF/SAHF instructions support in 64-bit mode
|
||||
// [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD)
|
||||
// [2:2] SVM: Secure Virtual Machine (AMD)
|
||||
// [3:3] Extended APIC Space
|
||||
// [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
|
||||
// [5:5] LZCNT: LZCNT instruction support
|
||||
// [6:6] SSE4A: SSE4A Instructions support (deprecated?)
|
||||
// [7:7] Misaligned SSE support
|
||||
// [8:8] PREFETCHW: PREFETCHW instruction support
|
||||
// [9:9] OSVW: OS visible workarounds (AMD)
|
||||
// [11:10] reserved
|
||||
// [12:12] SKINIT support
|
||||
// [13:13] WDT: Watchdog timer support
|
||||
// [31:14] reserved
|
||||
|
||||
leaf->ecx = BX_CPUID_EXT2_LAHF_SAHF;
|
||||
|
||||
// EDX:
|
||||
// Many of the bits in EDX are the same as FN 0x00000001 [*] for AMD
|
||||
// [10:0] Reserved for Intel
|
||||
// [11:11] SYSCALL/SYSRET support
|
||||
// [19:12] Reserved for Intel
|
||||
// [20:20] No-Execute page protection
|
||||
// [25:21] Reserved
|
||||
// [26:26] 1G paging support
|
||||
// [27:27] Support RDTSCP Instruction
|
||||
// [28:28] Reserved
|
||||
// [29:29] Long Mode
|
||||
// [30:30] AMD 3DNow! Extensions
|
||||
// [31:31] AMD 3DNow! Instructions
|
||||
|
||||
leaf->edx = 0;
|
||||
}
|
||||
|
||||
// leaf 0x80000002 //
|
||||
// leaf 0x80000003 //
|
||||
// leaf 0x80000004 //
|
||||
void core2_extreme_x9770_t::get_ext_cpuid_brand_string_leaf(Bit32u function, cpuid_function_t *leaf) const
|
||||
{
|
||||
// CPUID function 0x800000002-0x800000004 - Processor Name String Identifier
|
||||
static const char* brand_string = " Intel(R) Atom(TM) CPU N270 @ 1.60GHz";
|
||||
|
||||
switch(function) {
|
||||
case 0x80000002:
|
||||
memcpy(&(leaf->eax), brand_string , 4);
|
||||
memcpy(&(leaf->ebx), brand_string + 4, 4);
|
||||
memcpy(&(leaf->ecx), brand_string + 8, 4);
|
||||
memcpy(&(leaf->edx), brand_string + 12, 4);
|
||||
break;
|
||||
case 0x80000003:
|
||||
memcpy(&(leaf->eax), brand_string + 16, 4);
|
||||
memcpy(&(leaf->ebx), brand_string + 20, 4);
|
||||
memcpy(&(leaf->ecx), brand_string + 24, 4);
|
||||
memcpy(&(leaf->edx), brand_string + 28, 4);
|
||||
break;
|
||||
case 0x80000004:
|
||||
memcpy(&(leaf->eax), brand_string + 32, 4);
|
||||
memcpy(&(leaf->ebx), brand_string + 36, 4);
|
||||
memcpy(&(leaf->ecx), brand_string + 40, 4);
|
||||
memcpy(&(leaf->edx), brand_string + 44, 4);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef BX_BIG_ENDIAN
|
||||
leaf->eax = bx_bswap32(leaf->eax);
|
||||
leaf->ebx = bx_bswap32(leaf->ebx);
|
||||
leaf->ecx = bx_bswap32(leaf->ecx);
|
||||
leaf->edx = bx_bswap32(leaf->edx);
|
||||
#endif
|
||||
}
|
||||
|
||||
// leaf 0x80000005 //
|
||||
void core2_extreme_x9770_t::get_ext_cpuid_leaf_5(cpuid_function_t *leaf) const
|
||||
{
|
||||
// CPUID function 0x800000005 - L1 Cache and TLB Identifiers
|
||||
leaf->eax = 0;
|
||||
leaf->ebx = 0;
|
||||
leaf->ecx = 0; // reserved for Intel
|
||||
leaf->edx = 0;
|
||||
}
|
||||
|
||||
// leaf 0x80000006 //
|
||||
void core2_extreme_x9770_t::get_ext_cpuid_leaf_6(cpuid_function_t *leaf) const
|
||||
{
|
||||
// CPUID function 0x800000006 - L2 Cache and TLB Identifiers
|
||||
leaf->eax = 0x00000000;
|
||||
leaf->ebx = 0x00000000;
|
||||
leaf->ecx = 0x02008040;
|
||||
leaf->edx = 0x00000000;
|
||||
}
|
||||
|
||||
// leaf 0x80000007 //
|
||||
void core2_extreme_x9770_t::get_ext_cpuid_leaf_7(cpuid_function_t *leaf) const
|
||||
{
|
||||
// CPUID function 0x800000007 - Advanced Power Management
|
||||
leaf->eax = 0;
|
||||
leaf->ebx = 0;
|
||||
leaf->ecx = 0;
|
||||
leaf->edx = 0;
|
||||
}
|
||||
|
||||
// leaf 0x80000008 //
|
||||
void core2_extreme_x9770_t::get_ext_cpuid_leaf_8(cpuid_function_t *leaf) const
|
||||
{
|
||||
// virtual & phys address size in low 2 bytes.
|
||||
leaf->eax = BX_PHY_ADDRESS_WIDTH | (BX_LIN_ADDRESS_WIDTH << 8); // physical address should be 32-bit, no PSE-36
|
||||
leaf->ebx = 0;
|
||||
leaf->ecx = 0; // Reserved, undefined
|
||||
leaf->edx = 0;
|
||||
}
|
||||
|
||||
void atom_n270_t::dump_cpuid(void) const
|
||||
{
|
||||
struct cpuid_function_t leaf;
|
||||
unsigned n;
|
||||
|
||||
for (n=0; n<=0xA; n++) {
|
||||
get_cpuid_leaf(n, 0x00000000, &leaf);
|
||||
BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", n, leaf.eax, leaf.ebx, leaf.ecx, leaf.edx));
|
||||
}
|
||||
|
||||
for (n=0x80000000; n<=0x80000008; n++) {
|
||||
get_cpuid_leaf(n, 0x00000000, &leaf);
|
||||
BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", n, leaf.eax, leaf.ebx, leaf.ecx, leaf.edx));
|
||||
}
|
||||
}
|
||||
|
||||
bx_cpuid_t *create_atom_n270_cpuid(BX_CPU_C *cpu) { return new atom_n270_t(cpu); }
|
||||
|
||||
#endif
|
||||
79
bochs/cpu/cpudb/atom_n270.h
Normal file
79
bochs/cpu/cpudb/atom_n270.h
Normal file
@ -0,0 +1,79 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id$
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2011 Stanislav Shwartsman
|
||||
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
|
||||
//
|
||||
// This library is free software; you can redistribute it and/or
|
||||
// modify it under the terms of the GNU Lesser General Public
|
||||
// License as published by the Free Software Foundation; either
|
||||
// version 2 of the License, or (at your option) any later version.
|
||||
//
|
||||
// This library is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
// Lesser General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU Lesser General Public
|
||||
// License along with this library; if not, write to the Free Software
|
||||
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef BX_ATOM_N270_CPUID_DEFINITIONS_H
|
||||
#define BX_ATOM_N270_CPUID_DEFINITIONS_H
|
||||
|
||||
#if BX_CPU_LEVEL >= 6 && BX_SUPPORT_X86_64 == 0
|
||||
|
||||
#include "cpu/cpuid.h"
|
||||
|
||||
class atom_n270_t : public bx_cpuid_t {
|
||||
public:
|
||||
atom_n270_t(BX_CPU_C *cpu);
|
||||
virtual ~atom_n270_t() {}
|
||||
|
||||
// return CPU name
|
||||
virtual const char *get_name(void) const { return "atom_n270"; }
|
||||
|
||||
virtual Bit32u get_isa_extensions_bitmask(void) const;
|
||||
virtual Bit32u get_cpu_extensions_bitmask(void) const;
|
||||
|
||||
virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const;
|
||||
|
||||
virtual void dump_cpuid(void) const;
|
||||
|
||||
private:
|
||||
#if BX_SUPPORT_SMP
|
||||
unsigned nprocessors;
|
||||
unsigned ncores;
|
||||
unsigned nthreads;
|
||||
#endif
|
||||
|
||||
void get_std_cpuid_leaf_0(cpuid_function_t *leaf) const;
|
||||
void get_std_cpuid_leaf_1(cpuid_function_t *leaf) const;
|
||||
void get_std_cpuid_leaf_2(cpuid_function_t *leaf) const;
|
||||
void get_std_cpuid_leaf_3(cpuid_function_t *leaf) const;
|
||||
void get_std_cpuid_leaf_4(Bit32u subfunction, cpuid_function_t *leaf) const;
|
||||
void get_std_cpuid_leaf_5(cpuid_function_t *leaf) const;
|
||||
void get_std_cpuid_leaf_6(cpuid_function_t *leaf) const;
|
||||
void get_std_cpuid_leaf_7(Bit32u subfunction, cpuid_function_t *leaf) const;
|
||||
void get_std_cpuid_leaf_8(cpuid_function_t *leaf) const;
|
||||
void get_std_cpuid_leaf_9(cpuid_function_t *leaf) const;
|
||||
void get_std_cpuid_leaf_A(cpuid_function_t *leaf) const;
|
||||
|
||||
void get_ext_cpuid_leaf_0(cpuid_function_t *leaf) const;
|
||||
void get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const;
|
||||
void get_ext_cpuid_brand_string_leaf(Bit32u function, cpuid_function_t *leaf) const;
|
||||
void get_ext_cpuid_leaf_5(cpuid_function_t *leaf) const;
|
||||
void get_ext_cpuid_leaf_6(cpuid_function_t *leaf) const;
|
||||
void get_ext_cpuid_leaf_7(cpuid_function_t *leaf) const;
|
||||
void get_ext_cpuid_leaf_8(cpuid_function_t *leaf) const;
|
||||
};
|
||||
|
||||
extern bx_cpuid_t *create_atom_n270_cpuid(BX_CPU_C *cpu);
|
||||
|
||||
#endif // BX_CPU_LEVEL >= 6 && BX_SUPPORT_X86_64 == 0
|
||||
|
||||
#endif
|
||||
|
||||
144
bochs/cpu/cpudb/atom_n270.txt
Normal file
144
bochs/cpu/cpudb/atom_n270.txt
Normal file
@ -0,0 +1,144 @@
|
||||
CPU-Z TXT Report
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
Binaries
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
CPU-Z version 1.56
|
||||
|
||||
Processors
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
Number of processors 1
|
||||
Number of threads 2
|
||||
|
||||
APICs
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
Processor 0
|
||||
-- Core 0
|
||||
-- Thread 0 0
|
||||
-- Thread 1 1
|
||||
|
||||
Processors Information
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
Processor 1 ID = 0
|
||||
Number of cores 1 (max 1)
|
||||
Number of threads 2 (max 2)
|
||||
Name Intel Atom N270
|
||||
Codename Diamondville
|
||||
Specification Intel(R) Atom(TM) CPU N270 @ 1.60GHz
|
||||
Package (platform ID) Socket 437 FCBGA8 (0x2)
|
||||
CPUID 6.C.2
|
||||
Extended CPUID 6.1C
|
||||
Core Stepping C0
|
||||
Technology 45 nm
|
||||
Core Speed 798.1 MHz
|
||||
Multiplier x FSB 6.0 x 133.0 MHz
|
||||
Rated Bus speed 532.1 MHz
|
||||
Stock frequency 1600 MHz
|
||||
Instructions sets MMX, SSE, SSE2, SSE3, SSSE3
|
||||
L1 Data cache 24 KBytes, 6-way set associative, 64-byte line size
|
||||
L1 Instruction cache 32 KBytes, 8-way set associative, 64-byte line size
|
||||
L2 cache 512 KBytes, 8-way set associative, 64-byte line size
|
||||
FID/VID Control yes
|
||||
FID range 6.0x - 12.0x
|
||||
Max VID 1.113 V
|
||||
|
||||
|
||||
|
||||
Thread dumps
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
CPU Thread 0
|
||||
APIC ID 0
|
||||
Topology Processor ID 0, Core ID 0, Thread ID 0
|
||||
Type 01010001h
|
||||
Max CPUID level 0000000Ah
|
||||
Max CPUID ext. level 80000008h
|
||||
Cache descriptor Level 1, D, 24 KB, 2 thread(s)
|
||||
Cache descriptor Level 1, I, 32 KB, 2 thread(s)
|
||||
Cache descriptor Level 2, U, 512 KB, 2 thread(s)
|
||||
|
||||
CPUID
|
||||
0x00000000 0x0000000A 0x756E6547 0x6C65746E 0x49656E69
|
||||
0x00000001 0x000106C2 0x00020800 0x0040C39D 0xBFE9FBFF
|
||||
0x00000002 0x4FBA5901 0x0E3080C0 0x00000000 0x00000000
|
||||
0x00000003 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x00000004 0x00004121 0x0140003F 0x0000003F 0x00000001
|
||||
0x00000004 0x00004122 0x01C0003F 0x0000003F 0x00000001
|
||||
0x00000004 0x00004143 0x01C0003F 0x000003FF 0x00000001
|
||||
0x00000005 0x00000040 0x00000040 0x00000003 0x00020220
|
||||
0x00000006 0x00000001 0x00000002 0x00000001 0x00000000
|
||||
0x00000007 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x00000008 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x00000009 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x0000000A 0x07280203 0x00000000 0x00000000 0x00002501
|
||||
0x80000000 0x80000008 0x00000000 0x00000000 0x00000000
|
||||
0x80000001 0x00000000 0x00000000 0x00000001 0x00000000
|
||||
0x80000002 0x20202020 0x20202020 0x746E4920 0x52286C65
|
||||
0x80000003 0x74412029 0x54286D6F 0x4320294D 0x4E205550
|
||||
0x80000004 0x20303732 0x20402020 0x30362E31 0x007A4847
|
||||
0x80000005 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x80000006 0x00000000 0x00000000 0x02008040 0x00000000
|
||||
0x80000007 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x80000008 0x00002020 0x00000000 0x00000000 0x00000000
|
||||
|
||||
MSR 0x0000001B 0x00000000 0xFEE00900
|
||||
MSR 0x00000017 0x00080000 0x9024AC20
|
||||
MSR 0x000000CD 0x00000000 0x00000111
|
||||
MSR 0x0000003F 0x00000000 0x00000000
|
||||
MSR 0x000000CE 0x200F0C00 0x4B4B0000
|
||||
MSR 0x000001A0 0x00000007 0x64950480
|
||||
MSR 0x000000EE 0x00000000 0x02F90002
|
||||
MSR 0x0000011E 0x00000000 0x7E00011F
|
||||
MSR 0x0000019C 0x00000000 0x88380000
|
||||
MSR 0x00000198 0x060F0C20 0x06000C20
|
||||
MSR 0x00000199 0x00000000 0x00000C20
|
||||
|
||||
CPU Thread 1
|
||||
APIC ID 1
|
||||
Topology Processor ID 0, Core ID 0, Thread ID 1
|
||||
Type 01010001h
|
||||
Max CPUID level 0000000Ah
|
||||
Max CPUID ext. level 80000008h
|
||||
Cache descriptor Level 1, D, 24 KB, 2 thread(s)
|
||||
Cache descriptor Level 1, I, 32 KB, 2 thread(s)
|
||||
Cache descriptor Level 2, U, 512 KB, 2 thread(s)
|
||||
|
||||
CPUID
|
||||
0x00000000 0x0000000A 0x756E6547 0x6C65746E 0x49656E69
|
||||
0x00000001 0x000106C2 0x01020800 0x0040C39D 0xBFE9FBFF
|
||||
0x00000002 0x4FBA5901 0x0E3080C0 0x00000000 0x00000000
|
||||
0x00000003 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x00000004 0x00004121 0x0140003F 0x0000003F 0x00000001
|
||||
0x00000004 0x00004122 0x01C0003F 0x0000003F 0x00000001
|
||||
0x00000004 0x00004143 0x01C0003F 0x000003FF 0x00000001
|
||||
0x00000005 0x00000040 0x00000040 0x00000003 0x00020220
|
||||
0x00000006 0x00000001 0x00000002 0x00000001 0x00000000
|
||||
0x00000007 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x00000008 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x00000009 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x0000000A 0x07280203 0x00000000 0x00000000 0x00002501
|
||||
0x80000000 0x80000008 0x00000000 0x00000000 0x00000000
|
||||
0x80000001 0x00000000 0x00000000 0x00000001 0x00000000
|
||||
0x80000002 0x20202020 0x20202020 0x746E4920 0x52286C65
|
||||
0x80000003 0x74412029 0x54286D6F 0x4320294D 0x4E205550
|
||||
0x80000004 0x20303732 0x20402020 0x30362E31 0x007A4847
|
||||
0x80000005 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x80000006 0x00000000 0x00000000 0x02008040 0x00000000
|
||||
0x80000007 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
0x80000008 0x00002020 0x00000000 0x00000000 0x00000000
|
||||
|
||||
MSR 0x0000001B 0x00000000 0xFEE00800
|
||||
MSR 0x00000017 0x00080000 0x9024AC20
|
||||
MSR 0x000000CD 0x00000000 0x00000111
|
||||
MSR 0x0000003F 0x00000000 0x00000000
|
||||
MSR 0x000000CE 0x200F0C00 0x4B4B0000
|
||||
MSR 0x000001A0 0x00000007 0x64950480
|
||||
MSR 0x000000EE 0x00000000 0x02F90002
|
||||
MSR 0x0000011E 0x00000000 0x7E00011F
|
||||
MSR 0x0000019C 0x00000000 0x88370000
|
||||
MSR 0x00000198 0x060F0C20 0x06000C20
|
||||
MSR 0x00000199 0x00000000 0x00000C20
|
||||
@ -76,7 +76,9 @@ Bit32u p3_katmai_t::get_cpu_extensions_bitmask(void) const
|
||||
BX_CPU_PSE |
|
||||
BX_CPU_PAE |
|
||||
BX_CPU_PGE |
|
||||
#if BX_PHY_ADDRESS_LONG
|
||||
BX_CPU_PSE36 |
|
||||
#endif
|
||||
BX_CPU_PAT_MTRR;
|
||||
}
|
||||
|
||||
@ -165,7 +167,9 @@ void p3_katmai_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf) const
|
||||
BX_CPUID_STD_MCA |
|
||||
BX_CPUID_STD_CMOV |
|
||||
BX_CPUID_STD_PAT |
|
||||
#if BX_PHY_ADDRESS_LONG
|
||||
BX_CPUID_STD_PSE36 |
|
||||
#endif
|
||||
BX_CPUID_STD_MMX |
|
||||
BX_CPUID_STD_FXSAVE_FXRSTOR |
|
||||
BX_CPUID_STD_SSE;
|
||||
|
||||
@ -90,7 +90,9 @@ Bit32u p4_willamette_t::get_cpu_extensions_bitmask(void) const
|
||||
BX_CPU_PSE |
|
||||
BX_CPU_PAE |
|
||||
BX_CPU_PGE |
|
||||
#if BX_PHY_ADDRESS_LONG
|
||||
BX_CPU_PSE36 |
|
||||
#endif
|
||||
BX_CPU_PAT_MTRR |
|
||||
BX_CPU_XAPIC;
|
||||
}
|
||||
@ -197,7 +199,9 @@ void p4_willamette_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf) const
|
||||
BX_CPUID_STD_MCA |
|
||||
BX_CPUID_STD_CMOV |
|
||||
BX_CPUID_STD_PAT |
|
||||
#if BX_PHY_ADDRESS_LONG
|
||||
BX_CPUID_STD_PSE36 |
|
||||
#endif
|
||||
BX_CPUID_STD_CLFLUSH |
|
||||
BX_CPUID_STD_DEBUG_STORE |
|
||||
BX_CPUID_STD_ACPI |
|
||||
|
||||
@ -26,6 +26,7 @@ bx_define_cpudb(bx_generic)
|
||||
#if BX_SUPPORT_X86_64 == 0
|
||||
bx_define_cpudb(p3_katmai)
|
||||
bx_define_cpudb(p4_willamette)
|
||||
bx_define_cpudb(atom_n270)
|
||||
#else
|
||||
bx_define_cpudb(p4_prescott_celeron_336)
|
||||
bx_define_cpudb(athlon64_clawhammer)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user