mirror of https://github.com/bochs-emu/Bochs
- Zwane sent another version to the list at
Mon, 25 Mar 2002 11:47:38 +0200 (SAST) which should correct the compile problems when apic is disabled.
This commit is contained in:
Bryce Denney
parent
e6c82a961a
commit
03cd6fa9ad
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@ -1,3 +1,7 @@
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Zwane sent another version to the list at
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Mon, 25 Mar 2002 11:47:38 +0200 (SAST)
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which should correct the compile problems when apic is disabled.
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Updated so that it applies cleanly in cvs as of March 25. -Bryce
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Notes by Bryce:
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@ -29,22 +33,17 @@ Cheers,
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PS this is just the infrastructure, i haven't done all the registers, most
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notably the MTRR stuff.
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Index: cpu/apic.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/apic.cc,v
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retrieving revision 1.12
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diff -u -r1.12 apic.cc
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--- cpu/apic.cc 25 Mar 2002 01:58:34 -0000 1.12
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+++ cpu/apic.cc 25 Mar 2002 09:32:58 -0000
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@@ -34,6 +34,14 @@
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diff -ur /tmp/bochs-1.4.pre2/cpu/apic.cc bochs-1.4.pre2/cpu/apic.cc
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--- /tmp/bochs-1.4.pre2/cpu/apic.cc Wed Oct 3 15:10:38 2001
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+++ bochs-1.4.pre2/cpu/apic.cc Mon Mar 25 12:06:48 2002
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@@ -27,6 +27,14 @@
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{
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}
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+void bx_local_apic_c::update_msr_apicbase(Bit32u newbase)
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+{
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+ Bit64u val64;
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+ val64 = newbase << 12; /* push the APIC base address to bits 12:31 */
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+ val64 = newbase << 12; /* push the APIC base address to bits 12:35 */
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+ val64 += cpu->msr.apicbase & 0x0900; /* don't modify other apicbase or reserved bits */
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+ cpu->msr.apicbase = val64;
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+}
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@ -52,7 +51,7 @@ diff -u -r1.12 apic.cc
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void bx_generic_apic_c::set_base (Bit32u newbase)
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{
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BX_INFO(("relocate APIC id=%d to %8x", id, newbase));
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@@ -291,7 +299,8 @@
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@@ -247,7 +255,8 @@
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BX_INFO(("local apic in %s initializing",
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(cpu && cpu->name) ? cpu->name : "?"));
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// default address for a local APIC, can be moved
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@ -61,14 +60,10 @@ diff -u -r1.12 apic.cc
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+ update_msr_apicbase(base_addr);
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err_status = 0;
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log_dest = 0;
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dest_format = 0xf;
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Index: cpu/cpu.h
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
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retrieving revision 1.16
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diff -u -r1.16 cpu.h
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--- cpu/cpu.h 25 Mar 2002 01:58:34 -0000 1.16
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+++ cpu/cpu.h 25 Mar 2002 09:33:01 -0000
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dest_format = 0xff;
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diff -ur /tmp/bochs-1.4.pre2/cpu/cpu.h bochs-1.4.pre2/cpu/cpu.h
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--- /tmp/bochs-1.4.pre2/cpu/cpu.h Wed Oct 3 21:53:48 2001
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+++ bochs-1.4.pre2/cpu/cpu.h Mon Mar 25 12:08:32 2002
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@@ -195,9 +195,43 @@
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#define BX_MF_EXCEPTION 16
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#define BX_AC_EXCEPTION 17
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@ -135,15 +130,16 @@ diff -u -r1.16 cpu.h
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typedef struct { /* bx_selector_t */
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Bit16u value; /* the 16bit value of the selector */
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@@ -528,6 +574,7 @@
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Bit8u id;
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#define APIC_UNKNOWN_ID 0xff
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#define APIC_VERSION_ID 0x00170011 // same version as 82093 IOAPIC
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+#define APIC_BASE_ADDR 0xfee00000 // default APIC address
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public:
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bx_generic_apic_c ();
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virtual ~bx_generic_apic_c ();
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@@ -578,7 +625,6 @@
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@@ -521,6 +567,8 @@
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APIC_TYPE_LOCAL_APIC
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} bx_apic_type_t;
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+#define APIC_BASE_ADDR 0xfee00000 // default APIC address
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+
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#if BX_SUPPORT_APIC
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class bx_generic_apic_c : public logfunctions {
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protected:
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@@ -577,7 +625,6 @@
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Bit32u timer_initial, timer_current, timer_divconf;
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Boolean timer_active; // internal state, not accessible from bus
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Bit32u timer_divide_counter, timer_divide_factor;
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@ -151,15 +147,15 @@ diff -u -r1.16 cpu.h
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Bit32u icr_high, icr_low;
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Bit32u err_status;
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#define APIC_ERR_ILLEGAL_ADDR 0x80
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@@ -618,6 +664,7 @@
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@@ -616,6 +663,7 @@
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Bit8u get_apr ();
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void periodic (Bit32u usec_delta);
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void set_divide_configuration (Bit32u value);
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+ virtual void update_msr_apicbase(Bit32u newaddr);
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virtual void set_arb_id (int newid);
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};
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@@ -756,6 +803,10 @@
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#define APIC_MAX_ID 16
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@@ -753,6 +801,10 @@
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Bit32u cr4;
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#endif
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@ -170,7 +166,7 @@ diff -u -r1.16 cpu.h
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// pointer to the address space that this processor uses.
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BX_MEM_C *mem;
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@@ -768,6 +819,8 @@
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@@ -765,6 +817,8 @@
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volatile Boolean async_event;
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volatile Boolean INTR;
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@ -179,13 +175,9 @@ diff -u -r1.16 cpu.h
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// for accessing registers by index number
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Bit16u *_16bit_base_reg[8];
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Bit16u *_16bit_index_reg[8];
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Index: cpu/init.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/init.cc,v
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retrieving revision 1.14
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diff -u -r1.14 init.cc
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--- cpu/init.cc 3 Oct 2001 13:10:37 -0000 1.14
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+++ cpu/init.cc 25 Mar 2002 09:33:02 -0000
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diff -ur /tmp/bochs-1.4.pre2/cpu/init.cc bochs-1.4.pre2/cpu/init.cc
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--- /tmp/bochs-1.4.pre2/cpu/init.cc Wed Oct 3 15:10:38 2001
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+++ bochs-1.4.pre2/cpu/init.cc Mon Mar 25 12:06:48 2002
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@@ -554,7 +554,11 @@
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BX_CPU_THIS_PTR cr4 = 0;
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#endif
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@ -213,13 +205,9 @@ diff -u -r1.14 init.cc
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BX_INFO(("CPU[%d] is an application processor. Halting until IPI.", apic_id));
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debug_trap |= 0x80000000;
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async_event = 1;
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Index: cpu/proc_ctrl.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/proc_ctrl.cc,v
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retrieving revision 1.17
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diff -u -r1.17 proc_ctrl.cc
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--- cpu/proc_ctrl.cc 18 Nov 2001 16:32:40 -0000 1.17
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+++ cpu/proc_ctrl.cc 25 Mar 2002 09:33:03 -0000
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diff -ur /tmp/bochs-1.4.pre2/cpu/proc_ctrl.cc bochs-1.4.pre2/cpu/proc_ctrl.cc
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--- /tmp/bochs-1.4.pre2/cpu/proc_ctrl.cc Sun Nov 18 18:32:40 2001
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+++ bochs-1.4.pre2/cpu/proc_ctrl.cc Mon Mar 25 12:06:48 2002
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@@ -1147,23 +1147,143 @@
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BX_CPU_C::RDMSR(BxInstruction_t *i)
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{
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@ -372,3 +360,13 @@ diff -u -r1.17 proc_ctrl.cc
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}
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#if BX_X86_DEBUGGER
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--
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rants : http://function.linuxpower.ca
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_______________________________________________
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bochs-developers mailing list
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bochs-developers@lists.sourceforge.net
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https://lists.sourceforge.net/lists/listinfo/bochs-developers
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