2011-07-31 22:43:46 +04:00
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/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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2017-03-13 22:44:14 +03:00
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// Copyright (c) 2011-2017 Stanislav Shwartsman
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2011-07-31 22:43:46 +04:00
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#include "bochs.h"
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2011-08-18 22:55:22 +04:00
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#include "cpu.h"
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2011-07-31 22:43:46 +04:00
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#include "p4_willamette.h"
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#define LOG_THIS cpu->
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2011-09-25 21:36:20 +04:00
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#if BX_CPU_LEVEL >= 6
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2011-07-31 22:43:46 +04:00
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2014-08-31 22:39:18 +04:00
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p4_willamette_t::p4_willamette_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
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{
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2015-02-12 23:18:35 +03:00
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enable_cpu_extension(BX_ISA_X87);
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enable_cpu_extension(BX_ISA_486);
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enable_cpu_extension(BX_ISA_PENTIUM);
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enable_cpu_extension(BX_ISA_MMX);
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enable_cpu_extension(BX_ISA_P6);
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enable_cpu_extension(BX_ISA_SYSENTER_SYSEXIT);
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enable_cpu_extension(BX_ISA_SSE);
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enable_cpu_extension(BX_ISA_SSE2);
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enable_cpu_extension(BX_ISA_CLFLUSH);
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enable_cpu_extension(BX_ISA_DEBUG_EXTENSIONS);
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enable_cpu_extension(BX_ISA_VME);
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enable_cpu_extension(BX_ISA_PSE);
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enable_cpu_extension(BX_ISA_PAE);
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enable_cpu_extension(BX_ISA_PGE);
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2014-08-31 22:39:18 +04:00
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#if BX_PHY_ADDRESS_LONG
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2015-02-12 23:18:35 +03:00
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enable_cpu_extension(BX_ISA_PSE36);
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2014-08-31 22:39:18 +04:00
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#endif
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2015-02-12 23:18:35 +03:00
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enable_cpu_extension(BX_ISA_MTRR);
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enable_cpu_extension(BX_ISA_PAT);
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enable_cpu_extension(BX_ISA_XAPIC);
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2014-08-31 22:39:18 +04:00
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}
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2011-08-01 22:10:48 +04:00
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void p4_willamette_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const
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2011-07-31 22:43:46 +04:00
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{
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2014-03-15 23:24:42 +04:00
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// CPUID function 0x80000002-0x80000004 - Processor Name String Identifier
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static const char* brand_string = " Intel(R) Pentium(R) 4 CPU 1.80GHz";
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2011-07-31 22:43:46 +04:00
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switch(function) {
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case 0x80000000:
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get_ext_cpuid_leaf_0(leaf);
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return;
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case 0x80000001:
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get_ext_cpuid_leaf_1(leaf);
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return;
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case 0x80000002:
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case 0x80000003:
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case 0x80000004:
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2014-03-15 23:24:42 +04:00
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get_ext_cpuid_brand_string_leaf(brand_string, function, leaf);
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2011-07-31 22:43:46 +04:00
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return;
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case 0x00000000:
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get_std_cpuid_leaf_0(leaf);
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return;
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case 0x00000001:
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get_std_cpuid_leaf_1(leaf);
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return;
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case 0x00000002:
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default:
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get_std_cpuid_leaf_2(leaf);
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return;
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}
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}
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// leaf 0x00000000 //
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2011-08-01 22:10:48 +04:00
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void p4_willamette_t::get_std_cpuid_leaf_0(cpuid_function_t *leaf) const
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2011-07-31 22:43:46 +04:00
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{
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2015-02-12 00:31:17 +03:00
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get_leaf_0(0x2, "GenuineIntel", leaf);
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2011-07-31 22:43:46 +04:00
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}
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// leaf 0x00000001 //
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2011-08-01 22:10:48 +04:00
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void p4_willamette_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf) const
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2011-07-31 22:43:46 +04:00
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{
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// EAX: CPU Version Information
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// [3:0] Stepping ID
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// [7:4] Model: starts at 1
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// [11:8] Family: 4=486, 5=Pentium, 6=PPro, ...
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// [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved
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// [19:16] Extended Model
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// [27:20] Extended Family
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leaf->eax = 0x00000F12;
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// EBX:
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// [7:0] Brand ID
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// [15:8] CLFLUSH cache line size (value*8 = cache line size in bytes)
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// [23:16] Number of logical processors in one physical processor
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// [31:24] Local Apic ID
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unsigned n_logical_processors = ncores*nthreads;
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leaf->ebx = ((CACHE_LINE_SIZE / 8) << 8) |
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(n_logical_processors << 16);
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#if BX_SUPPORT_APIC
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leaf->ebx |= ((cpu->get_apic_id() & 0xff) << 24);
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#endif
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// ECX: Extended Feature Flags
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leaf->ecx = 0;
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// EDX: Standard Feature Flags
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// * [0:0] FPU on chip
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// * [1:1] VME: Virtual-8086 Mode enhancements
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// * [2:2] DE: Debug Extensions (I/O breakpoints)
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// * [3:3] PSE: Page Size Extensions
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// * [4:4] TSC: Time Stamp Counter
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// * [5:5] MSR: RDMSR and WRMSR support
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// * [6:6] PAE: Physical Address Extensions
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// * [7:7] MCE: Machine Check Exception
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// * [8:8] CXS: CMPXCHG8B instruction
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// * [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// * [11:11] SYSENTER/SYSEXIT support
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// * [12:12] MTRR: Memory Type Range Reg
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// * [13:13] PGE/PTE Global Bit
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// * [14:14] MCA: Machine Check Architecture
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// * [15:15] CMOV: Cond Mov/Cmp Instructions
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// * [16:16] PAT: Page Attribute Table
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// * [17:17] PSE-36: Physical Address Extensions
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// [18:18] PSN: Processor Serial Number
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// * [19:19] CLFLUSH: CLFLUSH Instruction support
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// [20:20] Reserved
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// * [21:21] DS: Debug Store
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// * [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
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// * [23:23] MMX Technology
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// * [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// * [25:25] SSE: SSE Extensions
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// * [26:26] SSE2: SSE2 Extensions
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// * [27:27] Self Snoop
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// * [28:28] Hyper Threading Technology
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// * [29:29] TM: Thermal Monitor
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// [30:30] Reserved
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// [31:31] PBE: Pending Break Enable
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leaf->edx = BX_CPUID_STD_X87 |
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BX_CPUID_STD_VME |
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BX_CPUID_STD_DEBUG_EXTENSIONS |
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BX_CPUID_STD_PSE |
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BX_CPUID_STD_TSC |
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BX_CPUID_STD_MSR |
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BX_CPUID_STD_PAE |
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BX_CPUID_STD_MCE |
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BX_CPUID_STD_CMPXCHG8B |
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BX_CPUID_STD_SYSENTER_SYSEXIT |
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BX_CPUID_STD_MTRR |
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BX_CPUID_STD_GLOBAL_PAGES |
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BX_CPUID_STD_MCA |
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BX_CPUID_STD_CMOV |
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BX_CPUID_STD_PAT |
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2011-08-03 21:49:49 +04:00
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#if BX_PHY_ADDRESS_LONG
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2011-07-31 22:43:46 +04:00
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BX_CPUID_STD_PSE36 |
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2011-08-03 21:49:49 +04:00
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#endif
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2011-07-31 22:43:46 +04:00
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BX_CPUID_STD_CLFLUSH |
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BX_CPUID_STD_DEBUG_STORE |
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BX_CPUID_STD_ACPI |
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BX_CPUID_STD_MMX |
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BX_CPUID_STD_FXSAVE_FXRSTOR |
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BX_CPUID_STD_SSE |
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BX_CPUID_STD_SSE2 |
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2020-01-11 09:18:13 +03:00
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BX_CPUID_STD_SELF_SNOOP
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#if BX_SUPPORT_SMP
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| BX_CPUID_STD_HT
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#endif
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;
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2011-07-31 22:43:46 +04:00
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#if BX_SUPPORT_APIC
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// if MSR_APICBASE APIC Global Enable bit has been cleared,
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// the CPUID feature flag for the APIC is set to 0.
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if (cpu->msr.apicbase & 0x800)
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leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip
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#endif
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}
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// leaf 0x00000002 //
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2011-08-01 22:10:48 +04:00
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void p4_willamette_t::get_std_cpuid_leaf_2(cpuid_function_t *leaf) const
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2011-07-31 22:43:46 +04:00
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{
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// CPUID function 0x00000002 - Cache and TLB Descriptors
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leaf->eax = 0x665B5001;
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leaf->ebx = 0x00000000;
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leaf->ecx = 0x00000000;
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leaf->edx = 0x007A7040;
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}
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// leaf 0x80000000 //
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2011-08-01 22:10:48 +04:00
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void p4_willamette_t::get_ext_cpuid_leaf_0(cpuid_function_t *leaf) const
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2011-07-31 22:43:46 +04:00
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{
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// EAX: highest extended function understood by CPUID
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// EBX: reserved
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// EDX: reserved
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// ECX: reserved
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2015-02-12 00:31:17 +03:00
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get_leaf_0(0x80000004, NULL, leaf);
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2011-07-31 22:43:46 +04:00
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}
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// leaf 0x80000001 //
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2011-08-01 22:10:48 +04:00
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void p4_willamette_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
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2011-07-31 22:43:46 +04:00
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{
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// EAX: CPU Version Information (reserved for Intel)
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leaf->eax = 0;
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// EBX: Brand ID (reserved for Intel)
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leaf->ebx = 0;
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// ECX:
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// [0:0] LAHF/SAHF instructions support in 64-bit mode
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// [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD)
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// [2:2] SVM: Secure Virtual Machine (AMD)
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// [3:3] Extended APIC Space
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// [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
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// [5:5] LZCNT: LZCNT instruction support
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2013-06-20 23:33:30 +04:00
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// [6:6] SSE4A: SSE4A Instructions support
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2011-07-31 22:43:46 +04:00
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// [7:7] Misaligned SSE support
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// [8:8] PREFETCHW: PREFETCHW instruction support
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// [9:9] OSVW: OS visible workarounds (AMD)
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// [11:10] reserved
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// [12:12] SKINIT support
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// [13:13] WDT: Watchdog timer support
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// [31:14] reserved
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leaf->ecx = 0;
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// EDX:
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// Many of the bits in EDX are the same as FN 0x00000001 [*] for AMD
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// [10:0] Reserved for Intel
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// [11:11] SYSCALL/SYSRET support
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// [19:12] Reserved for Intel
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// [20:20] No-Execute page protection
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// [25:21] Reserved
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// [26:26] 1G paging support
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// [27:27] Support RDTSCP Instruction
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// [28:28] Reserved
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// [29:29] Long Mode
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// [30:30] AMD 3DNow! Extensions
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// [31:31] AMD 3DNow! Instructions
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leaf->edx = 0;
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}
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// leaf 0x80000002 //
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// leaf 0x80000003 //
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// leaf 0x80000004 //
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2011-08-01 22:10:48 +04:00
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void p4_willamette_t::dump_cpuid(void) const
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2011-07-31 22:43:46 +04:00
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{
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2014-10-15 12:04:38 +04:00
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bx_cpuid_t::dump_cpuid(0x2, 0x4);
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2011-07-31 22:43:46 +04:00
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}
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bx_cpuid_t *create_p4_willamette_cpuid(BX_CPU_C *cpu) { return new p4_willamette_t(cpu); }
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#endif
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