56 lines
1.8 KiB
Plaintext
56 lines
1.8 KiB
Plaintext
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From zwane@linux.realnet.co.sz Thu Mar 28 12:01:06 2002
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Date: Thu, 28 Mar 2002 08:46:53 +0200 (SAST)
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From: Zwane Mwaikambo <zwane@linux.realnet.co.sz>
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To: Bryce Denney <bryce@tlw.com>
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Cc: William Lee Irwin III <wli@holomorphy.com>
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Subject: [BOCHS-SMP] processor priority
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Hi Bryce,
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Did you written your processor priority patch? Here's something
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which is supposed to work if you haven't written one yet.
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Cheers,
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Zwane
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diff -ur /tmp/bochs-1.3-smp/cpu/apic.cc bochs-1.3-smp/cpu/apic.cc
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--- /tmp/bochs-1.3-smp/cpu/apic.cc Mon Mar 25 10:02:49 2002
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+++ bochs-1.3-smp/cpu/apic.cc Thu Mar 28 07:20:25 2002
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@@ -703,10 +703,18 @@
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Bit8u bx_local_apic_c::get_ppr ()
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{
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+ Bit32u tpr = (task_priority >> 4) & 0xf; /* we want 7:4 */
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+ Bit32u isrv = (highest_priority_int(isr) >> 4) & 0xf; /* ditto */
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+
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+ if (tpr >= isrv)
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+ proc_priority = task_priority & 0xff;
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+ else
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+ proc_priority = isrv << 4; /* low 4 bits of PPR have to be cleared */
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+
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if (bx_dbg.apic)
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- BX_INFO(("WARNING: Local APIC Processor Priority not implemented, returning 0"));
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- // should look at TPR, vector of highest priority isr, etc.
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- return 0;
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+ BX_INFO(("%s: get_ppr returning %#x", cpu->name, proc_priority));
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+
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+ return proc_priority & 0xff;
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}
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diff -ur /tmp/bochs-1.3-smp/cpu/cpu.h bochs-1.3-smp/cpu/cpu.h
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--- /tmp/bochs-1.3-smp/cpu/cpu.h Thu Mar 28 06:16:24 2002
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+++ bochs-1.3-smp/cpu/cpu.h Thu Mar 28 06:40:53 2002
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@@ -614,7 +614,7 @@
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// ISR=in-service register. When an IRR bit is cleared, the corresponding
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// bit in ISR is set. The ISR bit is cleared when
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Bit8u isr[BX_LOCAL_APIC_MAX_INTS];
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- Bit32u arb_id, arb_priority, task_priority, log_dest, dest_format, spurious_vec;
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+ Bit32u arb_id, arb_priority, task_priority, proc_priority, log_dest, dest_format, spurious_vec;
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Bit32u lvt[6];
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#define APIC_LVT_TIMER 0
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#define APIC_LVT_THERMAL 1
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--
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http://function.linuxpower.ca
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