2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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2011-02-25 00:54:04 +03:00
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// $Id$
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2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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//
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2012-01-12 00:21:29 +04:00
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// Copyright (C) 2001-2012 The Bochs Project
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2001-04-10 05:04:59 +04:00
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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2009-01-16 21:18:59 +03:00
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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2007-11-17 21:08:46 +03:00
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/////////////////////////////////////////////////////////////////////////
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2001-04-10 05:04:59 +04:00
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2001-05-24 22:46:34 +04:00
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#define NEED_CPU_REG_SHORTCUTS 1
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2001-04-10 05:04:59 +04:00
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#include "bochs.h"
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2006-03-07 01:03:16 +03:00
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#include "cpu.h"
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merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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#define LOG_THIS BX_CPU_THIS_PTR
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2001-04-10 05:04:59 +04:00
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EwGwM(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-16 20:45:58 +03:00
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Bit16u op1_16, op2_16;
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2001-04-10 05:04:59 +04:00
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2008-08-08 13:22:49 +04:00
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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2008-01-10 22:37:56 +03:00
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2008-08-08 13:22:49 +04:00
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op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
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2002-09-30 07:37:42 +04:00
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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2007-11-17 15:44:10 +03:00
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op1_16 ^= op2_16;
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write_RMW_virtual_word(op1_16);
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2001-04-10 05:04:59 +04:00
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2007-11-20 20:15:33 +03:00
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SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2007-11-17 15:44:10 +03:00
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}
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2002-10-08 02:51:58 +04:00
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GwEwR(bxInstruction_c *i)
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2007-11-22 01:36:02 +03:00
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{
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Bit16u op1_16, op2_16;
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2001-04-10 05:04:59 +04:00
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2007-11-22 01:36:02 +03:00
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op1_16 = BX_READ_16BIT_REG(i->nnn());
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op2_16 = BX_READ_16BIT_REG(i->rm());
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op1_16 ^= op2_16;
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2007-11-08 21:21:37 +03:00
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BX_WRITE_16BIT_REG(i->nnn(), op1_16);
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2001-04-10 05:04:59 +04:00
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2007-11-20 20:15:33 +03:00
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SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2001-04-10 05:04:59 +04:00
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}
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2012-01-09 17:09:59 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GwEwM(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_16 = BX_READ_16BIT_REG(i->nnn());
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op2_16 = read_virtual_word(i->seg(), eaddr);
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op1_16 ^= op2_16;
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BX_WRITE_16BIT_REG(i->nnn(), op1_16);
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SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
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BX_NEXT_INSTR(i);
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_AXIw(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2011-04-12 10:05:31 +04:00
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Bit16u op_16 = AX ^ i->Iw();
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AX = op_16;
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2001-04-10 05:04:59 +04:00
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2011-04-12 10:05:31 +04:00
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SET_FLAGS_OSZAPC_LOGIC_16(op_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2001-04-10 05:04:59 +04:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EwIwM(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-16 20:45:58 +03:00
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Bit16u op1_16;
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2001-04-10 05:04:59 +04:00
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2008-08-08 13:22:49 +04:00
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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2008-01-10 22:37:56 +03:00
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2008-08-08 13:22:49 +04:00
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op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
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2007-11-16 20:45:58 +03:00
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op1_16 ^= i->Iw();
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write_RMW_virtual_word(op1_16);
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2001-04-10 05:04:59 +04:00
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2007-11-20 20:15:33 +03:00
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SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2007-11-16 20:45:58 +03:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EwIwR(bxInstruction_c *i)
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2007-11-16 20:45:58 +03:00
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{
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Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
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op1_16 ^= i->Iw();
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BX_WRITE_16BIT_REG(i->rm(), op1_16);
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2001-04-10 05:04:59 +04:00
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2007-11-20 20:15:33 +03:00
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SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2001-04-10 05:04:59 +04:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EwIwM(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-16 20:45:58 +03:00
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Bit16u op1_16;
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2001-04-10 05:04:59 +04:00
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2008-08-08 13:22:49 +04:00
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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2008-01-10 22:37:56 +03:00
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2008-08-08 13:22:49 +04:00
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op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
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2007-11-16 20:45:58 +03:00
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op1_16 |= i->Iw();
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write_RMW_virtual_word(op1_16);
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2001-04-10 05:04:59 +04:00
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2007-11-20 20:15:33 +03:00
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SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2007-11-16 20:45:58 +03:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EwIwR(bxInstruction_c *i)
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2007-11-16 20:45:58 +03:00
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{
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Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
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op1_16 |= i->Iw();
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BX_WRITE_16BIT_REG(i->rm(), op1_16);
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2001-04-10 05:04:59 +04:00
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2007-11-20 20:15:33 +03:00
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SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2001-04-10 05:04:59 +04:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EwM(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2008-08-08 13:22:49 +04:00
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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2008-01-10 22:37:56 +03:00
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2011-01-25 23:59:26 +03:00
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Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
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2007-11-17 19:20:37 +03:00
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op1_16 = ~op1_16;
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write_RMW_virtual_word(op1_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2007-11-17 19:20:37 +03:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EwR(bxInstruction_c *i)
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2007-11-17 19:20:37 +03:00
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{
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Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
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op1_16 = ~op1_16;
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BX_WRITE_16BIT_REG(i->rm(), op1_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2001-04-10 05:04:59 +04:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EwGwM(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-16 20:45:58 +03:00
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Bit16u op1_16, op2_16;
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2001-04-10 05:04:59 +04:00
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2008-08-08 13:22:49 +04:00
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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2008-01-10 22:37:56 +03:00
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2008-08-08 13:22:49 +04:00
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op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
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2002-09-30 07:37:42 +04:00
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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2007-11-17 15:44:10 +03:00
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op1_16 |= op2_16;
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write_RMW_virtual_word(op1_16);
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2001-04-10 05:04:59 +04:00
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2007-11-20 20:15:33 +03:00
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SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2007-11-17 15:44:10 +03:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GwEwR(bxInstruction_c *i)
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2007-11-22 01:36:02 +03:00
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{
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Bit16u op1_16, op2_16;
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2001-04-10 05:04:59 +04:00
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2007-11-22 01:36:02 +03:00
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op1_16 = BX_READ_16BIT_REG(i->nnn());
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op2_16 = BX_READ_16BIT_REG(i->rm());
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op1_16 |= op2_16;
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2007-10-22 03:35:11 +04:00
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BX_WRITE_16BIT_REG(i->nnn(), op1_16);
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2007-11-20 20:15:33 +03:00
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SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2001-04-10 05:04:59 +04:00
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}
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2012-01-09 17:09:59 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GwEwM(bxInstruction_c *i)
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{
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Bit16u op1_16, op2_16;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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op1_16 = BX_READ_16BIT_REG(i->nnn());
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op2_16 = read_virtual_word(i->seg(), eaddr);
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op1_16 |= op2_16;
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BX_WRITE_16BIT_REG(i->nnn(), op1_16);
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SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
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BX_NEXT_INSTR(i);
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_AXIw(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2011-04-12 10:05:31 +04:00
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Bit16u op_16 = AX | i->Iw();
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AX = op_16;
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2001-04-10 05:04:59 +04:00
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2011-04-12 10:05:31 +04:00
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SET_FLAGS_OSZAPC_LOGIC_16(op_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2001-04-10 05:04:59 +04:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwGwM(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2007-11-16 20:45:58 +03:00
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Bit16u op1_16, op2_16;
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2002-09-23 02:22:16 +04:00
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2008-08-08 13:22:49 +04:00
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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2008-01-10 22:37:56 +03:00
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2008-08-08 13:22:49 +04:00
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op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
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2002-09-23 02:22:16 +04:00
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op2_16 = BX_READ_16BIT_REG(i->nnn());
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2007-11-17 15:44:10 +03:00
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op1_16 &= op2_16;
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write_RMW_virtual_word(op1_16);
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2002-09-23 02:22:16 +04:00
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2007-11-20 20:15:33 +03:00
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SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2007-11-17 15:44:10 +03:00
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}
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2011-07-07 00:01:18 +04:00
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BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GwEwR(bxInstruction_c *i)
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2007-11-22 01:36:02 +03:00
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{
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Bit16u op1_16, op2_16;
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2002-09-28 05:48:18 +04:00
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2007-11-22 01:36:02 +03:00
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op1_16 = BX_READ_16BIT_REG(i->nnn());
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op2_16 = BX_READ_16BIT_REG(i->rm());
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op1_16 &= op2_16;
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2007-10-22 03:35:11 +04:00
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BX_WRITE_16BIT_REG(i->nnn(), op1_16);
|
2007-11-20 20:15:33 +03:00
|
|
|
|
|
|
|
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2012-01-09 17:09:59 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GwEwM(bxInstruction_c *i)
|
|
|
|
{
|
|
|
|
Bit16u op1_16, op2_16;
|
|
|
|
|
|
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
|
|
|
|
|
|
|
op1_16 = BX_READ_16BIT_REG(i->nnn());
|
|
|
|
op2_16 = read_virtual_word(i->seg(), eaddr);
|
|
|
|
op1_16 &= op2_16;
|
|
|
|
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
|
|
|
|
|
|
|
|
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
|
|
|
}
|
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_AXIw(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2011-04-12 10:05:31 +04:00
|
|
|
Bit16u op_16 = AX & i->Iw();
|
|
|
|
AX = op_16;
|
2007-11-20 20:15:33 +03:00
|
|
|
|
2011-04-12 10:05:31 +04:00
|
|
|
SET_FLAGS_OSZAPC_LOGIC_16(op_16);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwIwM(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2007-11-16 20:45:58 +03:00
|
|
|
Bit16u op1_16;
|
2002-09-23 02:22:16 +04:00
|
|
|
|
2008-08-08 13:22:49 +04:00
|
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
2008-01-10 22:37:56 +03:00
|
|
|
|
2008-08-08 13:22:49 +04:00
|
|
|
op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
|
2007-11-16 20:45:58 +03:00
|
|
|
op1_16 &= i->Iw();
|
|
|
|
write_RMW_virtual_word(op1_16);
|
2002-09-23 02:22:16 +04:00
|
|
|
|
2007-11-20 20:15:33 +03:00
|
|
|
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2007-11-16 20:45:58 +03:00
|
|
|
}
|
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwIwR(bxInstruction_c *i)
|
2007-11-16 20:45:58 +03:00
|
|
|
{
|
|
|
|
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
|
|
op1_16 &= i->Iw();
|
|
|
|
BX_WRITE_16BIT_REG(i->rm(), op1_16);
|
2002-09-28 05:48:18 +04:00
|
|
|
|
2007-11-20 20:15:33 +03:00
|
|
|
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwGwR(bxInstruction_c *i)
|
2007-11-17 21:08:46 +03:00
|
|
|
{
|
|
|
|
Bit16u op1_16, op2_16;
|
2002-09-23 02:22:16 +04:00
|
|
|
|
2007-11-17 21:08:46 +03:00
|
|
|
op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
|
|
op2_16 = BX_READ_16BIT_REG(i->nnn());
|
2007-10-22 03:35:11 +04:00
|
|
|
op1_16 &= op2_16;
|
2007-11-20 20:15:33 +03:00
|
|
|
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2012-01-09 17:09:59 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwGwM(bxInstruction_c *i)
|
|
|
|
{
|
|
|
|
Bit16u op1_16, op2_16;
|
|
|
|
|
|
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
|
|
|
|
|
|
|
op1_16 = read_virtual_word(i->seg(), eaddr);
|
|
|
|
op2_16 = BX_READ_16BIT_REG(i->nnn());
|
|
|
|
op1_16 &= op2_16;
|
|
|
|
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
|
|
|
}
|
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_AXIw(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2011-04-12 10:05:31 +04:00
|
|
|
Bit16u op_16 = AX & i->Iw();
|
2002-09-23 02:22:16 +04:00
|
|
|
|
2011-04-12 10:05:31 +04:00
|
|
|
SET_FLAGS_OSZAPC_LOGIC_16(op_16);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwIwR(bxInstruction_c *i)
|
2007-11-17 19:20:37 +03:00
|
|
|
{
|
|
|
|
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
|
|
|
|
op1_16 &= i->Iw();
|
2007-11-20 20:15:33 +03:00
|
|
|
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
2012-01-09 17:09:59 +04:00
|
|
|
|
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwIwM(bxInstruction_c *i)
|
|
|
|
{
|
|
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
|
|
|
|
|
|
|
Bit16u op1_16 = read_virtual_word(i->seg(), eaddr);
|
|
|
|
op1_16 &= i->Iw();
|
|
|
|
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
|
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
|
|
|
}
|