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Bochs/bochs/cpu/arith16.cc

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- add RCS Id to header of every file. This makes it easier to know what's going on when someone sends in a modified file.
2001-10-03 17:10:38 +04:00
/////////////////////////////////////////////////////////////////////////
I rehashed the way the EFLAGS register was stored internally. All the EFLAGS bits used to be cached in separate fields. I left a few of them in separate fields for now - might remove them at some point also. When the arithmetic fields are known (ie they're not in lazy mode), they are all cached in a 32-bit EFLAGS image, just like the x86 EFLAGS register expects. All other eflags are store in the 32-bit register also, with a few also mirrored in separate fields for now. The reason I did this, was so that on x86 hosts, asm() statements can be #ifdef'd in to do the calculation and get the native eflags results very cheaply. Just to test that it works, I coded ADD_EdId() and ADD_EwIw() with some conditionally compiled asm()s for accelerated eflags processing and it works. -Kevin
2002-09-08 08:08:14 +04:00
// $Id: arith16.cc,v 1.8 2002-09-08 04:08:14 kevinlawton Exp $
- add RCS Id to header of every file. This makes it easier to know what's going on when someone sends in a modified file.
2001-10-03 17:10:38 +04:00
/////////////////////////////////////////////////////////////////////////
//
- update copyright dates to 2001 for all mandrake headers - for bochs files with other header, replaced with current mandrake header
2001-04-10 06:20:02 +04:00
// Copyright (C) 2001 MandrakeSoft S.A.
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
//
// MandrakeSoft S.A.
// 43, rue d'Aboukir
// 75002 Paris - France
// http://www.linux-mandrake.com/
// http://www.mandrakesoft.com/
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- parts of the SMP merge apparantly broke the debugger and this revision tries to fix it. The shortcuts to register names such as AX and DL are #defines in cpu/cpu.h, and they are defined in terms of BX_CPU_THIS_PTR. When BX_USE_CPU_SMF=1, this works fine. (This is what bochs used for a long time, and nobody used the SMF=0 mode at all.) To make SMP bochs work, I had to get SMF=0 mode working for the CPU so that there could be an array of cpus. When SMF=0 for the CPU, BX_CPU_THIS_PTR is defined to be "this->" which only works within methods of BX_CPU_C. Code outside of BX_CPU_C must reference BX_CPU(num) instead. - to try to enforce the correct use of AL/AX/DL/etc. shortcuts, they are now only #defined when "NEED_CPU_REG_SHORTCUTS" is #defined. This is only done in the cpu/*.cc code.
2001-05-24 22:46:34 +04:00
#define NEED_CPU_REG_SHORTCUTS 1
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
#include "bochs.h"
merge in BRANCH-io-cleanup. To see the commit logs for this use either cvsweb or cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files. In general this provides a generic interface for logging. logfunctions:: is a class that is inherited by some classes, and also . allocated as a standalone global called 'genlog'. All logging uses . one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this . class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros . respectively. . . An example usage: . BX_INFO(("Hello, World!\n")); iofunctions:: is a class that is allocated once by default, and assigned as the iofunction of each logfunctions instance. It is this class that maintains the file descriptor and other output related code, at this point using vfprintf(). At some future point, someone may choose to write a gui 'console' for bochs to which messages would be redirected simply by assigning a different iofunction class to the various logfunctions objects. More cleanup is coming, but this works for now. If you want to see alot of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1. Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
#define LOG_THIS BX_CPU_THIS_PTR
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
void
BX_CPU_C::INC_RX(BxInstruction_t *i)
{
Bit16u rx;
rx = ++ BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx;
SET_FLAGS_OSZAP_16(0, 0, rx, BX_INSTR_INC16);
}
void
BX_CPU_C::DEC_RX(BxInstruction_t *i)
{
Bit16u rx;
rx = -- BX_CPU_THIS_PTR gen_reg[i->b1 & 0x07].word.rx;
SET_FLAGS_OSZAP_16(0, 0, rx, BX_INSTR_DEC16);
}
void
BX_CPU_C::ADD_EwGw(BxInstruction_t *i)
{
Bit16u op2_16, op1_16, sum_16;
/* op2_16 is a register, i->rm_addr is an index of a register */
op2_16 = BX_READ_16BIT_REG(i->nnn);
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg, i->rm_addr, &op1_16);
}
sum_16 = op1_16 + op2_16;
/* now write sum back to destination */
if (i->mod == 0xc0) {
BX_WRITE_16BIT_REG(i->rm, sum_16);
}
else {
write_virtual_word(i->seg, i->rm_addr, &sum_16);
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD16);
}
void
BX_CPU_C::ADD_GwEw(BxInstruction_t *i)
{
Bit16u op1_16, op2_16, sum_16;
/* op1_16 is a register, i->rm_addr is an index of a register */
op1_16 = BX_READ_16BIT_REG(i->nnn);
/* op2_16 is a register or memory reference */
if (i->mod == 0xc0) {
op2_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg, i->rm_addr, &op2_16);
}
sum_16 = op1_16 + op2_16;
/* now write sum back to destination */
BX_WRITE_16BIT_REG(i->nnn, sum_16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD16);
}
void
BX_CPU_C::ADD_AXIw(BxInstruction_t *i)
{
Bit16u op1_16, op2_16, sum_16;
op1_16 = AX;
op2_16 = i->Iw;
sum_16 = op1_16 + op2_16;
/* now write sum back to destination */
AX = sum_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD16);
}
void
BX_CPU_C::ADC_EwGw(BxInstruction_t *i)
{
Boolean temp_CF;
Bit16u op2_16, op1_16, sum_16;
temp_CF = get_CF();
/* op2_16 is a register, i->rm_addr is an index of a register */
op2_16 = BX_READ_16BIT_REG(i->nnn);
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
}
sum_16 = op1_16 + op2_16 + temp_CF;
/* now write sum back to destination */
if (i->mod == 0xc0) {
BX_WRITE_16BIT_REG(i->rm, sum_16);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_word(sum_16);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16,
temp_CF);
}
void
BX_CPU_C::ADC_GwEw(BxInstruction_t *i)
{
Boolean temp_CF;
Bit16u op1_16, op2_16, sum_16;
temp_CF = get_CF();
/* op1_16 is a register, i->rm_addr is an index of a register */
op1_16 = BX_READ_16BIT_REG(i->nnn);
/* op2_16 is a register or memory reference */
if (i->mod == 0xc0) {
op2_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg, i->rm_addr, &op2_16);
}
sum_16 = op1_16 + op2_16 + temp_CF;
/* now write sum back to destination */
BX_WRITE_16BIT_REG(i->nnn, sum_16);
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16,
temp_CF);
}
void
BX_CPU_C::ADC_AXIw(BxInstruction_t *i)
{
Boolean temp_CF;
Bit16u op1_16, op2_16, sum_16;
temp_CF = get_CF();
op1_16 = AX;
op2_16 = i->Iw;
sum_16 = op1_16 + op2_16 + temp_CF;
/* now write sum back to destination */
AX = sum_16;
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16,
temp_CF);
}
void
BX_CPU_C::SBB_EwGw(BxInstruction_t *i)
{
Boolean temp_CF;
Bit16u op2_16, op1_16, diff_16;
temp_CF = get_CF();
/* op2_16 is a register, i->rm_addr is an index of a register */
op2_16 = BX_READ_16BIT_REG(i->nnn);
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
}
diff_16 = op1_16 - (op2_16 + temp_CF);
/* now write diff back to destination */
if (i->mod == 0xc0) {
BX_WRITE_16BIT_REG(i->rm, diff_16);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_word(diff_16);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, diff_16, BX_INSTR_SBB16,
temp_CF);
}
void
BX_CPU_C::SBB_GwEw(BxInstruction_t *i)
{
Boolean temp_CF;
temp_CF = get_CF();
Bit16u op1_16, op2_16, diff_16;
/* op1_16 is a register, i->rm_addr is an index of a register */
op1_16 = BX_READ_16BIT_REG(i->nnn);
/* op2_16 is a register or memory reference */
if (i->mod == 0xc0) {
op2_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg, i->rm_addr, &op2_16);
}
diff_16 = op1_16 - (op2_16 + temp_CF);
/* now write diff back to destination */
BX_WRITE_16BIT_REG(i->nnn, diff_16);
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, diff_16, BX_INSTR_SBB16,
temp_CF);
}
void
BX_CPU_C::SBB_AXIw(BxInstruction_t *i)
{
Boolean temp_CF;
Bit16u op1_16, op2_16, diff_16;
temp_CF = get_CF();
op1_16 = AX;
op2_16 = i->Iw;
diff_16 = op1_16 - (op2_16 + temp_CF);
/* now write diff back to destination */
AX = diff_16;
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, diff_16, BX_INSTR_SBB16,
temp_CF);
}
void
BX_CPU_C::SBB_EwIw(BxInstruction_t *i)
{
Boolean temp_CF;
Bit16u op2_16, op1_16, diff_16;
temp_CF = get_CF();
op2_16 = i->Iw;
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
}
diff_16 = op1_16 - (op2_16 + temp_CF);
/* now write diff back to destination */
if (i->mod == 0xc0) {
BX_WRITE_16BIT_REG(i->rm, diff_16);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_word(diff_16);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, diff_16, BX_INSTR_SBB16,
temp_CF);
}
void
BX_CPU_C::SUB_EwGw(BxInstruction_t *i)
{
Bit16u op2_16, op1_16, diff_16;
/* op2_16 is a register, i->rm_addr is an index of a register */
op2_16 = BX_READ_16BIT_REG(i->nnn);
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
}
diff_16 = op1_16 - op2_16;
/* now write diff back to destination */
if (i->mod == 0xc0) {
BX_WRITE_16BIT_REG(i->rm, diff_16);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_word(diff_16);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_SUB16);
}
void
BX_CPU_C::SUB_GwEw(BxInstruction_t *i)
{
Bit16u op1_16, op2_16, diff_16;
/* op1_16 is a register, i->rm_addr is an index of a register */
op1_16 = BX_READ_16BIT_REG(i->nnn);
/* op2_16 is a register or memory reference */
if (i->mod == 0xc0) {
op2_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg, i->rm_addr, &op2_16);
}
diff_16 = op1_16 - op2_16;
/* now write diff back to destination */
BX_WRITE_16BIT_REG(i->nnn, diff_16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_SUB16);
}
void
BX_CPU_C::SUB_AXIw(BxInstruction_t *i)
{
Bit16u op1_16, op2_16, diff_16;
op1_16 = AX;
op2_16 = i->Iw;
diff_16 = op1_16 - op2_16;
/* now write diff back to destination */
AX = diff_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_SUB16);
}
void
BX_CPU_C::CMP_EwGw(BxInstruction_t *i)
{
Bit16u op2_16, op1_16, diff_16;
/* op2_16 is a register, i->rm_addr is an index of a register */
op2_16 = BX_READ_16BIT_REG(i->nnn);
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg, i->rm_addr, &op1_16);
}
diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMP16);
}
void
BX_CPU_C::CMP_GwEw(BxInstruction_t *i)
{
Bit16u op1_16, op2_16, diff_16;
/* op1_16 is a register, i->rm_addr is an index of a register */
op1_16 = BX_READ_16BIT_REG(i->nnn);
/* op2_16 is a register or memory reference */
if (i->mod == 0xc0) {
op2_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg, i->rm_addr, &op2_16);
}
diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMP16);
}
void
BX_CPU_C::CMP_AXIw(BxInstruction_t *i)
{
Bit16u op1_16, op2_16, diff_16;
op1_16 = AX;
op2_16 = i->Iw;
diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMP16);
}
void
BX_CPU_C::CBW(BxInstruction_t *i)
{
/* CBW: no flags are effected */
AX = (Bit8s) AL;
}
void
BX_CPU_C::CWD(BxInstruction_t *i)
{
/* CWD: no flags are affected */
if (AX & 0x8000) {
DX = 0xFFFF;
}
else {
DX = 0x0000;
}
}
void
BX_CPU_C::XADD_EwGw(BxInstruction_t *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit16u op2_16, op1_16, sum_16;
/* XADD dst(r/m), src(r)
* temp <-- src + dst | sum = op2 + op1
* src <-- dst | op2 = op1
* dst <-- tmp | op1 = sum
*/
/* op2 is a register, i->rm_addr is an index of a register */
op2_16 = BX_READ_16BIT_REG(i->nnn);
/* op1 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
}
sum_16 = op1_16 + op2_16;
/* now write sum back to destination */
if (i->mod == 0xc0) {
// and write destination into source
// Note: if both op1 & op2 are registers, the last one written
// should be the sum, as op1 & op2 may be the same register.
// For example: XADD AL, AL
BX_WRITE_16BIT_REG(i->nnn, op1_16);
BX_WRITE_16BIT_REG(i->rm, sum_16);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_word(sum_16);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
/* and write destination into source */
BX_WRITE_16BIT_REG(i->nnn, op1_16);
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_XADD16);
#else
strip '\n' from BX_{INFO,DEBUG,ERROR,PANIC} don't need it, moved the output of it into the general io functions. saves space, as well as removes the confusing output if a '\n' is left off
2001-05-30 22:56:02 +04:00
BX_PANIC(("XADD_EvGv: not supported on < 80486"));
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
#endif
}
void
BX_CPU_C::ADD_EwIw(BxInstruction_t *i)
{
I rehashed the way the EFLAGS register was stored internally. All the EFLAGS bits used to be cached in separate fields. I left a few of them in separate fields for now - might remove them at some point also. When the arithmetic fields are known (ie they're not in lazy mode), they are all cached in a 32-bit EFLAGS image, just like the x86 EFLAGS register expects. All other eflags are store in the 32-bit register also, with a few also mirrored in separate fields for now. The reason I did this, was so that on x86 hosts, asm() statements can be #ifdef'd in to do the calculation and get the native eflags results very cheaply. Just to test that it works, I coded ADD_EdId() and ADD_EwIw() with some conditionally compiled asm()s for accelerated eflags processing and it works. -Kevin
2002-09-08 08:08:14 +04:00
Bit16u op2_16, op1_16, sum_16;
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
I rehashed the way the EFLAGS register was stored internally. All the EFLAGS bits used to be cached in separate fields. I left a few of them in separate fields for now - might remove them at some point also. When the arithmetic fields are known (ie they're not in lazy mode), they are all cached in a 32-bit EFLAGS image, just like the x86 EFLAGS register expects. All other eflags are store in the 32-bit register also, with a few also mirrored in separate fields for now. The reason I did this, was so that on x86 hosts, asm() statements can be #ifdef'd in to do the calculation and get the native eflags results very cheaply. Just to test that it works, I coded ADD_EdId() and ADD_EwIw() with some conditionally compiled asm()s for accelerated eflags processing and it works. -Kevin
2002-09-08 08:08:14 +04:00
op2_16 = i->Iw;
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
}
#if (defined(__i386__) && defined(__GNUC__))
Bit32u flags32;
asm volatile (
"addw %3, %1 \n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_16)
: "1" (op1_16), "g" (op2_16)
: "memory", "cc"
);
#else
sum_16 = op1_16 + op2_16;
#endif
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
I rehashed the way the EFLAGS register was stored internally. All the EFLAGS bits used to be cached in separate fields. I left a few of them in separate fields for now - might remove them at some point also. When the arithmetic fields are known (ie they're not in lazy mode), they are all cached in a 32-bit EFLAGS image, just like the x86 EFLAGS register expects. All other eflags are store in the 32-bit register also, with a few also mirrored in separate fields for now. The reason I did this, was so that on x86 hosts, asm() statements can be #ifdef'd in to do the calculation and get the native eflags results very cheaply. Just to test that it works, I coded ADD_EdId() and ADD_EwIw() with some conditionally compiled asm()s for accelerated eflags processing and it works. -Kevin
2002-09-08 08:08:14 +04:00
/* now write sum back to destination */
if (i->mod == 0xc0) {
BX_WRITE_16BIT_REG(i->rm, sum_16);
}
else {
Write_RMW_virtual_word(sum_16);
}
#if (defined(__i386__) && defined(__GNUC__))
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~0x000008d5) | (flags32 & 0x000008d5);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD16);
#endif
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
void
BX_CPU_C::ADC_EwIw(BxInstruction_t *i)
{
Boolean temp_CF;
Bit16u op2_16, op1_16, sum_16;
temp_CF = get_CF();
op2_16 = i->Iw;
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
}
sum_16 = op1_16 + op2_16 + temp_CF;
/* now write sum back to destination */
if (i->mod == 0xc0) {
BX_WRITE_16BIT_REG(i->rm, sum_16);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_word(sum_16);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_16_CF(op1_16, op2_16, sum_16, BX_INSTR_ADC16,
temp_CF);
}
void
BX_CPU_C::SUB_EwIw(BxInstruction_t *i)
{
Bit16u op2_16, op1_16, diff_16;
op2_16 = i->Iw;
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
}
diff_16 = op1_16 - op2_16;
/* now write diff back to destination */
if (i->mod == 0xc0) {
BX_WRITE_16BIT_REG(i->rm, diff_16);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_word(diff_16);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_SUB16);
}
void
BX_CPU_C::CMP_EwIw(BxInstruction_t *i)
{
Bit16u op2_16, op1_16, diff_16;
op2_16 = i->Iw;
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg, i->rm_addr, &op1_16);
}
diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, diff_16, BX_INSTR_CMP16);
}
void
BX_CPU_C::NEG_Ew(BxInstruction_t *i)
{
Bit16u op1_16, diff_16;
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
}
diff_16 = 0 - op1_16;
/* now write diff back to destination */
if (i->mod == 0xc0) {
BX_WRITE_16BIT_REG(i->rm, diff_16);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_word(diff_16);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_16(op1_16, 0, diff_16, BX_INSTR_NEG16);
}
void
BX_CPU_C::INC_Ew(BxInstruction_t *i)
{
Bit16u op1_16;
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
}
op1_16++;
/* now write sum back to destination */
if (i->mod == 0xc0) {
BX_WRITE_16BIT_REG(i->rm, op1_16);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_word(op1_16);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAP_16(0, 0, op1_16, BX_INSTR_INC16);
}
void
BX_CPU_C::DEC_Ew(BxInstruction_t *i)
{
Bit16u op1_16;
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
}
op1_16--;
/* now write sum back to destination */
if (i->mod == 0xc0) {
BX_WRITE_16BIT_REG(i->rm, op1_16);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_word(op1_16);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAP_16(0, 0, op1_16, BX_INSTR_DEC16);
}
void
BX_CPU_C::CMPXCHG_EwGw(BxInstruction_t *i)
{
#if (BX_CPU_LEVEL >= 4) || (BX_CPU_LEVEL_HACKED >= 4)
Bit16u op2_16, op1_16, diff_16;
/* op1_16 is a register or memory reference */
if (i->mod == 0xc0) {
op1_16 = BX_READ_16BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg, i->rm_addr, &op1_16);
}
diff_16 = AX - op1_16;
SET_FLAGS_OSZAPC_16(AX, op1_16, diff_16, BX_INSTR_CMP16);
if (diff_16 == 0) { // if accumulator == dest
// ZF = 1
set_ZF(1);
// dest <-- src
op2_16 = BX_READ_16BIT_REG(i->nnn);
if (i->mod == 0xc0) {
BX_WRITE_16BIT_REG(i->rm, op2_16);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_word(op2_16);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
}
else {
// ZF = 0
set_ZF(0);
// accumulator <-- dest
AX = op1_16;
}
#else
strip '\n' from BX_{INFO,DEBUG,ERROR,PANIC} don't need it, moved the output of it into the general io functions. saves space, as well as removes the confusing output if a '\n' is left off
2001-05-30 22:56:02 +04:00
BX_PANIC(("CMPXCHG_EwGw:"));
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
#endif
}
Reference in New Issue Copy Permalink