634 lines
20 KiB
C++
634 lines
20 KiB
C++
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// Copyright (C) 2000 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include "bochs.h"
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#define DMA_MODE_DEMAND 0
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#define DMA_MODE_SINGLE 1
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#define DMA_MODE_BLOCK 2
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#define DMA_MODE_CASCADE 3
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#if BX_USE_DMA_SMF
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bx_dma_c bx_dma;
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#define this (&bx_dma)
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#endif
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bx_dma_c::bx_dma_c(void)
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{
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}
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bx_dma_c::~bx_dma_c(void)
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{
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}
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void
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bx_dma_c::init(bx_devices_c *d)
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{
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unsigned c;
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BX_DMA_THIS devices = d;
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/* 8237 DMA controller */
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// 0000..000F
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unsigned i;
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for (i=0x0000; i<=0x000F; i++) {
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BX_DMA_THIS devices->register_io_read_handler(this, read_handler,
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i, "DMA controller");
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BX_DMA_THIS devices->register_io_write_handler(this, write_handler,
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i, "DMA controller");
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}
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// 00081..008D
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for (i=0x0081; i<=0x008D; i++) {
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BX_DMA_THIS devices->register_io_read_handler(this, read_handler,
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i, "DMA controller");
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BX_DMA_THIS devices->register_io_write_handler(this, write_handler,
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i, "DMA controller");
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}
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// 0008F..008F
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for (i=0x008F; i<=0x008F; i++) {
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BX_DMA_THIS devices->register_io_read_handler(this, read_handler,
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i, "DMA controller");
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BX_DMA_THIS devices->register_io_write_handler(this, write_handler,
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i, "DMA controller");
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}
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// 000C0..00DE
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for (i=0x00C0; i<=0x00DE; i++) {
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BX_DMA_THIS devices->register_io_read_handler(this, read_handler,
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i, "DMA controller");
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BX_DMA_THIS devices->register_io_write_handler(this, write_handler,
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i, "DMA controller");
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}
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BX_DMA_THIS s.mask[0] = 1; // channel 0 masked
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BX_DMA_THIS s.mask[1] = 1; // channel 1 masked
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BX_DMA_THIS s.mask[2] = 1; // channel 2 masked
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BX_DMA_THIS s.mask[3] = 1; // channel 3 masked
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BX_DMA_THIS s.flip_flop = 0; /* cleared */
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BX_DMA_THIS s.status_reg = 0; // no requests, no terminal counts reached
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for (c=0; c<4; c++) {
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BX_DMA_THIS s.chan[c].mode.mode_type = 0; // demand mode
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BX_DMA_THIS s.chan[c].mode.address_decrement = 0; // address increment
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BX_DMA_THIS s.chan[c].mode.autoinit_enable = 0; // autoinit disable
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BX_DMA_THIS s.chan[c].mode.transfer_type = 0; // verify
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BX_DMA_THIS s.chan[c].base_address = 0;
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BX_DMA_THIS s.chan[c].current_address = 0;
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BX_DMA_THIS s.chan[c].base_count = 0;
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BX_DMA_THIS s.chan[c].current_count = 0;
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BX_DMA_THIS s.chan[c].page_reg = 0;
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}
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}
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// index to find channel from register number (only [0],[1],[2],[6] used)
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Bit8u channelindex[7] = {2, 3, 1, 0, 0, 0, 0};
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// static IO port read callback handler
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// redirects to non-static class handler to avoid virtual functions
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Bit32u
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bx_dma_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
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{
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#if !BX_USE_DMA_SMF
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bx_dma_c *class_ptr = (bx_dma_c *) this_ptr;
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return( class_ptr->read(address, io_len) );
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}
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/* 8237 DMA controller */
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Bit32u
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bx_dma_c::read( Bit32u address, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_DMA_SMF
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Bit8u retval;
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Bit8u channel;
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if (io_len > 1) {
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bx_panic("dma: io read from address %08x, len=%u\n",
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(unsigned) address, (unsigned) io_len);
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}
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if (bx_dbg.dma)
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bx_printf("dma: read addr=%04x\n", (unsigned) address);
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#if BX_DMA_FLOPPY_IO < 1
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/* if we're not supporting DMA/floppy IO just return a bogus value */
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return(0xff);
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#endif
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switch (address) {
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case 0x00: /* DMA-1 current address, channel 0 */
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case 0x02: /* DMA-1 current address, channel 1 */
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case 0x04: /* DMA-1 current address, channel 2 */
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case 0x06: /* DMA-1 current address, channel 3 */
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channel = address >> 1;
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if (BX_DMA_THIS s.flip_flop==0) {
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BX_DMA_THIS s.flip_flop = !BX_DMA_THIS s.flip_flop;
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return(BX_DMA_THIS s.chan[channel].current_address & 0xff);
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}
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else {
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BX_DMA_THIS s.flip_flop = !BX_DMA_THIS s.flip_flop;
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return(BX_DMA_THIS s.chan[channel].current_address >> 8);
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}
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case 0x01: /* DMA-1 current count, channel 0 */
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case 0x03: /* DMA-1 current count, channel 1 */
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case 0x05: /* DMA-1 current count, channel 2 */
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case 0x07: /* DMA-1 current count, channel 3 */
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channel = address >> 1;
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if (BX_DMA_THIS s.flip_flop==0) {
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BX_DMA_THIS s.flip_flop = !BX_DMA_THIS s.flip_flop;
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return(BX_DMA_THIS s.chan[channel].current_count & 0xff);
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}
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else {
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BX_DMA_THIS s.flip_flop = !BX_DMA_THIS s.flip_flop;
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return(BX_DMA_THIS s.chan[channel].current_count >> 8);
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}
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case 0x08: // DMA-1 Status Register
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// bit 7: 1 = channel 3 request
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// bit 6: 1 = channel 2 request
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// bit 5: 1 = channel 1 request
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// bit 4: 1 = channel 0 request
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// bit 3: 1 = channel 3 has reached terminal count
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// bit 2: 1 = channel 2 has reached terminal count
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// bit 1: 1 = channel 1 has reached terminal count
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// bit 0: 1 = channel 0 has reached terminal count
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// reading this register clears lower 4 bits (hold flags)
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retval = BX_DMA_THIS s.status_reg;
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BX_DMA_THIS s.status_reg &= 0xf0;
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return(retval);
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break;
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case 0x0d: // dma-1: temporary register
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bx_panic("dma-1: read of temporary register\n");
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// Note: write to 0x0D clears temporary register
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return(0);
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break;
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case 0x0081: // DMA-1 page register, channel 2
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case 0x0082: // DMA-1 page register, channel 3
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case 0x0083: // DMA-1 page register, channel 1
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case 0x0087: // DMA-1 page register, channel 0
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channel = channelindex[address - 0x81];
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return( BX_DMA_THIS s.chan[channel].page_reg );
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case 0x0084: // ???
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return(0);
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case 0x0089: // DMA-2 page register, channel 6
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case 0x008a: // DMA-2 page register, channel 7
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case 0x008b: // DMA-2 page register, channel 5
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case 0x008f: // DMA-2 page register, channel 4
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channel = channelindex[address - 0x89] + 4;
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bx_printf("dma: read: unsupported address=%04x (channel %d)\n",
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(unsigned) address, channel);
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return( 0x00 );
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case 0x00c0:
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case 0x00c2:
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case 0x00c4:
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case 0x00c6:
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case 0x00c8:
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case 0x00ca:
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case 0x00cc:
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case 0x00ce:
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case 0x00d0:
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case 0x00d2:
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case 0x00d4:
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case 0x00d6:
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case 0x00d8:
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case 0x00da:
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case 0x00dc:
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case 0x00de:
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bx_printf("dma: read: unsupported address=%04x\n", (unsigned) address);
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return(0x0000);
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break;
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default:
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bx_panic("dma: read: unsupported address=%04x\n", (unsigned) address);
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return(0);
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}
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}
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// static IO port write callback handler
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// redirects to non-static class handler to avoid virtual functions
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void
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bx_dma_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
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{
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#if !BX_USE_DMA_SMF
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bx_dma_c *class_ptr = (bx_dma_c *) this_ptr;
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class_ptr->write(address, value, io_len);
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}
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/* 8237 DMA controller */
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void
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bx_dma_c::write(Bit32u address, Bit32u value, unsigned io_len)
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{
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#else
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UNUSED(this_ptr);
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#endif // !BX_USE_DMA_SMF
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Bit8u set_mask_bit;
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Bit8u channel;
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if (io_len > 1) {
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if ( (io_len == 2) && (address == 0x0b) ) {
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#if BX_USE_DMA_SMF
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BX_DMA_THIS write_handler(NULL, address, value & 0xff, 1);
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BX_DMA_THIS write_handler(NULL, address+1, value >> 8, 1);
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#else
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BX_DMA_THIS write(address, value & 0xff, 1);
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BX_DMA_THIS write(address+1, value >> 8, 1);
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#endif
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return;
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}
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bx_panic("dma: io write to address %08x, len=%u\n",
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(unsigned) address, (unsigned) io_len);
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}
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if (bx_dbg.dma)
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bx_printf("\ndma: write: address=%04x value=%02x\n",
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(unsigned) address, (unsigned) value);
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#if BX_DMA_FLOPPY_IO < 1
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/* if we're not supporting DMA/floppy IO just return */
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return;
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#endif
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switch (address) {
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case 0x00:
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case 0x02:
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case 0x04:
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case 0x06:
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channel = address >> 1;
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if (bx_dbg.dma)
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bx_printf(" DMA-1 base and current address, channel %d\n", channel);
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if (BX_DMA_THIS s.flip_flop==0) { /* 1st byte */
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BX_DMA_THIS s.chan[channel].base_address = value;
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BX_DMA_THIS s.chan[channel].current_address = value;
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}
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else { /* 2nd byte */
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BX_DMA_THIS s.chan[channel].base_address |= (value << 8);
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BX_DMA_THIS s.chan[channel].current_address |= (value << 8);
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if (bx_dbg.dma) {
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bx_printf(" base = %04x\n",
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(unsigned) BX_DMA_THIS s.chan[channel].base_address);
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bx_printf(" curr = %04x\n",
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(unsigned) BX_DMA_THIS s.chan[channel].current_address);
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}
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}
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BX_DMA_THIS s.flip_flop = !BX_DMA_THIS s.flip_flop;
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return;
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break;
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case 0x01:
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case 0x03:
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case 0x05:
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case 0x07:
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channel = address >> 1;
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if (bx_dbg.dma)
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bx_printf(" DMA-1 base and current count, channel %d\n", channel);
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if (BX_DMA_THIS s.flip_flop==0) { /* 1st byte */
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BX_DMA_THIS s.chan[channel].base_count = value;
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BX_DMA_THIS s.chan[channel].current_count = value;
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}
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else { /* 2nd byte */
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BX_DMA_THIS s.chan[channel].base_count |= (value << 8);
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BX_DMA_THIS s.chan[channel].current_count |= (value << 8);
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if (bx_dbg.dma) {
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bx_printf(" base = %04x\n",
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(unsigned) BX_DMA_THIS s.chan[channel].base_count);
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bx_printf(" curr = %04x\n",
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(unsigned) BX_DMA_THIS s.chan[channel].current_count);
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}
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}
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BX_DMA_THIS s.flip_flop = !BX_DMA_THIS s.flip_flop;
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return;
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break;
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case 0x08: /* DMA-1: command register */
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if (value != 0x04)
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bx_printf("DMA: write to 0008: value(%02xh) not 04h\n",
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(unsigned) value);
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BX_DMA_THIS s.command_reg = value;
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return;
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break;
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case 0x09: // DMA-1: request register
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bx_printf("DMA-1: write to request register (%02x)\n", (unsigned) value);
|
||
|
|
// note: write to 0x0d clears this register
|
||
|
|
if (value & 0x04) {
|
||
|
|
// set request bit
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
Bit8u channel;
|
||
|
|
|
||
|
|
// clear request bit
|
||
|
|
channel = value & 0x03;
|
||
|
|
BX_DMA_THIS s.status_reg &= ~(1 << (channel+4));
|
||
|
|
bx_printf("dma-1: cleared request bit for channel %u\n", (unsigned) channel);
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0x0a:
|
||
|
|
set_mask_bit = value & 0x04;
|
||
|
|
channel = value & 0x03;
|
||
|
|
BX_DMA_THIS s.mask[channel] = (set_mask_bit > 0);
|
||
|
|
if (bx_dbg.dma)
|
||
|
|
bx_printf("DMA1: set_mask_bit=%u, channel=%u, mask now=%02xh\n",
|
||
|
|
(unsigned) set_mask_bit, (unsigned) channel, (unsigned) BX_DMA_THIS s.mask[channel]);
|
||
|
|
return;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0x0b: /* dma-1 mode register */
|
||
|
|
channel = value & 0x03;
|
||
|
|
BX_DMA_THIS s.chan[channel].mode.mode_type = (value >> 6) & 0x03;
|
||
|
|
BX_DMA_THIS s.chan[channel].mode.address_decrement = (value >> 5) & 0x01;
|
||
|
|
BX_DMA_THIS s.chan[channel].mode.autoinit_enable = (value >> 4) & 0x01;
|
||
|
|
BX_DMA_THIS s.chan[channel].mode.transfer_type = (value >> 2) & 0x03;
|
||
|
|
//bx_printf("DMA1: mode register[%u] = %02x\n",
|
||
|
|
//(unsigned) channel, (unsigned) value);
|
||
|
|
if (bx_dbg.dma)
|
||
|
|
bx_printf("DMA1: mode register[%u] = %02x\n",
|
||
|
|
(unsigned) channel, (unsigned) value);
|
||
|
|
return;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0x0c: /* dma-1 clear byte flip/flop */
|
||
|
|
if (bx_dbg.dma)
|
||
|
|
bx_printf("DMA1: clear flip/flop\n");
|
||
|
|
BX_DMA_THIS s.flip_flop = 0;
|
||
|
|
return;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0x0d: // dma-1: master disable
|
||
|
|
/* ??? */
|
||
|
|
bx_printf("dma: master disable\n");
|
||
|
|
// writing any value to this port resets DMA controller 1
|
||
|
|
// same action as a hardware reset
|
||
|
|
// mask register is set (chan 0..3 disabled)
|
||
|
|
// command, status, request, temporary, and byte flip-flop are all cleared
|
||
|
|
BX_DMA_THIS s.mask[0] = 1;
|
||
|
|
BX_DMA_THIS s.mask[1] = 1;
|
||
|
|
BX_DMA_THIS s.mask[2] = 1;
|
||
|
|
BX_DMA_THIS s.mask[3] = 1;
|
||
|
|
BX_DMA_THIS s.command_reg = 0;
|
||
|
|
BX_DMA_THIS s.status_reg = 0;
|
||
|
|
BX_DMA_THIS s.request_reg = 0;
|
||
|
|
BX_DMA_THIS s.temporary_reg = 0;
|
||
|
|
BX_DMA_THIS s.flip_flop = 0;
|
||
|
|
return;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0x0e: // dma-1: clear mask register
|
||
|
|
bx_printf("dma-1: clear mask register\n");
|
||
|
|
BX_DMA_THIS s.mask[0] = 0;
|
||
|
|
BX_DMA_THIS s.mask[1] = 0;
|
||
|
|
BX_DMA_THIS s.mask[2] = 0;
|
||
|
|
BX_DMA_THIS s.mask[3] = 0;
|
||
|
|
return;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0x0f: // dma-1: write all mask bits
|
||
|
|
bx_printf("dma-1: write all mask bits\n");
|
||
|
|
BX_DMA_THIS s.mask[0] = value & 0x01; value >>= 1;
|
||
|
|
BX_DMA_THIS s.mask[1] = value & 0x01; value >>= 1;
|
||
|
|
BX_DMA_THIS s.mask[2] = value & 0x01; value >>= 1;
|
||
|
|
BX_DMA_THIS s.mask[3] = value & 0x01;
|
||
|
|
return;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0x81: /* dma page register, channel 2 */
|
||
|
|
case 0x82: /* dma page register, channel 3 */
|
||
|
|
case 0x83: /* dma page register, channel 1 */
|
||
|
|
case 0x87: /* dma page register, channel 0 */
|
||
|
|
/* address bits A16-A23 for DMA channel */
|
||
|
|
channel = channelindex[address - 0x81];
|
||
|
|
BX_DMA_THIS s.chan[channel].page_reg = value;
|
||
|
|
if (bx_dbg.dma)
|
||
|
|
bx_printf("DMA1: page register %d = %02x\n", channel, (unsigned) value);
|
||
|
|
return;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 0x0084: // ???
|
||
|
|
return;
|
||
|
|
break;
|
||
|
|
|
||
|
|
//case 0xd0: /* DMA-2 command register */
|
||
|
|
// if (value != 0x04)
|
||
|
|
// bx_printf("DMA2: write command register: value(%02xh)!=04h\n",
|
||
|
|
// (unsigned) value);
|
||
|
|
// return;
|
||
|
|
// break;
|
||
|
|
|
||
|
|
case 0x00c0:
|
||
|
|
case 0x00c2:
|
||
|
|
case 0x00c4:
|
||
|
|
case 0x00c6:
|
||
|
|
case 0x00c8:
|
||
|
|
case 0x00ca:
|
||
|
|
case 0x00cc:
|
||
|
|
case 0x00ce:
|
||
|
|
case 0x00d0:
|
||
|
|
case 0x00d2:
|
||
|
|
case 0x00d4:
|
||
|
|
case 0x00d6:
|
||
|
|
case 0x00d8:
|
||
|
|
case 0x00da:
|
||
|
|
case 0x00dc:
|
||
|
|
case 0x00de:
|
||
|
|
bx_printf("DMA(ignored): write: %04xh = %04xh\n",
|
||
|
|
(unsigned) address, (unsigned) value);
|
||
|
|
return;
|
||
|
|
break;
|
||
|
|
|
||
|
|
|
||
|
|
default:
|
||
|
|
bx_printf("DMA(ignored): write: %04xh = %02xh\n",
|
||
|
|
(unsigned) address, (unsigned) value);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
bx_dma_c::DRQ(unsigned channel, Boolean val)
|
||
|
|
{
|
||
|
|
Bit32u dma_base, dma_roof;
|
||
|
|
|
||
|
|
#if BX_SUPPORT_SB16
|
||
|
|
if ( (channel != 2) && (channel != (unsigned) BX_SB16_DMAL) )
|
||
|
|
bx_panic("bx_dma_c::DRQ(): channel %d != 2 or %d (SB16) (\n",
|
||
|
|
channel, BX_SB16_DMAL);
|
||
|
|
#else
|
||
|
|
if ( channel != 2 )
|
||
|
|
bx_panic("bx_dma_c::DRQ(): channel %d != 2\n",
|
||
|
|
channel);
|
||
|
|
#endif
|
||
|
|
if (!val) {
|
||
|
|
//bx_printf("bx_dma_c::DRQ(): val == 0\n");
|
||
|
|
// clear bit in status reg
|
||
|
|
// deassert HRQ if not pending DRQ's ?
|
||
|
|
// etc.
|
||
|
|
BX_DMA_THIS s.status_reg &= ~(1 << (channel+4));
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
#if 0
|
||
|
|
bx_printf("BX_DMA_THIS s.mask[2]: %02x\n", (unsigned) BX_DMA_THIS s.mask[2]);
|
||
|
|
bx_printf("BX_DMA_THIS s.flip_flop: %u\n", (unsigned) BX_DMA_THIS s.flip_flop);
|
||
|
|
bx_printf("BX_DMA_THIS s.status_reg: %02x\n", (unsigned) BX_DMA_THIS s.status_reg);
|
||
|
|
bx_printf("mode_type: %02x\n", (unsigned) BX_DMA_THIS s.chan[channel].mode.mode_type);
|
||
|
|
bx_printf("address_decrement: %02x\n", (unsigned) BX_DMA_THIS s.chan[channel].mode.address_decrement);
|
||
|
|
bx_printf("autoinit_enable: %02x\n", (unsigned) BX_DMA_THIS s.chan[channel].mode.autoinit_enable);
|
||
|
|
bx_printf("transfer_type: %02x\n", (unsigned) BX_DMA_THIS s.chan[channel].mode.transfer_type);
|
||
|
|
bx_printf(".base_address: %04x\n", (unsigned) BX_DMA_THIS s.chan[channel].base_address);
|
||
|
|
bx_printf(".current_address: %04x\n", (unsigned) BX_DMA_THIS s.chan[channel].current_address);
|
||
|
|
bx_printf(".base_count: %04x\n", (unsigned) BX_DMA_THIS s.chan[channel].base_count);
|
||
|
|
bx_printf(".current_count: %04x\n", (unsigned) BX_DMA_THIS s.chan[channel].current_count);
|
||
|
|
bx_printf(".page_reg: %02x\n", (unsigned) BX_DMA_THIS s.chan[channel].page_reg);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
BX_DMA_THIS s.status_reg |= (1 << (channel+4));
|
||
|
|
|
||
|
|
// if (BX_DMA_THIS s.mask[channel])
|
||
|
|
// bx_panic("bx_dma_c::DRQ(): BX_DMA_THIS s.mask[] is set\n");
|
||
|
|
|
||
|
|
|
||
|
|
if ( (BX_DMA_THIS s.chan[channel].mode.mode_type != DMA_MODE_SINGLE) &&
|
||
|
|
(BX_DMA_THIS s.chan[channel].mode.mode_type != DMA_MODE_DEMAND) )
|
||
|
|
bx_panic("bx_dma_c::DRQ: mode_type(%02x) not handled\n",
|
||
|
|
(unsigned) BX_DMA_THIS s.chan[channel].mode.mode_type);
|
||
|
|
if (BX_DMA_THIS s.chan[channel].mode.address_decrement != 0)
|
||
|
|
bx_panic("bx_dma_c::DRQ: address_decrement != 0\n");
|
||
|
|
//if (BX_DMA_THIS s.chan[channel].mode.autoinit_enable != 0)
|
||
|
|
// bx_panic("bx_dma_c::DRQ: autoinit_enable != 0\n");
|
||
|
|
|
||
|
|
dma_base = (BX_DMA_THIS s.chan[channel].page_reg << 16) | BX_DMA_THIS s.chan[channel].base_address;
|
||
|
|
dma_roof = dma_base + BX_DMA_THIS s.chan[channel].base_count;
|
||
|
|
if ( (dma_base & 0xffff0000) != (dma_roof & 0xffff0000) ) {
|
||
|
|
bx_printf("dma_base = %08x\n", (unsigned) dma_base);
|
||
|
|
bx_printf("dma_base_count = %08x\n", (unsigned) BX_DMA_THIS s.chan[channel].base_count);
|
||
|
|
bx_printf("dma_roof = %08x\n", (unsigned) dma_roof);
|
||
|
|
bx_panic("dma: DMA request outside 64k boundary\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
//bx_printf("DRQ set up for single mode, increment, auto-init disabled, write\n");
|
||
|
|
// should check mask register VS DREQ's in status register here?
|
||
|
|
// assert Hold ReQuest line to CPU
|
||
|
|
bx_pc_system.set_HRQ(1);
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
bx_dma_c::raise_HLDA(bx_pc_system_c *pc_sys)
|
||
|
|
{
|
||
|
|
unsigned channel;
|
||
|
|
Bit32u phy_addr;
|
||
|
|
Boolean count_expired = 0;
|
||
|
|
|
||
|
|
// find highest priority channel
|
||
|
|
for (channel=0; channel<4; channel++) {
|
||
|
|
if ( (BX_DMA_THIS s.status_reg & (1 << (channel+4))) &&
|
||
|
|
(BX_DMA_THIS s.mask[channel]==0) ) {
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if (channel >= 4) {
|
||
|
|
// don't panic, just wait till they're unmasked
|
||
|
|
// bx_panic("hlda: no unmasked requests\n");
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
//bx_printf("hlda: OK in response to DRQ(%u)\n", (unsigned) channel);
|
||
|
|
phy_addr = (BX_DMA_THIS s.chan[channel].page_reg << 16) |
|
||
|
|
BX_DMA_THIS s.chan[channel].current_address;
|
||
|
|
|
||
|
|
bx_pc_system.set_DACK(channel, 1);
|
||
|
|
// check for expiration of count, so we can signal TC and DACK(n)
|
||
|
|
// at the same time.
|
||
|
|
if (BX_DMA_THIS s.chan[channel].mode.address_decrement==0) {
|
||
|
|
// address increment
|
||
|
|
BX_DMA_THIS s.chan[channel].current_address++;
|
||
|
|
BX_DMA_THIS s.chan[channel].current_count--;
|
||
|
|
if (BX_DMA_THIS s.chan[channel].current_count == 0xffff)
|
||
|
|
if (BX_DMA_THIS s.chan[channel].mode.autoinit_enable == 0) {
|
||
|
|
// count expired, done with transfer
|
||
|
|
// assert TC, deassert HRQ & DACK(n) lines
|
||
|
|
BX_DMA_THIS s.status_reg |= (1 << channel); // hold TC in status reg
|
||
|
|
bx_pc_system.set_TC(1);
|
||
|
|
count_expired = 1;
|
||
|
|
} else {
|
||
|
|
// count expired, but in autoinit mode
|
||
|
|
// reload count and base address
|
||
|
|
BX_DMA_THIS s.chan[channel].current_address =
|
||
|
|
BX_DMA_THIS s.chan[channel].base_address;
|
||
|
|
BX_DMA_THIS s.chan[channel].current_count =
|
||
|
|
BX_DMA_THIS s.chan[channel].base_count;
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
// address decrement
|
||
|
|
bx_panic("hlda: decrement not implemented\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
if (BX_DMA_THIS s.chan[channel].mode.transfer_type == 1) { // write
|
||
|
|
// xfer from I/O to Memory
|
||
|
|
pc_sys->dma_write8(phy_addr, channel);
|
||
|
|
}
|
||
|
|
else if (BX_DMA_THIS s.chan[channel].mode.transfer_type == 2) { // read
|
||
|
|
// xfer from Memory to I/O
|
||
|
|
pc_sys->dma_read8(phy_addr, channel);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
bx_panic("hlda: transfer_type of %u not handled\n",
|
||
|
|
(unsigned) BX_DMA_THIS s.chan[channel].mode.transfer_type);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (count_expired) {
|
||
|
|
bx_pc_system.set_TC(0); // clear TC, adapter card already notified
|
||
|
|
bx_pc_system.set_HRQ(0); // clear HRQ to CPU
|
||
|
|
bx_pc_system.set_DACK(channel, 0); // clear DACK to adapter card
|
||
|
|
}
|
||
|
|
}
|