2019-10-26 23:09:30 +03:00
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/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2019 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_MSR_H
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#define BX_MSR_H
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enum MSR_Register {
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BX_MSR_TSC = 0x010,
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BX_MSR_APICBASE = 0x01b,
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BX_MSR_TSC_ADJUST = 0x03b,
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BX_MSR_TSC_DEADLINE = 0x6E0,
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BX_MSR_IA32_SPEC_CTRL = 0x048,
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BX_MSR_IA32_PRED_CMD = 0x049,
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BX_MSR_IA32_ARCH_CAPABILITIES = 0x10a,
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BX_MSR_IA32_FLUSH_CMD = 0x10b,
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#if BX_CPU_LEVEL >= 6
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BX_MSR_SYSENTER_CS = 0x174,
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BX_MSR_SYSENTER_ESP = 0x175,
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BX_MSR_SYSENTER_EIP = 0x176,
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#endif
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BX_MSR_DEBUGCTLMSR = 0x1d9,
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BX_MSR_LASTBRANCHFROMIP = 0x1db,
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BX_MSR_LASTBRANCHTOIP = 0x1dc,
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BX_MSR_LASTINTOIP = 0x1dd,
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#if BX_CPU_LEVEL >= 6
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BX_MSR_MTRRCAP = 0x0fe,
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BX_MSR_MTRRPHYSBASE0 = 0x200,
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BX_MSR_MTRRPHYSMASK0 = 0x201,
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BX_MSR_MTRRPHYSBASE1 = 0x202,
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BX_MSR_MTRRPHYSMASK1 = 0x203,
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BX_MSR_MTRRPHYSBASE2 = 0x204,
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BX_MSR_MTRRPHYSMASK2 = 0x205,
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BX_MSR_MTRRPHYSBASE3 = 0x206,
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BX_MSR_MTRRPHYSMASK3 = 0x207,
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BX_MSR_MTRRPHYSBASE4 = 0x208,
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BX_MSR_MTRRPHYSMASK4 = 0x209,
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BX_MSR_MTRRPHYSBASE5 = 0x20a,
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BX_MSR_MTRRPHYSMASK5 = 0x20b,
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BX_MSR_MTRRPHYSBASE6 = 0x20c,
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BX_MSR_MTRRPHYSMASK6 = 0x20d,
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BX_MSR_MTRRPHYSBASE7 = 0x20e,
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BX_MSR_MTRRPHYSMASK7 = 0x20f,
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BX_MSR_MTRRFIX64K_00000 = 0x250,
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BX_MSR_MTRRFIX16K_80000 = 0x258,
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BX_MSR_MTRRFIX16K_A0000 = 0x259,
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BX_MSR_MTRRFIX4K_C0000 = 0x268,
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BX_MSR_MTRRFIX4K_C8000 = 0x269,
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BX_MSR_MTRRFIX4K_D0000 = 0x26a,
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BX_MSR_MTRRFIX4K_D8000 = 0x26b,
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BX_MSR_MTRRFIX4K_E0000 = 0x26c,
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BX_MSR_MTRRFIX4K_E8000 = 0x26d,
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BX_MSR_MTRRFIX4K_F0000 = 0x26e,
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BX_MSR_MTRRFIX4K_F8000 = 0x26f,
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BX_MSR_PAT = 0x277,
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BX_MSR_MTRR_DEFTYPE = 0x2ff,
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#endif
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#if BX_SUPPORT_PERFMON
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BX_MSR_PMC0 = 0x0c1, /* PERFCTR0 */
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BX_MSR_PMC1 = 0x0c2, /* PERFCTR1 */
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BX_MSR_PMC2 = 0x0c3,
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BX_MSR_PMC3 = 0x0c4,
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BX_MSR_PMC4 = 0x0c5,
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BX_MSR_PMC5 = 0x0c6,
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BX_MSR_PMC6 = 0x0c7,
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BX_MSR_PMC7 = 0x0c8,
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BX_MSR_PERFEVTSEL0 = 0x186,
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BX_MSR_PERFEVTSEL1 = 0x187,
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BX_MSR_PERFEVTSEL2 = 0x188,
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BX_MSR_PERFEVTSEL3 = 0x189,
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BX_MSR_PERFEVTSEL4 = 0x18a,
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BX_MSR_PERFEVTSEL5 = 0x18b,
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BX_MSR_PERFEVTSEL6 = 0x18c,
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BX_MSR_PERFEVTSEL7 = 0x18d,
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BX_MSR_PERF_FIXED_CTR0 = 0x309, /* Fixed Performance Counter 0 (R/W): Counts Instr_Retired.Any */
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BX_MSR_PERF_FIXED_CTR1 = 0x30a, /* Fixed Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core */
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BX_MSR_PERF_FIXED_CTR2 = 0x30b, /* Fixed Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref */
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BX_MSR_FIXED_CTR_CTRL = 0x38d, /* Fixed Performance Counter Control (R/W) */
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BX_MSR_PERF_GLOBAL_CTRL = 0x38f, /* Global Performance Counter Control */
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#endif
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#if BX_SUPPORT_VMX
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BX_MSR_VMX_BASIC = 0x480,
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BX_MSR_VMX_PINBASED_CTRLS = 0x481,
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BX_MSR_VMX_PROCBASED_CTRLS = 0x482,
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BX_MSR_VMX_VMEXIT_CTRLS = 0x483,
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BX_MSR_VMX_VMENTRY_CTRLS = 0x484,
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BX_MSR_VMX_MISC = 0x485,
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BX_MSR_VMX_CR0_FIXED0 = 0x486,
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BX_MSR_VMX_CR0_FIXED1 = 0x487,
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BX_MSR_VMX_CR4_FIXED0 = 0x488,
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BX_MSR_VMX_CR4_FIXED1 = 0x489,
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BX_MSR_VMX_VMCS_ENUM = 0x48a,
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BX_MSR_VMX_PROCBASED_CTRLS2 = 0x48b,
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BX_MSR_VMX_EPT_VPID_CAP = 0x48c,
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BX_MSR_VMX_TRUE_PINBASED_CTRLS = 0x48d,
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BX_MSR_VMX_TRUE_PROCBASED_CTRLS = 0x48e,
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BX_MSR_VMX_TRUE_VMEXIT_CTRLS = 0x48f,
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BX_MSR_VMX_TRUE_VMENTRY_CTRLS = 0x490,
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BX_MSR_VMX_VMFUNC = 0x491,
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BX_MSR_IA32_FEATURE_CONTROL = 0x03A,
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BX_MSR_IA32_SMM_MONITOR_CTL = 0x09B,
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#endif
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BX_MSR_XSS = 0xda0,
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2019-11-26 20:39:09 +03:00
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/* AMD MSRs */
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2019-10-26 23:09:30 +03:00
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BX_MSR_EFER = 0xc0000080,
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BX_MSR_STAR = 0xc0000081,
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BX_MSR_LSTAR = 0xc0000082,
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BX_MSR_CSTAR = 0xc0000083,
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BX_MSR_FMASK = 0xc0000084,
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BX_MSR_FSBASE = 0xc0000100,
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BX_MSR_GSBASE = 0xc0000101,
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BX_MSR_KERNELGSBASE = 0xc0000102,
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BX_MSR_TSC_AUX = 0xc0000103,
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BX_SVM_VM_CR_MSR = 0xc0010114,
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BX_SVM_IGNNE_MSR = 0xc0010115,
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BX_SVM_SMM_CTL_MSR = 0xc0010116,
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BX_SVM_HSAVE_PA_MSR = 0xc0010117,
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};
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const unsigned BX_NUM_VARIABLE_RANGE_MTRRS = 8;
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#endif // #ifndef BX_MSR_H
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