mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
7db6c647b0
Bochs/bochs/cpu/fetchdecode_evex.h

1736 lines
63 KiB
C
Raw Normal View History

added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2013 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
//
/////////////////////////////////////////////////////////////////////////
#ifndef BX_EVEX_FETCHDECODE_TABLES_H
#define BX_EVEX_FETCHDECODE_TABLES_H
#if BX_SUPPORT_EVEX
implemented avx-512 fma instructions (in seperate file), fixes in avx-512 decoding tables
2013-11-26 00:42:24 +04:00
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f14[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VUNPCKLPS_VpsHpsWps },
/* 66 */ { BxVexW1, BX_IA_V512_VUNPCKLPD_VpdHpdWpd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f14_Mask[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VUNPCKLPS_VpsHpsWps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VUNPCKLPD_VpdHpdWpd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f15[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VUNPCKHPS_VpsHpsWps },
/* 66 */ { BxVexW1, BX_IA_V512_VUNPCKHPD_VpdHpdWpd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f15_Mask[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VUNPCKHPS_VpsHpsWps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VUNPCKHPD_VpdHpdWpd_Kmask }
};
implemented avx-512 masked register moves
2013-11-29 00:58:31 +04:00
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f28[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VMOVAPS_VpsWps },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVAPD_VpdWpd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f28_Mask[2] = {
Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions Fix vector length values for AVX-512 (512-bit vector should have length 4) support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions move AVX512 load/store and register move operations into dedicated file avx512_move.cc
2013-11-30 00:22:31 +04:00
/* -- */ { BxVexW0, BX_IA_V512_VMOVAPS_VpsWps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVAPD_VpdWpd_Kmask }
implemented avx-512 masked register moves
2013-11-29 00:58:31 +04:00
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f29[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VMOVAPS_WpsVps },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVAPD_WpdVpd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f29_Mask[2] = {
Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions Fix vector length values for AVX-512 (512-bit vector should have length 4) support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions move AVX512 load/store and register move operations into dedicated file avx512_move.cc
2013-11-30 00:22:31 +04:00
/* -- */ { BxVexW0, BX_IA_V512_VMOVAPS_WpsVps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VMOVAPD_WpdVpd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f2e[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VUCOMISS_VssWss },
/* 66 */ { BxVexW1, BX_IA_V512_VUCOMISD_VsdWsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f2f[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VCOMISS_VssWss },
/* 66 */ { BxVexW1, BX_IA_V512_VCOMISD_VsdWsd }
implemented avx-512 masked register moves
2013-11-29 00:58:31 +04:00
};
implemented avx-512 fma instructions (in seperate file), fixes in avx-512 decoding tables
2013-11-26 00:42:24 +04:00
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f58[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VADDPS_VpsHpsWps },
/* 66 */ { BxVexW1, BX_IA_V512_VADDPD_VpdHpdWpd },
/* F3 */ { BxVexW0, BX_IA_V512_VADDSS_VssHpsWss },
/* F2 */ { BxVexW1, BX_IA_V512_VADDSD_VsdHpdWsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f58_Mask[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VADDPS_VpsHpsWps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VADDPD_VpdHpdWpd_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VADDSS_VssHpsWss_Kmask },
/* F2 */ { BxVexW1, BX_IA_V512_VADDSD_VsdHpdWsd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f59[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VMULPS_VpsHpsWps },
/* 66 */ { BxVexW1, BX_IA_V512_VMULPD_VpdHpdWpd },
/* F3 */ { BxVexW0, BX_IA_V512_VMULSS_VssHpsWss },
/* F2 */ { BxVexW1, BX_IA_V512_VMULSD_VsdHpdWsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f59_Mask[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VMULPS_VpsHpsWps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VMULPD_VpdHpdWpd_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VMULSS_VssHpsWss_Kmask },
/* F2 */ { BxVexW1, BX_IA_V512_VMULSD_VsdHpdWsd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f5c[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VSUBPS_VpsHpsWps },
/* 66 */ { BxVexW1, BX_IA_V512_VSUBPD_VpdHpdWpd },
/* F3 */ { BxVexW0, BX_IA_V512_VSUBSS_VssHpsWss },
/* F2 */ { BxVexW1, BX_IA_V512_VSUBSD_VsdHpdWsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f5c_Mask[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VSUBPS_VpsHpsWps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VSUBPD_VpdHpdWpd_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VSUBSS_VssHpsWss_Kmask },
/* F2 */ { BxVexW1, BX_IA_V512_VSUBSD_VsdHpdWsd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f5d[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VMINPS_VpsHpsWps },
/* 66 */ { BxVexW1, BX_IA_V512_VMINPD_VpdHpdWpd },
/* F3 */ { BxVexW0, BX_IA_V512_VMINSS_VssHpsWss },
/* F2 */ { BxVexW1, BX_IA_V512_VMINSD_VsdHpdWsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f5d_Mask[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VMINPS_VpsHpsWps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VMINPD_VpdHpdWpd_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VMINSS_VssHpsWss_Kmask },
/* F2 */ { BxVexW1, BX_IA_V512_VMINSD_VsdHpdWsd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f5e[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VDIVPS_VpsHpsWps },
/* 66 */ { BxVexW1, BX_IA_V512_VDIVPD_VpdHpdWpd },
/* F3 */ { BxVexW0, BX_IA_V512_VDIVSS_VssHpsWss },
/* F2 */ { BxVexW1, BX_IA_V512_VDIVSD_VsdHpdWsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f5e_Mask[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VDIVPS_VpsHpsWps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VDIVPD_VpdHpdWpd_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VDIVSS_VssHpsWss_Kmask },
/* F2 */ { BxVexW1, BX_IA_V512_VDIVSD_VsdHpdWsd_Kmask }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f5f[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VMAXPS_VpsHpsWps },
/* 66 */ { BxVexW1, BX_IA_V512_VMAXPD_VpdHpdWpd },
/* F3 */ { BxVexW0, BX_IA_V512_VMAXSS_VssHpsWss },
/* F2 */ { BxVexW1, BX_IA_V512_VMAXSD_VsdHpdWsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f5f_Mask[4] = {
/* -- */ { BxVexW0, BX_IA_V512_VMAXPS_VpsHpsWps_Kmask },
/* 66 */ { BxVexW1, BX_IA_V512_VMAXPD_VpdHpdWpd_Kmask },
/* F3 */ { BxVexW0, BX_IA_V512_VMAXSS_VssHpsWss_Kmask },
/* F2 */ { BxVexW1, BX_IA_V512_VMAXSD_VsdHpdWsd_Kmask }
};
Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions Fix vector length values for AVX-512 (512-bit vector should have length 4) support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions move AVX512 load/store and register move operations into dedicated file avx512_move.cc
2013-11-30 00:22:31 +04:00
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f6f[3] = {
/* 66 */ { BxAliasVexW, BX_IA_V512_VMOVDQA32_VdqWdq },
/* F3 */ { BxAliasVexW, BX_IA_V512_VMOVDQU32_VdqWdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f6f_Mask[3] = {
/* 66 */ { BxAliasVexW, BX_IA_V512_VMOVDQA32_VdqWdq_Kmask },
/* F3 */ { BxAliasVexW, BX_IA_V512_VMOVDQU32_VdqWdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f7f[3] = {
/* 66 */ { BxAliasVexW, BX_IA_V512_VMOVDQA32_WdqVdq },
/* F3 */ { BxAliasVexW, BX_IA_V512_VMOVDQU32_WdqVdq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f7f_Mask[3] = {
/* 66 */ { BxAliasVexW, BX_IA_V512_VMOVDQA32_WdqVdq_Kmask },
/* F3 */ { BxAliasVexW, BX_IA_V512_VMOVDQU32_WdqVdq_Kmask },
/* F2 */ { 0, BX_IA_ERROR }
};
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* ************************************************************************ */
static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
// 256 entries for EVEX-encoded 0x0F opcodes
/* 00 k0 */ { 0, BX_IA_ERROR },
/* 00 */ { 0, BX_IA_ERROR },
/* 01 k0 */ { 0, BX_IA_ERROR },
/* 01 */ { 0, BX_IA_ERROR },
/* 02 k0 */ { 0, BX_IA_ERROR },
/* 02 */ { 0, BX_IA_ERROR },
/* 03 k0 */ { 0, BX_IA_ERROR },
/* 03 */ { 0, BX_IA_ERROR },
/* 04 k0 */ { 0, BX_IA_ERROR },
/* 04 */ { 0, BX_IA_ERROR },
/* 05 k0 */ { 0, BX_IA_ERROR },
/* 05 */ { 0, BX_IA_ERROR },
/* 06 k0 */ { 0, BX_IA_ERROR },
/* 06 */ { 0, BX_IA_ERROR },
/* 07 k0 */ { 0, BX_IA_ERROR },
/* 07 */ { 0, BX_IA_ERROR },
/* 08 k0 */ { 0, BX_IA_ERROR },
/* 08 */ { 0, BX_IA_ERROR },
/* 09 k0 */ { 0, BX_IA_ERROR },
/* 09 */ { 0, BX_IA_ERROR },
/* 0A k0 */ { 0, BX_IA_ERROR },
/* 0A */ { 0, BX_IA_ERROR },
/* 0B k0 */ { 0, BX_IA_ERROR },
/* 0B */ { 0, BX_IA_ERROR },
/* 0C k0 */ { 0, BX_IA_ERROR },
/* 0C */ { 0, BX_IA_ERROR },
/* 0D k0 */ { 0, BX_IA_ERROR },
/* 0D */ { 0, BX_IA_ERROR },
/* 0E k0 */ { 0, BX_IA_ERROR },
/* 0E */ { 0, BX_IA_ERROR },
/* 0F k0 */ { 0, BX_IA_ERROR },
/* 0F */ { 0, BX_IA_ERROR },
/* 10 k0 */ { 0, BX_IA_ERROR },
/* 10 */ { 0, BX_IA_ERROR },
/* 11 k0 */ { 0, BX_IA_ERROR },
/* 11 */ { 0, BX_IA_ERROR },
/* 12 k0 */ { 0, BX_IA_ERROR },
/* 12 */ { 0, BX_IA_ERROR },
/* 13 k0 */ { 0, BX_IA_ERROR },
/* 13 */ { 0, BX_IA_ERROR },
implemented avx-512 fma instructions (in seperate file), fixes in avx-512 decoding tables
2013-11-26 00:42:24 +04:00
/* 14 k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f14 },
/* 14 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f14_Mask },
/* 15 k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f15 },
/* 15 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f15_Mask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 16 k0 */ { 0, BX_IA_ERROR },
/* 16 */ { 0, BX_IA_ERROR },
/* 17 k0 */ { 0, BX_IA_ERROR },
/* 17 */ { 0, BX_IA_ERROR },
/* 18 k0 */ { 0, BX_IA_ERROR },
/* 18 */ { 0, BX_IA_ERROR },
/* 19 k0 */ { 0, BX_IA_ERROR },
/* 19 */ { 0, BX_IA_ERROR },
/* 1A k0 */ { 0, BX_IA_ERROR },
/* 1A */ { 0, BX_IA_ERROR },
/* 1B k0 */ { 0, BX_IA_ERROR },
/* 1B */ { 0, BX_IA_ERROR },
/* 1C k0 */ { 0, BX_IA_ERROR },
/* 1C */ { 0, BX_IA_ERROR },
/* 1D k0 */ { 0, BX_IA_ERROR },
/* 1D */ { 0, BX_IA_ERROR },
/* 1E k0 */ { 0, BX_IA_ERROR },
/* 1E */ { 0, BX_IA_ERROR },
/* 1F k0 */ { 0, BX_IA_ERROR },
/* 1F */ { 0, BX_IA_ERROR },
/* 20 k0 */ { 0, BX_IA_ERROR },
/* 20 */ { 0, BX_IA_ERROR },
/* 21 k0 */ { 0, BX_IA_ERROR },
/* 21 */ { 0, BX_IA_ERROR },
/* 22 k0 */ { 0, BX_IA_ERROR },
/* 22 */ { 0, BX_IA_ERROR },
/* 23 k0 */ { 0, BX_IA_ERROR },
/* 23 */ { 0, BX_IA_ERROR },
/* 24 k0 */ { 0, BX_IA_ERROR },
/* 24 */ { 0, BX_IA_ERROR },
/* 25 k0 */ { 0, BX_IA_ERROR },
/* 25 */ { 0, BX_IA_ERROR },
/* 26 k0 */ { 0, BX_IA_ERROR },
/* 26 */ { 0, BX_IA_ERROR },
/* 27 k0 */ { 0, BX_IA_ERROR },
/* 27 */ { 0, BX_IA_ERROR },
implemented avx-512 masked register moves
2013-11-29 00:58:31 +04:00
/* 28 k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f28 },
/* 28 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f28_Mask },
/* 29 k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f29 },
/* 29 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f29_Mask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 2A k0 */ { 0, BX_IA_ERROR },
/* 2A */ { 0, BX_IA_ERROR },
/* 2B k0 */ { 0, BX_IA_ERROR },
/* 2B */ { 0, BX_IA_ERROR },
/* 2C k0 */ { 0, BX_IA_ERROR },
/* 2C */ { 0, BX_IA_ERROR },
/* 2D k0 */ { 0, BX_IA_ERROR },
/* 2D */ { 0, BX_IA_ERROR },
Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions Fix vector length values for AVX-512 (512-bit vector should have length 4) support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions move AVX512 load/store and register move operations into dedicated file avx512_move.cc
2013-11-30 00:22:31 +04:00
/* 2E k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f2e },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 2E */ { 0, BX_IA_ERROR },
Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions Fix vector length values for AVX-512 (512-bit vector should have length 4) support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions move AVX512 load/store and register move operations into dedicated file avx512_move.cc
2013-11-30 00:22:31 +04:00
/* 2F k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f2f },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 2F */ { 0, BX_IA_ERROR },
/* 30 k0 */ { 0, BX_IA_ERROR },
/* 30 */ { 0, BX_IA_ERROR },
/* 31 k0 */ { 0, BX_IA_ERROR },
/* 31 */ { 0, BX_IA_ERROR },
/* 32 k0 */ { 0, BX_IA_ERROR },
/* 32 */ { 0, BX_IA_ERROR },
/* 33 k0 */ { 0, BX_IA_ERROR },
/* 33 */ { 0, BX_IA_ERROR },
/* 34 k0 */ { 0, BX_IA_ERROR },
/* 34 */ { 0, BX_IA_ERROR },
/* 35 k0 */ { 0, BX_IA_ERROR },
/* 35 */ { 0, BX_IA_ERROR },
/* 36 k0 */ { 0, BX_IA_ERROR },
/* 36 */ { 0, BX_IA_ERROR },
/* 37 k0 */ { 0, BX_IA_ERROR },
/* 37 */ { 0, BX_IA_ERROR },
/* 38 k0 */ { 0, BX_IA_ERROR }, // 3-Byte Escape
/* 38 */ { 0, BX_IA_ERROR }, // 3-Byte Escape
more avx512 instructions done
2013-10-09 23:45:36 +04:00
/* 39 k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPMINSD_VdqHdqWdq },
/* 39 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPMINSD_VdqHdqWdq_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 3A k0 */ { 0, BX_IA_ERROR }, // 3-Byte Escape
/* 3A */ { 0, BX_IA_ERROR }, // 3-Byte Escape
more avx512 instructions done
2013-10-09 23:45:36 +04:00
/* 3B k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPMINUD_VdqHdqWdq },
/* 3B */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPMINUD_VdqHdqWdq_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 3C k0 */ { 0, BX_IA_ERROR },
/* 3C */ { 0, BX_IA_ERROR },
more avx512 instructions done
2013-10-09 23:45:36 +04:00
/* 3D k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPMAXSD_VdqHdqWdq },
/* 3D */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPMAXSD_VdqHdqWdq_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 3E k0 */ { 0, BX_IA_ERROR },
/* 3E */ { 0, BX_IA_ERROR },
more avx512 instructions done
2013-10-09 23:45:36 +04:00
/* 3F k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPMAXUD_VdqHdqWdq },
/* 3F */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPMAXUD_VdqHdqWdq_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 40 k0 */ { 0, BX_IA_ERROR },
/* 40 */ { 0, BX_IA_ERROR },
/* 41 k0 */ { 0, BX_IA_ERROR },
/* 41 */ { 0, BX_IA_ERROR },
/* 42 k0 */ { 0, BX_IA_ERROR },
/* 42 */ { 0, BX_IA_ERROR },
/* 43 k0 */ { 0, BX_IA_ERROR },
/* 43 */ { 0, BX_IA_ERROR },
/* 44 k0 */ { 0, BX_IA_ERROR },
/* 44 */ { 0, BX_IA_ERROR },
/* 45 k0 */ { 0, BX_IA_ERROR },
/* 45 */ { 0, BX_IA_ERROR },
/* 46 k0 */ { 0, BX_IA_ERROR },
/* 46 */ { 0, BX_IA_ERROR },
/* 47 k0 */ { 0, BX_IA_ERROR },
/* 47 */ { 0, BX_IA_ERROR },
/* 48 k0 */ { 0, BX_IA_ERROR },
/* 48 */ { 0, BX_IA_ERROR },
/* 49 k0 */ { 0, BX_IA_ERROR },
/* 49 */ { 0, BX_IA_ERROR },
/* 4A k0 */ { 0, BX_IA_ERROR },
/* 4A */ { 0, BX_IA_ERROR },
/* 4B k0 */ { 0, BX_IA_ERROR },
/* 4B */ { 0, BX_IA_ERROR },
/* 4C k0 */ { 0, BX_IA_ERROR },
/* 4C */ { 0, BX_IA_ERROR },
/* 4D k0 */ { 0, BX_IA_ERROR },
/* 4D */ { 0, BX_IA_ERROR },
/* 4E k0 */ { 0, BX_IA_ERROR },
/* 4E */ { 0, BX_IA_ERROR },
/* 4F k0 */ { 0, BX_IA_ERROR },
/* 4F */ { 0, BX_IA_ERROR },
/* 50 k0 */ { 0, BX_IA_ERROR },
/* 50 */ { 0, BX_IA_ERROR },
/* 51 k0 */ { 0, BX_IA_ERROR },
/* 51 */ { 0, BX_IA_ERROR },
/* 52 k0 */ { 0, BX_IA_ERROR },
/* 52 */ { 0, BX_IA_ERROR },
/* 53 k0 */ { 0, BX_IA_ERROR },
/* 53 */ { 0, BX_IA_ERROR },
/* 54 k0 */ { 0, BX_IA_ERROR },
/* 54 */ { 0, BX_IA_ERROR },
/* 55 k0 */ { 0, BX_IA_ERROR },
/* 55 */ { 0, BX_IA_ERROR },
/* 56 k0 */ { 0, BX_IA_ERROR },
/* 56 */ { 0, BX_IA_ERROR },
/* 57 k0 */ { 0, BX_IA_ERROR },
/* 57 */ { 0, BX_IA_ERROR },
implemented avx-512 fma instructions (in seperate file), fixes in avx-512 decoding tables
2013-11-26 00:42:24 +04:00
/* 58 k0 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f58 },
/* 58 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f58_Mask },
/* 59 k0 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f59 },
/* 59 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f59_Mask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 5A k0 */ { 0, BX_IA_ERROR },
/* 5A */ { 0, BX_IA_ERROR },
/* 5B k0 */ { 0, BX_IA_ERROR },
/* 5B */ { 0, BX_IA_ERROR },
implemented avx-512 fma instructions (in seperate file), fixes in avx-512 decoding tables
2013-11-26 00:42:24 +04:00
/* 5C k0 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f5c },
/* 5C */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f5c_Mask },
/* 5D k0 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f5d },
/* 5D */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f5d_Mask },
/* 5E k0 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f5e },
/* 5E */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f5e_Mask },
/* 5F k0 */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f5f },
/* 5F */ { BxPrefixSSE4, BX_IA_ERROR, BxOpcodeGroupEVEX_0f5f_Mask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 60 k0 */ { 0, BX_IA_ERROR },
/* 60 */ { 0, BX_IA_ERROR },
/* 61 k0 */ { 0, BX_IA_ERROR },
/* 61 */ { 0, BX_IA_ERROR },
/* 62 k0 */ { 0, BX_IA_ERROR },
/* 62 */ { 0, BX_IA_ERROR },
/* 63 k0 */ { 0, BX_IA_ERROR },
/* 63 */ { 0, BX_IA_ERROR },
/* 64 k0 */ { 0, BX_IA_ERROR },
/* 64 */ { 0, BX_IA_ERROR },
/* 65 k0 */ { 0, BX_IA_ERROR },
/* 65 */ { 0, BX_IA_ERROR },
/* 66 k0 */ { 0, BX_IA_ERROR },
/* 66 */ { 0, BX_IA_ERROR },
/* 67 k0 */ { 0, BX_IA_ERROR },
/* 67 */ { 0, BX_IA_ERROR },
/* 68 k0 */ { 0, BX_IA_ERROR },
/* 68 */ { 0, BX_IA_ERROR },
/* 69 k0 */ { 0, BX_IA_ERROR },
/* 69 */ { 0, BX_IA_ERROR },
/* 6A k0 */ { 0, BX_IA_ERROR },
/* 6A */ { 0, BX_IA_ERROR },
/* 6B k0 */ { 0, BX_IA_ERROR },
/* 6B */ { 0, BX_IA_ERROR },
/* 6C k0 */ { 0, BX_IA_ERROR },
/* 6C */ { 0, BX_IA_ERROR },
/* 6D k0 */ { 0, BX_IA_ERROR },
/* 6D */ { 0, BX_IA_ERROR },
/* 6E k0 */ { 0, BX_IA_ERROR },
/* 6E */ { 0, BX_IA_ERROR },
Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions Fix vector length values for AVX-512 (512-bit vector should have length 4) support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions move AVX512 load/store and register move operations into dedicated file avx512_move.cc
2013-11-30 00:22:31 +04:00
/* 6F k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f6f },
/* 6F */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f6f_Mask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 70 k0 */ { 0, BX_IA_ERROR },
/* 70 */ { 0, BX_IA_ERROR },
/* 71 k0 */ { 0, BX_IA_ERROR },
/* 71 */ { 0, BX_IA_ERROR },
/* 72 k0 */ { 0, BX_IA_ERROR },
/* 72 */ { 0, BX_IA_ERROR },
/* 73 k0 */ { 0, BX_IA_ERROR },
/* 73 */ { 0, BX_IA_ERROR },
/* 74 k0 */ { 0, BX_IA_ERROR },
/* 74 */ { 0, BX_IA_ERROR },
/* 75 k0 */ { 0, BX_IA_ERROR },
/* 75 */ { 0, BX_IA_ERROR },
/* 76 k0 */ { 0, BX_IA_ERROR },
/* 76 */ { 0, BX_IA_ERROR },
/* 77 k0 */ { 0, BX_IA_ERROR },
/* 77 */ { 0, BX_IA_ERROR },
/* 78 k0 */ { 0, BX_IA_ERROR },
/* 78 */ { 0, BX_IA_ERROR },
/* 79 k0 */ { 0, BX_IA_ERROR },
/* 79 */ { 0, BX_IA_ERROR },
/* 7A k0 */ { 0, BX_IA_ERROR },
/* 7A */ { 0, BX_IA_ERROR },
/* 7B k0 */ { 0, BX_IA_ERROR },
/* 7B */ { 0, BX_IA_ERROR },
/* 7C k0 */ { 0, BX_IA_ERROR },
/* 7C */ { 0, BX_IA_ERROR },
/* 7D k0 */ { 0, BX_IA_ERROR },
/* 7D */ { 0, BX_IA_ERROR },
/* 7E k0 */ { 0, BX_IA_ERROR },
/* 7E */ { 0, BX_IA_ERROR },
Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions Fix vector length values for AVX-512 (512-bit vector should have length 4) support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions move AVX512 load/store and register move operations into dedicated file avx512_move.cc
2013-11-30 00:22:31 +04:00
/* 7F k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f7f },
/* 7F */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f7f_Mask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 80 k0 */ { 0, BX_IA_ERROR },
/* 80 */ { 0, BX_IA_ERROR },
/* 81 k0 */ { 0, BX_IA_ERROR },
/* 81 */ { 0, BX_IA_ERROR },
/* 82 k0 */ { 0, BX_IA_ERROR },
/* 82 */ { 0, BX_IA_ERROR },
/* 83 k0 */ { 0, BX_IA_ERROR },
/* 83 */ { 0, BX_IA_ERROR },
/* 84 k0 */ { 0, BX_IA_ERROR },
/* 84 */ { 0, BX_IA_ERROR },
/* 85 k0 */ { 0, BX_IA_ERROR },
/* 85 */ { 0, BX_IA_ERROR },
/* 86 k0 */ { 0, BX_IA_ERROR },
/* 86 */ { 0, BX_IA_ERROR },
/* 87 k0 */ { 0, BX_IA_ERROR },
/* 87 */ { 0, BX_IA_ERROR },
/* 88 k0 */ { 0, BX_IA_ERROR },
/* 88 */ { 0, BX_IA_ERROR },
/* 89 k0 */ { 0, BX_IA_ERROR },
/* 89 */ { 0, BX_IA_ERROR },
/* 8A k0 */ { 0, BX_IA_ERROR },
/* 8A */ { 0, BX_IA_ERROR },
/* 8B k0 */ { 0, BX_IA_ERROR },
/* 8B */ { 0, BX_IA_ERROR },
/* 8C k0 */ { 0, BX_IA_ERROR },
/* 8C */ { 0, BX_IA_ERROR },
/* 8D k0 */ { 0, BX_IA_ERROR },
/* 8D */ { 0, BX_IA_ERROR },
/* 8E k0 */ { 0, BX_IA_ERROR },
/* 8E */ { 0, BX_IA_ERROR },
/* 8F k0 */ { 0, BX_IA_ERROR },
/* 8F */ { 0, BX_IA_ERROR },
/* 90 k0 */ { 0, BX_IA_ERROR },
/* 90 */ { 0, BX_IA_ERROR },
/* 91 k0 */ { 0, BX_IA_ERROR },
/* 91 */ { 0, BX_IA_ERROR },
/* 92 k0 */ { 0, BX_IA_ERROR },
/* 92 */ { 0, BX_IA_ERROR },
/* 93 k0 */ { 0, BX_IA_ERROR },
/* 93 */ { 0, BX_IA_ERROR },
/* 94 k0 */ { 0, BX_IA_ERROR },
/* 94 */ { 0, BX_IA_ERROR },
/* 95 k0 */ { 0, BX_IA_ERROR },
/* 95 */ { 0, BX_IA_ERROR },
/* 96 k0 */ { 0, BX_IA_ERROR },
/* 96 */ { 0, BX_IA_ERROR },
/* 97 k0 */ { 0, BX_IA_ERROR },
/* 97 */ { 0, BX_IA_ERROR },
/* 98 k0 */ { 0, BX_IA_ERROR },
/* 98 */ { 0, BX_IA_ERROR },
/* 99 k0 */ { 0, BX_IA_ERROR },
/* 99 */ { 0, BX_IA_ERROR },
/* 9A k0 */ { 0, BX_IA_ERROR },
/* 9A */ { 0, BX_IA_ERROR },
/* 9B k0 */ { 0, BX_IA_ERROR },
/* 9B */ { 0, BX_IA_ERROR },
/* 9C k0 */ { 0, BX_IA_ERROR },
/* 9C */ { 0, BX_IA_ERROR },
/* 9D k0 */ { 0, BX_IA_ERROR },
/* 9D */ { 0, BX_IA_ERROR },
/* 9E k0 */ { 0, BX_IA_ERROR },
/* 9E */ { 0, BX_IA_ERROR },
/* 9F k0 */ { 0, BX_IA_ERROR },
/* 9F */ { 0, BX_IA_ERROR },
/* A0 k0 */ { 0, BX_IA_ERROR },
/* A0 */ { 0, BX_IA_ERROR },
/* A1 k0 */ { 0, BX_IA_ERROR },
/* A1 */ { 0, BX_IA_ERROR },
/* A2 k0 */ { 0, BX_IA_ERROR },
/* A2 */ { 0, BX_IA_ERROR },
/* A3 k0 */ { 0, BX_IA_ERROR },
/* A3 */ { 0, BX_IA_ERROR },
/* A4 k0 */ { 0, BX_IA_ERROR },
/* A4 */ { 0, BX_IA_ERROR },
/* A5 k0 */ { 0, BX_IA_ERROR },
/* A5 */ { 0, BX_IA_ERROR },
/* A6 k0 */ { 0, BX_IA_ERROR },
/* A6 */ { 0, BX_IA_ERROR },
/* A7 k0 */ { 0, BX_IA_ERROR },
/* A7 */ { 0, BX_IA_ERROR },
/* A8 k0 */ { 0, BX_IA_ERROR },
/* A8 */ { 0, BX_IA_ERROR },
/* A9 k0 */ { 0, BX_IA_ERROR },
/* A9 */ { 0, BX_IA_ERROR },
/* AA k0 */ { 0, BX_IA_ERROR },
/* AA */ { 0, BX_IA_ERROR },
/* AB k0 */ { 0, BX_IA_ERROR },
/* AB */ { 0, BX_IA_ERROR },
/* AC k0 */ { 0, BX_IA_ERROR },
/* AC */ { 0, BX_IA_ERROR },
/* AD k0 */ { 0, BX_IA_ERROR },
/* AD */ { 0, BX_IA_ERROR },
/* AE k0 */ { 0, BX_IA_ERROR },
/* AE */ { 0, BX_IA_ERROR },
/* AF k0 */ { 0, BX_IA_ERROR },
/* AF */ { 0, BX_IA_ERROR },
/* B0 k0 */ { 0, BX_IA_ERROR },
/* B0 */ { 0, BX_IA_ERROR },
/* B1 k0 */ { 0, BX_IA_ERROR },
/* B1 */ { 0, BX_IA_ERROR },
/* B2 k0 */ { 0, BX_IA_ERROR },
/* B2 */ { 0, BX_IA_ERROR },
/* B3 k0 */ { 0, BX_IA_ERROR },
/* B3 */ { 0, BX_IA_ERROR },
/* B4 k0 */ { 0, BX_IA_ERROR },
/* B4 */ { 0, BX_IA_ERROR },
/* B5 k0 */ { 0, BX_IA_ERROR },
/* B5 */ { 0, BX_IA_ERROR },
/* B6 k0 */ { 0, BX_IA_ERROR },
/* B6 */ { 0, BX_IA_ERROR },
/* B7 k0 */ { 0, BX_IA_ERROR },
/* B7 */ { 0, BX_IA_ERROR },
/* B8 k0 */ { 0, BX_IA_ERROR },
/* B8 */ { 0, BX_IA_ERROR },
/* B9 k0 */ { 0, BX_IA_ERROR },
/* B9 */ { 0, BX_IA_ERROR },
/* BA k0 */ { 0, BX_IA_ERROR },
/* BA */ { 0, BX_IA_ERROR },
/* BB k0 */ { 0, BX_IA_ERROR },
/* BB */ { 0, BX_IA_ERROR },
/* BC k0 */ { 0, BX_IA_ERROR },
/* BC */ { 0, BX_IA_ERROR },
/* BD k0 */ { 0, BX_IA_ERROR },
/* BD */ { 0, BX_IA_ERROR },
/* BE k0 */ { 0, BX_IA_ERROR },
/* BE */ { 0, BX_IA_ERROR },
/* BF k0 */ { 0, BX_IA_ERROR },
/* BF */ { 0, BX_IA_ERROR },
/* C0 k0 */ { 0, BX_IA_ERROR },
/* C0 */ { 0, BX_IA_ERROR },
/* C1 k0 */ { 0, BX_IA_ERROR },
/* C1 */ { 0, BX_IA_ERROR },
/* C2 k0 */ { 0, BX_IA_ERROR },
/* C2 */ { 0, BX_IA_ERROR },
/* C3 k0 */ { 0, BX_IA_ERROR },
/* C3 */ { 0, BX_IA_ERROR },
/* C4 k0 */ { 0, BX_IA_ERROR },
/* C4 */ { 0, BX_IA_ERROR },
/* C5 k0 */ { 0, BX_IA_ERROR },
/* C5 */ { 0, BX_IA_ERROR },
/* C6 k0 */ { 0, BX_IA_ERROR },
/* C6 */ { 0, BX_IA_ERROR },
/* C7 k0 */ { 0, BX_IA_ERROR },
/* C7 */ { 0, BX_IA_ERROR },
/* C8 k0 */ { 0, BX_IA_ERROR },
/* C8 */ { 0, BX_IA_ERROR },
/* C9 k0 */ { 0, BX_IA_ERROR },
/* C9 */ { 0, BX_IA_ERROR },
/* CA k0 */ { 0, BX_IA_ERROR },
/* CA */ { 0, BX_IA_ERROR },
/* CB k0 */ { 0, BX_IA_ERROR },
/* CB */ { 0, BX_IA_ERROR },
/* CC k0 */ { 0, BX_IA_ERROR },
/* CC */ { 0, BX_IA_ERROR },
/* CD k0 */ { 0, BX_IA_ERROR },
/* CD */ { 0, BX_IA_ERROR },
/* CE k0 */ { 0, BX_IA_ERROR },
/* CE */ { 0, BX_IA_ERROR },
/* CF k0 */ { 0, BX_IA_ERROR },
/* CF */ { 0, BX_IA_ERROR },
/* D0 k0 */ { 0, BX_IA_ERROR },
/* D0 */ { 0, BX_IA_ERROR },
/* D1 k0 */ { 0, BX_IA_ERROR },
/* D1 */ { 0, BX_IA_ERROR },
/* D2 k0 */ { 0, BX_IA_ERROR },
/* D2 */ { 0, BX_IA_ERROR },
/* D3 k0 */ { 0, BX_IA_ERROR },
/* D3 */ { 0, BX_IA_ERROR },
more avx512 instructions done
2013-10-09 23:45:36 +04:00
/* D4 k0 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPADDQ_VdqHdqWdq },
/* D4 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPADDQ_VdqHdqWdq_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* D5 k0 */ { 0, BX_IA_ERROR },
/* D5 */ { 0, BX_IA_ERROR },
/* D6 k0 */ { 0, BX_IA_ERROR },
/* D6 */ { 0, BX_IA_ERROR },
/* D7 k0 */ { 0, BX_IA_ERROR },
/* D7 */ { 0, BX_IA_ERROR },
/* D8 k0 */ { 0, BX_IA_ERROR },
/* D8 */ { 0, BX_IA_ERROR },
/* D9 k0 */ { 0, BX_IA_ERROR },
/* D9 */ { 0, BX_IA_ERROR },
/* DA k0 */ { 0, BX_IA_ERROR },
/* DA */ { 0, BX_IA_ERROR },
more avx512 instructions done
2013-10-09 23:45:36 +04:00
/* DB k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPANDD_VdqHdqWdq },
/* DB */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPANDD_VdqHdqWdq_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* DC k0 */ { 0, BX_IA_ERROR },
/* DC */ { 0, BX_IA_ERROR },
/* DD k0 */ { 0, BX_IA_ERROR },
/* DD */ { 0, BX_IA_ERROR },
/* DE k0 */ { 0, BX_IA_ERROR },
/* DE */ { 0, BX_IA_ERROR },
more avx512 instructions done
2013-10-09 23:45:36 +04:00
/* DF k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPANDND_VdqHdqWdq },
/* DF */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPANDND_VdqHdqWdq_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* E0 k0 */ { 0, BX_IA_ERROR },
/* E0 */ { 0, BX_IA_ERROR },
/* E1 k0 */ { 0, BX_IA_ERROR },
/* E1 */ { 0, BX_IA_ERROR },
/* E2 k0 */ { 0, BX_IA_ERROR },
/* E2 */ { 0, BX_IA_ERROR },
/* E3 k0 */ { 0, BX_IA_ERROR },
/* E3 */ { 0, BX_IA_ERROR },
/* E4 k0 */ { 0, BX_IA_ERROR },
/* E4 */ { 0, BX_IA_ERROR },
/* E5 k0 */ { 0, BX_IA_ERROR },
/* E5 */ { 0, BX_IA_ERROR },
/* E6 k0 */ { 0, BX_IA_ERROR },
/* E6 */ { 0, BX_IA_ERROR },
/* E7 k0 */ { 0, BX_IA_ERROR },
/* E7 */ { 0, BX_IA_ERROR },
/* E8 k0 */ { 0, BX_IA_ERROR },
/* E8 */ { 0, BX_IA_ERROR },
/* E9 k0 */ { 0, BX_IA_ERROR },
/* E9 */ { 0, BX_IA_ERROR },
/* EA k0 */ { 0, BX_IA_ERROR },
/* EA */ { 0, BX_IA_ERROR },
more avx512 instructions done
2013-10-09 23:45:36 +04:00
/* EB k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPORD_VdqHdqWdq },
/* EB */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPORD_VdqHdqWdq_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* EC k0 */ { 0, BX_IA_ERROR },
/* EC */ { 0, BX_IA_ERROR },
/* ED k0 */ { 0, BX_IA_ERROR },
/* ED */ { 0, BX_IA_ERROR },
/* EE k0 */ { 0, BX_IA_ERROR },
/* EE */ { 0, BX_IA_ERROR },
more avx512 instructions done
2013-10-09 23:45:36 +04:00
/* EF k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPXORD_VdqHdqWdq },
/* EF */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPXORD_VdqHdqWdq_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* F0 k0 */ { 0, BX_IA_ERROR },
/* F0 */ { 0, BX_IA_ERROR },
/* F1 k0 */ { 0, BX_IA_ERROR },
/* F1 */ { 0, BX_IA_ERROR },
/* F2 k0 */ { 0, BX_IA_ERROR },
/* F2 */ { 0, BX_IA_ERROR },
/* F3 k0 */ { 0, BX_IA_ERROR },
/* F3 */ { 0, BX_IA_ERROR },
/* F4 k0 */ { 0, BX_IA_ERROR },
/* F4 */ { 0, BX_IA_ERROR },
/* F5 k0 */ { 0, BX_IA_ERROR },
/* F5 */ { 0, BX_IA_ERROR },
/* F6 k0 */ { 0, BX_IA_ERROR },
/* F6 */ { 0, BX_IA_ERROR },
/* F7 k0 */ { 0, BX_IA_ERROR },
/* F7 */ { 0, BX_IA_ERROR },
/* F8 k0 */ { 0, BX_IA_ERROR },
/* F8 */ { 0, BX_IA_ERROR },
/* F9 k0 */ { 0, BX_IA_ERROR },
/* F9 */ { 0, BX_IA_ERROR },
more avx512 instructions done
2013-10-09 23:45:36 +04:00
/* FA k0 */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VPSUBD_VdqHdqWdq },
/* FA */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VPSUBD_VdqHdqWdq_Kmask },
/* FB k0 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPSUBQ_VdqHdqWdq },
/* FB */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPSUBQ_VdqHdqWdq_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* FC k0 */ { 0, BX_IA_ERROR },
/* FC */ { 0, BX_IA_ERROR },
/* FD k0 */ { 0, BX_IA_ERROR },
/* FD */ { 0, BX_IA_ERROR },
more avx512 instructions done
2013-10-09 23:45:36 +04:00
/* FE k0 */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VPADDD_VdqHdqWdq },
/* FE */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VPADDD_VdqHdqWdq_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* FF k0 */ { 0, BX_IA_ERROR },
/* FF */ { 0, BX_IA_ERROR },
// 256 entries for EVEX-encoded 0x0F 0x38 opcodes
/* 00 k0 */ { 0, BX_IA_ERROR },
/* 00 */ { 0, BX_IA_ERROR },
/* 01 k0 */ { 0, BX_IA_ERROR },
/* 01 */ { 0, BX_IA_ERROR },
/* 02 k0 */ { 0, BX_IA_ERROR },
/* 02 */ { 0, BX_IA_ERROR },
/* 03 k0 */ { 0, BX_IA_ERROR },
/* 03 */ { 0, BX_IA_ERROR },
/* 04 k0 */ { 0, BX_IA_ERROR },
/* 04 */ { 0, BX_IA_ERROR },
/* 05 k0 */ { 0, BX_IA_ERROR },
/* 05 */ { 0, BX_IA_ERROR },
/* 06 k0 */ { 0, BX_IA_ERROR },
/* 06 */ { 0, BX_IA_ERROR },
/* 07 k0 */ { 0, BX_IA_ERROR },
/* 07 */ { 0, BX_IA_ERROR },
/* 08 k0 */ { 0, BX_IA_ERROR },
/* 08 */ { 0, BX_IA_ERROR },
/* 09 k0 */ { 0, BX_IA_ERROR },
/* 09 */ { 0, BX_IA_ERROR },
/* 0A k0 */ { 0, BX_IA_ERROR },
/* 0A */ { 0, BX_IA_ERROR },
/* 0B k0 */ { 0, BX_IA_ERROR },
/* 0B */ { 0, BX_IA_ERROR },
/* 0C k0 */ { 0, BX_IA_ERROR },
/* 0C */ { 0, BX_IA_ERROR },
/* 0D k0 */ { 0, BX_IA_ERROR },
/* 0D */ { 0, BX_IA_ERROR },
/* 0E k0 */ { 0, BX_IA_ERROR },
/* 0E */ { 0, BX_IA_ERROR },
/* 0F k0 */ { 0, BX_IA_ERROR },
/* 0F */ { 0, BX_IA_ERROR },
/* 10 k0 */ { 0, BX_IA_ERROR },
/* 10 */ { 0, BX_IA_ERROR },
/* 11 k0 */ { 0, BX_IA_ERROR },
/* 11 */ { 0, BX_IA_ERROR },
/* 12 k0 */ { 0, BX_IA_ERROR },
/* 12 */ { 0, BX_IA_ERROR },
/* 13 k0 */ { 0, BX_IA_ERROR },
/* 13 */ { 0, BX_IA_ERROR },
/* 14 k0 */ { 0, BX_IA_ERROR },
/* 14 */ { 0, BX_IA_ERROR },
/* 15 k0 */ { 0, BX_IA_ERROR },
/* 15 */ { 0, BX_IA_ERROR },
/* 16 k0 */ { 0, BX_IA_ERROR },
/* 16 */ { 0, BX_IA_ERROR },
/* 17 k0 */ { 0, BX_IA_ERROR },
/* 17 */ { 0, BX_IA_ERROR },
/* 18 k0 */ { 0, BX_IA_ERROR },
/* 18 */ { 0, BX_IA_ERROR },
/* 19 k0 */ { 0, BX_IA_ERROR },
/* 19 */ { 0, BX_IA_ERROR },
/* 1A k0 */ { 0, BX_IA_ERROR },
/* 1A */ { 0, BX_IA_ERROR },
/* 1B k0 */ { 0, BX_IA_ERROR },
/* 1B */ { 0, BX_IA_ERROR },
/* 1C k0 */ { 0, BX_IA_ERROR },
/* 1C */ { 0, BX_IA_ERROR },
/* 1D k0 */ { 0, BX_IA_ERROR },
/* 1D */ { 0, BX_IA_ERROR },
/* 1E k0 */ { 0, BX_IA_ERROR },
/* 1E */ { 0, BX_IA_ERROR },
/* 1F k0 */ { 0, BX_IA_ERROR },
/* 1F */ { 0, BX_IA_ERROR },
/* 20 k0 */ { 0, BX_IA_ERROR },
/* 20 */ { 0, BX_IA_ERROR },
/* 21 k0 */ { 0, BX_IA_ERROR },
/* 21 */ { 0, BX_IA_ERROR },
/* 22 k0 */ { 0, BX_IA_ERROR },
/* 22 */ { 0, BX_IA_ERROR },
/* 23 k0 */ { 0, BX_IA_ERROR },
/* 23 */ { 0, BX_IA_ERROR },
/* 24 k0 */ { 0, BX_IA_ERROR },
/* 24 */ { 0, BX_IA_ERROR },
/* 25 k0 */ { 0, BX_IA_ERROR },
/* 25 */ { 0, BX_IA_ERROR },
/* 26 k0 */ { 0, BX_IA_ERROR },
/* 26 */ { 0, BX_IA_ERROR },
/* 27 k0 */ { 0, BX_IA_ERROR },
/* 27 */ { 0, BX_IA_ERROR },
/* 28 k0 */ { 0, BX_IA_ERROR },
/* 28 */ { 0, BX_IA_ERROR },
/* 29 k0 */ { 0, BX_IA_ERROR },
/* 29 */ { 0, BX_IA_ERROR },
/* 2A k0 */ { 0, BX_IA_ERROR },
/* 2A */ { 0, BX_IA_ERROR },
/* 2B k0 */ { 0, BX_IA_ERROR },
/* 2B */ { 0, BX_IA_ERROR },
/* 2C k0 */ { 0, BX_IA_ERROR },
/* 2C */ { 0, BX_IA_ERROR },
/* 2D k0 */ { 0, BX_IA_ERROR },
/* 2D */ { 0, BX_IA_ERROR },
/* 2E k0 */ { 0, BX_IA_ERROR },
/* 2E */ { 0, BX_IA_ERROR },
/* 2F k0 */ { 0, BX_IA_ERROR },
/* 2F */ { 0, BX_IA_ERROR },
/* 30 k0 */ { 0, BX_IA_ERROR },
/* 30 */ { 0, BX_IA_ERROR },
/* 31 k0 */ { 0, BX_IA_ERROR },
/* 31 */ { 0, BX_IA_ERROR },
/* 32 k0 */ { 0, BX_IA_ERROR },
/* 32 */ { 0, BX_IA_ERROR },
/* 33 k0 */ { 0, BX_IA_ERROR },
/* 33 */ { 0, BX_IA_ERROR },
/* 34 k0 */ { 0, BX_IA_ERROR },
/* 34 */ { 0, BX_IA_ERROR },
/* 35 k0 */ { 0, BX_IA_ERROR },
/* 35 */ { 0, BX_IA_ERROR },
/* 36 k0 */ { 0, BX_IA_ERROR },
/* 36 */ { 0, BX_IA_ERROR },
/* 37 k0 */ { 0, BX_IA_ERROR },
/* 37 */ { 0, BX_IA_ERROR },
/* 38 k0 */ { 0, BX_IA_ERROR },
/* 38 */ { 0, BX_IA_ERROR },
/* 39 k0 */ { 0, BX_IA_ERROR },
/* 39 */ { 0, BX_IA_ERROR },
/* 3A k0 */ { 0, BX_IA_ERROR },
/* 3A */ { 0, BX_IA_ERROR },
/* 3B k0 */ { 0, BX_IA_ERROR },
/* 3B */ { 0, BX_IA_ERROR },
/* 3C k0 */ { 0, BX_IA_ERROR },
/* 3C */ { 0, BX_IA_ERROR },
/* 3D k0 */ { 0, BX_IA_ERROR },
/* 3D */ { 0, BX_IA_ERROR },
/* 3E k0 */ { 0, BX_IA_ERROR },
/* 3E */ { 0, BX_IA_ERROR },
/* 3F k0 */ { 0, BX_IA_ERROR },
/* 3F */ { 0, BX_IA_ERROR },
more coding for avx512
2013-11-26 23:22:31 +04:00
/* 40 k0 */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VPMULLD_VdqHdqWdq },
/* 40 */ { BxVexW0 | BxPrefixSSE66, BX_IA_V512_VPMULLD_VdqHdqWdq_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* 41 k0 */ { 0, BX_IA_ERROR },
/* 41 */ { 0, BX_IA_ERROR },
/* 42 k0 */ { 0, BX_IA_ERROR },
/* 42 */ { 0, BX_IA_ERROR },
/* 43 k0 */ { 0, BX_IA_ERROR },
/* 43 */ { 0, BX_IA_ERROR },
/* 44 k0 */ { 0, BX_IA_ERROR },
/* 44 */ { 0, BX_IA_ERROR },
/* 45 k0 */ { 0, BX_IA_ERROR },
/* 45 */ { 0, BX_IA_ERROR },
/* 46 k0 */ { 0, BX_IA_ERROR },
/* 46 */ { 0, BX_IA_ERROR },
/* 47 k0 */ { 0, BX_IA_ERROR },
/* 47 */ { 0, BX_IA_ERROR },
/* 48 k0 */ { 0, BX_IA_ERROR },
/* 48 */ { 0, BX_IA_ERROR },
/* 49 k0 */ { 0, BX_IA_ERROR },
/* 49 */ { 0, BX_IA_ERROR },
/* 4A k0 */ { 0, BX_IA_ERROR },
/* 4A */ { 0, BX_IA_ERROR },
/* 4B k0 */ { 0, BX_IA_ERROR },
/* 4B */ { 0, BX_IA_ERROR },
/* 4C k0 */ { 0, BX_IA_ERROR },
/* 4C */ { 0, BX_IA_ERROR },
/* 4D k0 */ { 0, BX_IA_ERROR },
/* 4D */ { 0, BX_IA_ERROR },
/* 4E k0 */ { 0, BX_IA_ERROR },
/* 4E */ { 0, BX_IA_ERROR },
/* 4F k0 */ { 0, BX_IA_ERROR },
/* 4F */ { 0, BX_IA_ERROR },
/* 50 k0 */ { 0, BX_IA_ERROR },
/* 50 */ { 0, BX_IA_ERROR },
/* 51 k0 */ { 0, BX_IA_ERROR },
/* 51 */ { 0, BX_IA_ERROR },
/* 52 k0 */ { 0, BX_IA_ERROR },
/* 52 */ { 0, BX_IA_ERROR },
/* 53 k0 */ { 0, BX_IA_ERROR },
/* 53 */ { 0, BX_IA_ERROR },
/* 54 k0 */ { 0, BX_IA_ERROR },
/* 54 */ { 0, BX_IA_ERROR },
/* 55 k0 */ { 0, BX_IA_ERROR },
/* 55 */ { 0, BX_IA_ERROR },
/* 56 k0 */ { 0, BX_IA_ERROR },
/* 56 */ { 0, BX_IA_ERROR },
/* 57 k0 */ { 0, BX_IA_ERROR },
/* 57 */ { 0, BX_IA_ERROR },
/* 58 k0 */ { 0, BX_IA_ERROR },
/* 58 */ { 0, BX_IA_ERROR },
/* 59 k0 */ { 0, BX_IA_ERROR },
/* 59 */ { 0, BX_IA_ERROR },
/* 5A k0 */ { 0, BX_IA_ERROR },
/* 5A */ { 0, BX_IA_ERROR },
/* 5B k0 */ { 0, BX_IA_ERROR },
/* 5B */ { 0, BX_IA_ERROR },
/* 5C k0 */ { 0, BX_IA_ERROR },
/* 5C */ { 0, BX_IA_ERROR },
/* 5D k0 */ { 0, BX_IA_ERROR },
/* 5D */ { 0, BX_IA_ERROR },
/* 5E k0 */ { 0, BX_IA_ERROR },
/* 5E */ { 0, BX_IA_ERROR },
/* 5F k0 */ { 0, BX_IA_ERROR },
/* 5F */ { 0, BX_IA_ERROR },
/* 60 k0 */ { 0, BX_IA_ERROR },
/* 60 */ { 0, BX_IA_ERROR },
/* 61 k0 */ { 0, BX_IA_ERROR },
/* 61 */ { 0, BX_IA_ERROR },
/* 62 k0 */ { 0, BX_IA_ERROR },
/* 62 */ { 0, BX_IA_ERROR },
/* 63 k0 */ { 0, BX_IA_ERROR },
/* 63 */ { 0, BX_IA_ERROR },
/* 64 k0 */ { 0, BX_IA_ERROR },
/* 64 */ { 0, BX_IA_ERROR },
/* 65 k0 */ { 0, BX_IA_ERROR },
/* 65 */ { 0, BX_IA_ERROR },
/* 66 k0 */ { 0, BX_IA_ERROR },
/* 66 */ { 0, BX_IA_ERROR },
/* 67 k0 */ { 0, BX_IA_ERROR },
/* 67 */ { 0, BX_IA_ERROR },
/* 68 k0 */ { 0, BX_IA_ERROR },
/* 68 */ { 0, BX_IA_ERROR },
/* 69 k0 */ { 0, BX_IA_ERROR },
/* 69 */ { 0, BX_IA_ERROR },
/* 6A k0 */ { 0, BX_IA_ERROR },
/* 6A */ { 0, BX_IA_ERROR },
/* 6B k0 */ { 0, BX_IA_ERROR },
/* 6B */ { 0, BX_IA_ERROR },
/* 6C k0 */ { 0, BX_IA_ERROR },
/* 6C */ { 0, BX_IA_ERROR },
/* 6D k0 */ { 0, BX_IA_ERROR },
/* 6D */ { 0, BX_IA_ERROR },
/* 6E k0 */ { 0, BX_IA_ERROR },
/* 6E */ { 0, BX_IA_ERROR },
/* 6F k0 */ { 0, BX_IA_ERROR },
/* 6F */ { 0, BX_IA_ERROR },
/* 70 k0 */ { 0, BX_IA_ERROR },
/* 70 */ { 0, BX_IA_ERROR },
/* 71 k0 */ { 0, BX_IA_ERROR },
/* 71 */ { 0, BX_IA_ERROR },
/* 72 k0 */ { 0, BX_IA_ERROR },
/* 72 */ { 0, BX_IA_ERROR },
/* 73 k0 */ { 0, BX_IA_ERROR },
/* 73 */ { 0, BX_IA_ERROR },
/* 74 k0 */ { 0, BX_IA_ERROR },
/* 74 */ { 0, BX_IA_ERROR },
/* 75 k0 */ { 0, BX_IA_ERROR },
/* 75 */ { 0, BX_IA_ERROR },
/* 76 k0 */ { 0, BX_IA_ERROR },
/* 76 */ { 0, BX_IA_ERROR },
/* 77 k0 */ { 0, BX_IA_ERROR },
/* 77 */ { 0, BX_IA_ERROR },
/* 78 k0 */ { 0, BX_IA_ERROR },
/* 78 */ { 0, BX_IA_ERROR },
/* 79 k0 */ { 0, BX_IA_ERROR },
/* 79 */ { 0, BX_IA_ERROR },
/* 7A k0 */ { 0, BX_IA_ERROR },
/* 7A */ { 0, BX_IA_ERROR },
/* 7B k0 */ { 0, BX_IA_ERROR },
/* 7B */ { 0, BX_IA_ERROR },
/* 7C k0 */ { 0, BX_IA_ERROR },
/* 7C */ { 0, BX_IA_ERROR },
/* 7D k0 */ { 0, BX_IA_ERROR },
/* 7D */ { 0, BX_IA_ERROR },
/* 7E k0 */ { 0, BX_IA_ERROR },
/* 7E */ { 0, BX_IA_ERROR },
/* 7F k0 */ { 0, BX_IA_ERROR },
/* 7F */ { 0, BX_IA_ERROR },
/* 80 k0 */ { 0, BX_IA_ERROR },
/* 80 */ { 0, BX_IA_ERROR },
/* 81 k0 */ { 0, BX_IA_ERROR },
/* 81 */ { 0, BX_IA_ERROR },
/* 82 k0 */ { 0, BX_IA_ERROR },
/* 82 */ { 0, BX_IA_ERROR },
/* 83 k0 */ { 0, BX_IA_ERROR },
/* 83 */ { 0, BX_IA_ERROR },
/* 84 k0 */ { 0, BX_IA_ERROR },
/* 84 */ { 0, BX_IA_ERROR },
/* 85 k0 */ { 0, BX_IA_ERROR },
/* 85 */ { 0, BX_IA_ERROR },
/* 86 k0 */ { 0, BX_IA_ERROR },
/* 86 */ { 0, BX_IA_ERROR },
/* 87 k0 */ { 0, BX_IA_ERROR },
/* 87 */ { 0, BX_IA_ERROR },
/* 88 k0 */ { 0, BX_IA_ERROR },
/* 88 */ { 0, BX_IA_ERROR },
/* 89 k0 */ { 0, BX_IA_ERROR },
/* 89 */ { 0, BX_IA_ERROR },
/* 8A k0 */ { 0, BX_IA_ERROR },
/* 8A */ { 0, BX_IA_ERROR },
/* 8B k0 */ { 0, BX_IA_ERROR },
/* 8B */ { 0, BX_IA_ERROR },
/* 8C k0 */ { 0, BX_IA_ERROR },
/* 8C */ { 0, BX_IA_ERROR },
/* 8D k0 */ { 0, BX_IA_ERROR },
/* 8D */ { 0, BX_IA_ERROR },
/* 8E k0 */ { 0, BX_IA_ERROR },
/* 8E */ { 0, BX_IA_ERROR },
/* 8F k0 */ { 0, BX_IA_ERROR },
/* 8F */ { 0, BX_IA_ERROR },
/* 90 k0 */ { 0, BX_IA_ERROR },
/* 90 */ { 0, BX_IA_ERROR },
/* 91 k0 */ { 0, BX_IA_ERROR },
/* 91 */ { 0, BX_IA_ERROR },
/* 92 k0 */ { 0, BX_IA_ERROR },
/* 92 */ { 0, BX_IA_ERROR },
/* 93 k0 */ { 0, BX_IA_ERROR },
/* 93 */ { 0, BX_IA_ERROR },
/* 94 k0 */ { 0, BX_IA_ERROR },
/* 94 */ { 0, BX_IA_ERROR },
/* 95 k0 */ { 0, BX_IA_ERROR },
/* 95 */ { 0, BX_IA_ERROR },
implemented avx-512 fma instructions (in seperate file), fixes in avx-512 decoding tables
2013-11-26 00:42:24 +04:00
/* 96 k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADDSUB132PS_VpsHpsWps },
/* 96 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADDSUB132PS_VpsHpsWps_Kmask },
/* 97 k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUBADD132PS_VpsHpsWps },
/* 97 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUBADD132PS_VpsHpsWps_Kmask },
/* 98 k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADD132PS_VpsHpsWps },
/* 98 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADD132PS_VpsHpsWps_Kmask },
/* 99 k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADD132SS_VpsHssWss },
/* 99 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADD132SS_VpsHssWss_Kmask },
/* 9A k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUB132PS_VpsHpsWps },
/* 9A */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUB132PS_VpsHpsWps_Kmask },
/* 9B k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUB132SS_VpsHssWss },
/* 9B */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUB132SS_VpsHssWss_Kmask },
/* 9C k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMADD132PS_VpsHpsWps },
/* 9C */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMADD132PS_VpsHpsWps_Kmask },
/* 9D k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMADD132SS_VpsHssWss },
/* 9D */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMADD132SS_VpsHssWss_Kmask },
/* 9E k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMSUB132PS_VpsHpsWps },
/* 9E */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMSUB132PS_VpsHpsWps_Kmask },
/* 9F k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMSUB132SS_VpsHssWss },
/* 9F */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMSUB132SS_VpsHssWss_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* A0 k0 */ { 0, BX_IA_ERROR },
/* A0 */ { 0, BX_IA_ERROR },
/* A1 k0 */ { 0, BX_IA_ERROR },
/* A1 */ { 0, BX_IA_ERROR },
/* A2 k0 */ { 0, BX_IA_ERROR },
/* A2 */ { 0, BX_IA_ERROR },
/* A3 k0 */ { 0, BX_IA_ERROR },
/* A3 */ { 0, BX_IA_ERROR },
/* A4 k0 */ { 0, BX_IA_ERROR },
/* A4 */ { 0, BX_IA_ERROR },
/* A5 k0 */ { 0, BX_IA_ERROR },
/* A5 */ { 0, BX_IA_ERROR },
implemented avx-512 fma instructions (in seperate file), fixes in avx-512 decoding tables
2013-11-26 00:42:24 +04:00
/* A6 k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADDSUB213PS_VpsHpsWps },
/* A6 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADDSUB213PS_VpsHpsWps_Kmask },
/* A7 k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUBADD213PS_VpsHpsWps },
/* A7 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUBADD213PS_VpsHpsWps_Kmask },
/* A8 k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADD213PS_VpsHpsWps },
/* A8 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADD213PS_VpsHpsWps_Kmask },
/* A9 k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADD213SS_VpsHssWss },
/* A9 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADD213SS_VpsHssWss_Kmask },
/* AA k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUB213PS_VpsHpsWps },
/* AA */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUB213PS_VpsHpsWps_Kmask },
/* AB k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUB213SS_VpsHssWss },
/* AB */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUB213SS_VpsHssWss_Kmask },
/* AC k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMADD213PS_VpsHpsWps },
/* AC */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMADD213PS_VpsHpsWps_Kmask },
/* AD k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMADD213SS_VpsHssWss },
/* AD */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMADD213SS_VpsHssWss_Kmask },
/* AE k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMSUB213PS_VpsHpsWps },
/* AE */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMSUB213PS_VpsHpsWps_Kmask },
/* AF k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMSUB213SS_VpsHssWss },
/* AF */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFNMSUB213SS_VpsHssWss_Kmask },
added evex decode tables - next step to populate them :)
2013-09-16 00:48:39 +04:00
/* B0 k0 */ { 0, BX_IA_ERROR },
/* B0 */ { 0, BX_IA_ERROR },
/* B1 k0 */ { 0, BX_IA_ERROR },
/* B1 */ { 0, BX_IA_ERROR },
/* B2 k0 */ { 0, BX_IA_ERROR },
/* B2 */ { 0, BX_IA_ERROR },
/* B3 k0 */ { 0, BX_IA_ERROR },
/* B3 */ { 0, BX_IA_ERROR },
/* B4 k0 */ { 0, BX_IA_ERROR },
/* B4 */ { 0, BX_IA_ERROR },
/* B5 k0 */ { 0, BX_IA_ERROR },
/* B5 */ { 0, BX_IA_ERROR },
/* B6 k0 */ { 0, BX_IA_ERROR },
/* B6 */ { 0, BX_IA_ERROR },
/* B7 k0 */ { 0, BX_IA_ERROR },
/* B7 */ { 0, BX_IA_ERROR },
/* B8 k0 */ { 0, BX_IA_ERROR },
/* B8 */ { 0, BX_IA_ERROR },
/* B9 k0 */ { 0, BX_IA_ERROR },
/* B9 */ { 0, BX_IA_ERROR },
/* BA k0 */ { 0, BX_IA_ERROR },
/* BA */ { 0, BX_IA_ERROR },
/* BB k0 */ { 0, BX_IA_ERROR },
/* BB */ { 0, BX_IA_ERROR },
/* BC k0 */ { 0, BX_IA_ERROR },
/* BC */ { 0, BX_IA_ERROR },
/* BD k0 */ { 0, BX_IA_ERROR },
/* BD */ { 0, BX_IA_ERROR },
/* BE k0 */ { 0, BX_IA_ERROR },
/* BE */ { 0, BX_IA_ERROR },
/* BF k0 */ { 0, BX_IA_ERROR },
/* BF */ { 0, BX_IA_ERROR },
/* C0 k0 */ { 0, BX_IA_ERROR },
/* C0 */ { 0, BX_IA_ERROR },
/* C1 k0 */ { 0, BX_IA_ERROR },
/* C1 */ { 0, BX_IA_ERROR },
/* C2 k0 */ { 0, BX_IA_ERROR },
/* C2 */ { 0, BX_IA_ERROR },
/* C3 k0 */ { 0, BX_IA_ERROR },
/* C3 */ { 0, BX_IA_ERROR },
/* C4 k0 */ { 0, BX_IA_ERROR },
/* C4 */ { 0, BX_IA_ERROR },
/* C5 k0 */ { 0, BX_IA_ERROR },
/* C5 */ { 0, BX_IA_ERROR },
/* C6 k0 */ { 0, BX_IA_ERROR },
/* C6 */ { 0, BX_IA_ERROR },
/* C7 k0 */ { 0, BX_IA_ERROR },
/* C7 */ { 0, BX_IA_ERROR },
/* C8 k0 */ { 0, BX_IA_ERROR },
/* C8 */ { 0, BX_IA_ERROR },
/* C9 k0 */ { 0, BX_IA_ERROR },
/* C9 */ { 0, BX_IA_ERROR },
/* CA k0 */ { 0, BX_IA_ERROR },
/* CA */ { 0, BX_IA_ERROR },
/* CB k0 */ { 0, BX_IA_ERROR },
/* CB */ { 0, BX_IA_ERROR },
/* CC k0 */ { 0, BX_IA_ERROR },
/* CC */ { 0, BX_IA_ERROR },
/* CD k0 */ { 0, BX_IA_ERROR },
/* CD */ { 0, BX_IA_ERROR },
/* CE k0 */ { 0, BX_IA_ERROR },
/* CE */ { 0, BX_IA_ERROR },
/* CF k0 */ { 0, BX_IA_ERROR },
/* CF */ { 0, BX_IA_ERROR },
/* D0 k0 */ { 0, BX_IA_ERROR },
/* D0 */ { 0, BX_IA_ERROR },
/* D1 k0 */ { 0, BX_IA_ERROR },
/* D1 */ { 0, BX_IA_ERROR },
/* D2 k0 */ { 0, BX_IA_ERROR },
/* D2 */ { 0, BX_IA_ERROR },
/* D3 k0 */ { 0, BX_IA_ERROR },
/* D3 */ { 0, BX_IA_ERROR },
/* D4 k0 */ { 0, BX_IA_ERROR },
/* D4 */ { 0, BX_IA_ERROR },
/* D5 k0 */ { 0, BX_IA_ERROR },
/* D5 */ { 0, BX_IA_ERROR },
/* D6 k0 */ { 0, BX_IA_ERROR },
/* D6 */ { 0, BX_IA_ERROR },
/* D7 k0 */ { 0, BX_IA_ERROR },
/* D7 */ { 0, BX_IA_ERROR },
/* D8 k0 */ { 0, BX_IA_ERROR },
/* D8 */ { 0, BX_IA_ERROR },
/* D9 k0 */ { 0, BX_IA_ERROR },
/* D9 */ { 0, BX_IA_ERROR },
/* DA k0 */ { 0, BX_IA_ERROR },
/* DA */ { 0, BX_IA_ERROR },
/* DB k0 */ { 0, BX_IA_ERROR },
/* DB */ { 0, BX_IA_ERROR },
/* DC k0 */ { 0, BX_IA_ERROR },
/* DC */ { 0, BX_IA_ERROR },
/* DD k0 */ { 0, BX_IA_ERROR },
/* DD */ { 0, BX_IA_ERROR },
/* DE k0 */ { 0, BX_IA_ERROR },
/* DE */ { 0, BX_IA_ERROR },
/* DF k0 */ { 0, BX_IA_ERROR },
/* DF */ { 0, BX_IA_ERROR },
/* E0 k0 */ { 0, BX_IA_ERROR },
/* E0 */ { 0, BX_IA_ERROR },
/* E1 k0 */ { 0, BX_IA_ERROR },
/* E1 */ { 0, BX_IA_ERROR },
/* E2 k0 */ { 0, BX_IA_ERROR },
/* E2 */ { 0, BX_IA_ERROR },
/* E3 k0 */ { 0, BX_IA_ERROR },
/* E3 */ { 0, BX_IA_ERROR },
/* E4 k0 */ { 0, BX_IA_ERROR },
/* E4 */ { 0, BX_IA_ERROR },
/* E5 k0 */ { 0, BX_IA_ERROR },
/* E5 */ { 0, BX_IA_ERROR },
/* E6 k0 */ { 0, BX_IA_ERROR },
/* E6 */ { 0, BX_IA_ERROR },
/* E7 k0 */ { 0, BX_IA_ERROR },
/* E7 */ { 0, BX_IA_ERROR },
/* E8 k0 */ { 0, BX_IA_ERROR },
/* E8 */ { 0, BX_IA_ERROR },
/* E9 k0 */ { 0, BX_IA_ERROR },
/* E9 */ { 0, BX_IA_ERROR },
/* EA k0 */ { 0, BX_IA_ERROR },
/* EA */ { 0, BX_IA_ERROR },
/* EB k0 */ { 0, BX_IA_ERROR },
/* EB */ { 0, BX_IA_ERROR },
/* EC k0 */ { 0, BX_IA_ERROR },
/* EC */ { 0, BX_IA_ERROR },
/* ED k0 */ { 0, BX_IA_ERROR },
/* ED */ { 0, BX_IA_ERROR },
/* EE k0 */ { 0, BX_IA_ERROR },
/* EE */ { 0, BX_IA_ERROR },
/* EF k0 */ { 0, BX_IA_ERROR },
/* EF */ { 0, BX_IA_ERROR },
/* F0 k0 */ { 0, BX_IA_ERROR },
/* F0 */ { 0, BX_IA_ERROR },
/* F1 k0 */ { 0, BX_IA_ERROR },
/* F1 */ { 0, BX_IA_ERROR },
/* F2 k0 */ { 0, BX_IA_ERROR },
/* F2 */ { 0, BX_IA_ERROR },
/* F3 k0 */ { 0, BX_IA_ERROR },
/* F3 */ { 0, BX_IA_ERROR },
/* F4 k0 */ { 0, BX_IA_ERROR },
/* F4 */ { 0, BX_IA_ERROR },
/* F5 k0 */ { 0, BX_IA_ERROR },
/* F5 */ { 0, BX_IA_ERROR },
/* F6 k0 */ { 0, BX_IA_ERROR },
/* F6 */ { 0, BX_IA_ERROR },
/* F7 k0 */ { 0, BX_IA_ERROR },
/* F7 */ { 0, BX_IA_ERROR },
/* F8 k0 */ { 0, BX_IA_ERROR },
/* F8 */ { 0, BX_IA_ERROR },
/* F9 k0 */ { 0, BX_IA_ERROR },
/* F9 */ { 0, BX_IA_ERROR },
/* FA k0 */ { 0, BX_IA_ERROR },
/* FA */ { 0, BX_IA_ERROR },
/* FB k0 */ { 0, BX_IA_ERROR },
/* FB */ { 0, BX_IA_ERROR },
/* FC k0 */ { 0, BX_IA_ERROR },
/* FC */ { 0, BX_IA_ERROR },
/* FD k0 */ { 0, BX_IA_ERROR },
/* FD */ { 0, BX_IA_ERROR },
/* FE k0 */ { 0, BX_IA_ERROR },
/* FE */ { 0, BX_IA_ERROR },
/* FF k0 */ { 0, BX_IA_ERROR },
/* FF */ { 0, BX_IA_ERROR },
// 256 entries for EVEX-encoded 0x0F 0x3A opcodes
/* 00 k0 */ { 0, BX_IA_ERROR },
/* 00 */ { 0, BX_IA_ERROR },
/* 01 k0 */ { 0, BX_IA_ERROR },
/* 01 */ { 0, BX_IA_ERROR },
/* 02 k0 */ { 0, BX_IA_ERROR },
/* 02 */ { 0, BX_IA_ERROR },
/* 03 k0 */ { 0, BX_IA_ERROR },
/* 03 */ { 0, BX_IA_ERROR },
/* 04 k0 */ { 0, BX_IA_ERROR },
/* 04 */ { 0, BX_IA_ERROR },
/* 05 k0 */ { 0, BX_IA_ERROR },
/* 05 */ { 0, BX_IA_ERROR },
/* 06 k0 */ { 0, BX_IA_ERROR },
/* 06 */ { 0, BX_IA_ERROR },
/* 07 k0 */ { 0, BX_IA_ERROR },
/* 07 */ { 0, BX_IA_ERROR },
/* 08 k0 */ { 0, BX_IA_ERROR },
/* 08 */ { 0, BX_IA_ERROR },
/* 09 k0 */ { 0, BX_IA_ERROR },
/* 09 */ { 0, BX_IA_ERROR },
/* 0A k0 */ { 0, BX_IA_ERROR },
/* 0A */ { 0, BX_IA_ERROR },
/* 0B k0 */ { 0, BX_IA_ERROR },
/* 0B */ { 0, BX_IA_ERROR },
/* 0C k0 */ { 0, BX_IA_ERROR },
/* 0C */ { 0, BX_IA_ERROR },
/* 0D k0 */ { 0, BX_IA_ERROR },
/* 0D */ { 0, BX_IA_ERROR },
/* 0E k0 */ { 0, BX_IA_ERROR },
/* 0E */ { 0, BX_IA_ERROR },
/* 0F k0 */ { 0, BX_IA_ERROR },
/* 0F */ { 0, BX_IA_ERROR },
/* 10 k0 */ { 0, BX_IA_ERROR },
/* 10 */ { 0, BX_IA_ERROR },
/* 11 k0 */ { 0, BX_IA_ERROR },
/* 11 */ { 0, BX_IA_ERROR },
/* 12 k0 */ { 0, BX_IA_ERROR },
/* 12 */ { 0, BX_IA_ERROR },
/* 13 k0 */ { 0, BX_IA_ERROR },
/* 13 */ { 0, BX_IA_ERROR },
/* 14 k0 */ { 0, BX_IA_ERROR },
/* 14 */ { 0, BX_IA_ERROR },
/* 15 k0 */ { 0, BX_IA_ERROR },
/* 15 */ { 0, BX_IA_ERROR },
/* 16 k0 */ { 0, BX_IA_ERROR },
/* 16 */ { 0, BX_IA_ERROR },
/* 17 k0 */ { 0, BX_IA_ERROR },
/* 17 */ { 0, BX_IA_ERROR },
/* 18 k0 */ { 0, BX_IA_ERROR },
/* 18 */ { 0, BX_IA_ERROR },
/* 19 k0 */ { 0, BX_IA_ERROR },
/* 19 */ { 0, BX_IA_ERROR },
/* 1A k0 */ { 0, BX_IA_ERROR },
/* 1A */ { 0, BX_IA_ERROR },
/* 1B k0 */ { 0, BX_IA_ERROR },
/* 1B */ { 0, BX_IA_ERROR },
/* 1C k0 */ { 0, BX_IA_ERROR },
/* 1C */ { 0, BX_IA_ERROR },
/* 1D k0 */ { 0, BX_IA_ERROR },
/* 1D */ { 0, BX_IA_ERROR },
/* 1E k0 */ { 0, BX_IA_ERROR },
/* 1E */ { 0, BX_IA_ERROR },
/* 1F k0 */ { 0, BX_IA_ERROR },
/* 1F */ { 0, BX_IA_ERROR },
/* 20 k0 */ { 0, BX_IA_ERROR },
/* 20 */ { 0, BX_IA_ERROR },
/* 21 k0 */ { 0, BX_IA_ERROR },
/* 21 */ { 0, BX_IA_ERROR },
/* 22 k0 */ { 0, BX_IA_ERROR },
/* 22 */ { 0, BX_IA_ERROR },
/* 23 k0 */ { 0, BX_IA_ERROR },
/* 23 */ { 0, BX_IA_ERROR },
/* 24 k0 */ { 0, BX_IA_ERROR },
/* 24 */ { 0, BX_IA_ERROR },
/* 25 k0 */ { 0, BX_IA_ERROR },
/* 25 */ { 0, BX_IA_ERROR },
/* 26 k0 */ { 0, BX_IA_ERROR },
/* 26 */ { 0, BX_IA_ERROR },
/* 27 k0 */ { 0, BX_IA_ERROR },
/* 27 */ { 0, BX_IA_ERROR },
/* 28 k0 */ { 0, BX_IA_ERROR },
/* 28 */ { 0, BX_IA_ERROR },
/* 29 k0 */ { 0, BX_IA_ERROR },
/* 29 */ { 0, BX_IA_ERROR },
/* 2A k0 */ { 0, BX_IA_ERROR },
/* 2A */ { 0, BX_IA_ERROR },
/* 2B k0 */ { 0, BX_IA_ERROR },
/* 2B */ { 0, BX_IA_ERROR },
/* 2C k0 */ { 0, BX_IA_ERROR },
/* 2C */ { 0, BX_IA_ERROR },
/* 2D k0 */ { 0, BX_IA_ERROR },
/* 2D */ { 0, BX_IA_ERROR },
/* 2E k0 */ { 0, BX_IA_ERROR },
/* 2E */ { 0, BX_IA_ERROR },
/* 2F k0 */ { 0, BX_IA_ERROR },
/* 2F */ { 0, BX_IA_ERROR },
/* 30 k0 */ { 0, BX_IA_ERROR },
/* 30 */ { 0, BX_IA_ERROR },
/* 31 k0 */ { 0, BX_IA_ERROR },
/* 31 */ { 0, BX_IA_ERROR },
/* 32 k0 */ { 0, BX_IA_ERROR },
/* 32 */ { 0, BX_IA_ERROR },
/* 33 k0 */ { 0, BX_IA_ERROR },
/* 33 */ { 0, BX_IA_ERROR },
/* 34 k0 */ { 0, BX_IA_ERROR },
/* 34 */ { 0, BX_IA_ERROR },
/* 35 k0 */ { 0, BX_IA_ERROR },
/* 35 */ { 0, BX_IA_ERROR },
/* 36 k0 */ { 0, BX_IA_ERROR },
/* 36 */ { 0, BX_IA_ERROR },
/* 37 k0 */ { 0, BX_IA_ERROR },
/* 37 */ { 0, BX_IA_ERROR },
/* 38 k0 */ { 0, BX_IA_ERROR },
/* 38 */ { 0, BX_IA_ERROR },
/* 39 k0 */ { 0, BX_IA_ERROR },
/* 39 */ { 0, BX_IA_ERROR },
/* 3A k0 */ { 0, BX_IA_ERROR },
/* 3A */ { 0, BX_IA_ERROR },
/* 3B k0 */ { 0, BX_IA_ERROR },
/* 3B */ { 0, BX_IA_ERROR },
/* 3C k0 */ { 0, BX_IA_ERROR },
/* 3C */ { 0, BX_IA_ERROR },
/* 3D k0 */ { 0, BX_IA_ERROR },
/* 3D */ { 0, BX_IA_ERROR },
/* 3E k0 */ { 0, BX_IA_ERROR },
/* 3E */ { 0, BX_IA_ERROR },
/* 3F k0 */ { 0, BX_IA_ERROR },
/* 3F */ { 0, BX_IA_ERROR },
/* 40 k0 */ { 0, BX_IA_ERROR },
/* 40 */ { 0, BX_IA_ERROR },
/* 41 k0 */ { 0, BX_IA_ERROR },
/* 41 */ { 0, BX_IA_ERROR },
/* 42 k0 */ { 0, BX_IA_ERROR },
/* 42 */ { 0, BX_IA_ERROR },
/* 43 k0 */ { 0, BX_IA_ERROR },
/* 43 */ { 0, BX_IA_ERROR },
/* 44 k0 */ { 0, BX_IA_ERROR },
/* 44 */ { 0, BX_IA_ERROR },
/* 45 k0 */ { 0, BX_IA_ERROR },
/* 45 */ { 0, BX_IA_ERROR },
/* 46 k0 */ { 0, BX_IA_ERROR },
/* 46 */ { 0, BX_IA_ERROR },
/* 47 k0 */ { 0, BX_IA_ERROR },
/* 47 */ { 0, BX_IA_ERROR },
/* 48 k0 */ { 0, BX_IA_ERROR },
/* 48 */ { 0, BX_IA_ERROR },
/* 49 k0 */ { 0, BX_IA_ERROR },
/* 49 */ { 0, BX_IA_ERROR },
/* 4A k0 */ { 0, BX_IA_ERROR },
/* 4A */ { 0, BX_IA_ERROR },
/* 4B k0 */ { 0, BX_IA_ERROR },
/* 4B */ { 0, BX_IA_ERROR },
/* 4C k0 */ { 0, BX_IA_ERROR },
/* 4C */ { 0, BX_IA_ERROR },
/* 4D k0 */ { 0, BX_IA_ERROR },
/* 4D */ { 0, BX_IA_ERROR },
/* 4E k0 */ { 0, BX_IA_ERROR },
/* 4E */ { 0, BX_IA_ERROR },
/* 4F k0 */ { 0, BX_IA_ERROR },
/* 4F */ { 0, BX_IA_ERROR },
/* 50 k0 */ { 0, BX_IA_ERROR },
/* 50 */ { 0, BX_IA_ERROR },
/* 51 k0 */ { 0, BX_IA_ERROR },
/* 51 */ { 0, BX_IA_ERROR },
/* 52 k0 */ { 0, BX_IA_ERROR },
/* 52 */ { 0, BX_IA_ERROR },
/* 53 k0 */ { 0, BX_IA_ERROR },
/* 53 */ { 0, BX_IA_ERROR },
/* 54 k0 */ { 0, BX_IA_ERROR },
/* 54 */ { 0, BX_IA_ERROR },
/* 55 k0 */ { 0, BX_IA_ERROR },
/* 55 */ { 0, BX_IA_ERROR },
/* 56 k0 */ { 0, BX_IA_ERROR },
/* 56 */ { 0, BX_IA_ERROR },
/* 57 k0 */ { 0, BX_IA_ERROR },
/* 57 */ { 0, BX_IA_ERROR },
/* 58 k0 */ { 0, BX_IA_ERROR },
/* 58 */ { 0, BX_IA_ERROR },
/* 59 k0 */ { 0, BX_IA_ERROR },
/* 59 */ { 0, BX_IA_ERROR },
/* 5A k0 */ { 0, BX_IA_ERROR },
/* 5A */ { 0, BX_IA_ERROR },
/* 5B k0 */ { 0, BX_IA_ERROR },
/* 5B */ { 0, BX_IA_ERROR },
/* 5C k0 */ { 0, BX_IA_ERROR },
/* 5C */ { 0, BX_IA_ERROR },
/* 5D k0 */ { 0, BX_IA_ERROR },
/* 5D */ { 0, BX_IA_ERROR },
/* 5E k0 */ { 0, BX_IA_ERROR },
/* 5E */ { 0, BX_IA_ERROR },
/* 5F k0 */ { 0, BX_IA_ERROR },
/* 5F */ { 0, BX_IA_ERROR },
/* 60 k0 */ { 0, BX_IA_ERROR },
/* 60 */ { 0, BX_IA_ERROR },
/* 61 k0 */ { 0, BX_IA_ERROR },
/* 61 */ { 0, BX_IA_ERROR },
/* 62 k0 */ { 0, BX_IA_ERROR },
/* 62 */ { 0, BX_IA_ERROR },
/* 63 k0 */ { 0, BX_IA_ERROR },
/* 63 */ { 0, BX_IA_ERROR },
/* 64 k0 */ { 0, BX_IA_ERROR },
/* 64 */ { 0, BX_IA_ERROR },
/* 65 k0 */ { 0, BX_IA_ERROR },
/* 65 */ { 0, BX_IA_ERROR },
/* 66 k0 */ { 0, BX_IA_ERROR },
/* 66 */ { 0, BX_IA_ERROR },
/* 67 k0 */ { 0, BX_IA_ERROR },
/* 67 */ { 0, BX_IA_ERROR },
/* 68 k0 */ { 0, BX_IA_ERROR },
/* 68 */ { 0, BX_IA_ERROR },
/* 69 k0 */ { 0, BX_IA_ERROR },
/* 69 */ { 0, BX_IA_ERROR },
/* 6A k0 */ { 0, BX_IA_ERROR },
/* 6A */ { 0, BX_IA_ERROR },
/* 6B k0 */ { 0, BX_IA_ERROR },
/* 6B */ { 0, BX_IA_ERROR },
/* 6C k0 */ { 0, BX_IA_ERROR },
/* 6C */ { 0, BX_IA_ERROR },
/* 6D k0 */ { 0, BX_IA_ERROR },
/* 6D */ { 0, BX_IA_ERROR },
/* 6E k0 */ { 0, BX_IA_ERROR },
/* 6E */ { 0, BX_IA_ERROR },
/* 6F k0 */ { 0, BX_IA_ERROR },
/* 6F */ { 0, BX_IA_ERROR },
/* 70 k0 */ { 0, BX_IA_ERROR },
/* 70 */ { 0, BX_IA_ERROR },
/* 71 k0 */ { 0, BX_IA_ERROR },
/* 71 */ { 0, BX_IA_ERROR },
/* 72 k0 */ { 0, BX_IA_ERROR },
/* 72 */ { 0, BX_IA_ERROR },
/* 73 k0 */ { 0, BX_IA_ERROR },
/* 73 */ { 0, BX_IA_ERROR },
/* 74 k0 */ { 0, BX_IA_ERROR },
/* 74 */ { 0, BX_IA_ERROR },
/* 75 k0 */ { 0, BX_IA_ERROR },
/* 75 */ { 0, BX_IA_ERROR },
/* 76 k0 */ { 0, BX_IA_ERROR },
/* 76 */ { 0, BX_IA_ERROR },
/* 77 k0 */ { 0, BX_IA_ERROR },
/* 77 */ { 0, BX_IA_ERROR },
/* 78 k0 */ { 0, BX_IA_ERROR },
/* 78 */ { 0, BX_IA_ERROR },
/* 79 k0 */ { 0, BX_IA_ERROR },
/* 79 */ { 0, BX_IA_ERROR },
/* 7A k0 */ { 0, BX_IA_ERROR },
/* 7A */ { 0, BX_IA_ERROR },
/* 7B k0 */ { 0, BX_IA_ERROR },
/* 7B */ { 0, BX_IA_ERROR },
/* 7C k0 */ { 0, BX_IA_ERROR },
/* 7C */ { 0, BX_IA_ERROR },
/* 7D k0 */ { 0, BX_IA_ERROR },
/* 7D */ { 0, BX_IA_ERROR },
/* 7E k0 */ { 0, BX_IA_ERROR },
/* 7E */ { 0, BX_IA_ERROR },
/* 7F k0 */ { 0, BX_IA_ERROR },
/* 7F */ { 0, BX_IA_ERROR },
/* 80 k0 */ { 0, BX_IA_ERROR },
/* 80 */ { 0, BX_IA_ERROR },
/* 81 k0 */ { 0, BX_IA_ERROR },
/* 81 */ { 0, BX_IA_ERROR },
/* 82 k0 */ { 0, BX_IA_ERROR },
/* 82 */ { 0, BX_IA_ERROR },
/* 83 k0 */ { 0, BX_IA_ERROR },
/* 83 */ { 0, BX_IA_ERROR },
/* 84 k0 */ { 0, BX_IA_ERROR },
/* 84 */ { 0, BX_IA_ERROR },
/* 85 k0 */ { 0, BX_IA_ERROR },
/* 85 */ { 0, BX_IA_ERROR },
/* 86 k0 */ { 0, BX_IA_ERROR },
/* 86 */ { 0, BX_IA_ERROR },
/* 87 k0 */ { 0, BX_IA_ERROR },
/* 87 */ { 0, BX_IA_ERROR },
/* 88 k0 */ { 0, BX_IA_ERROR },
/* 88 */ { 0, BX_IA_ERROR },
/* 89 k0 */ { 0, BX_IA_ERROR },
/* 89 */ { 0, BX_IA_ERROR },
/* 8A k0 */ { 0, BX_IA_ERROR },
/* 8A */ { 0, BX_IA_ERROR },
/* 8B k0 */ { 0, BX_IA_ERROR },
/* 8B */ { 0, BX_IA_ERROR },
/* 8C k0 */ { 0, BX_IA_ERROR },
/* 8C */ { 0, BX_IA_ERROR },
/* 8D k0 */ { 0, BX_IA_ERROR },
/* 8D */ { 0, BX_IA_ERROR },
/* 8E k0 */ { 0, BX_IA_ERROR },
/* 8E */ { 0, BX_IA_ERROR },
/* 8F k0 */ { 0, BX_IA_ERROR },
/* 8F */ { 0, BX_IA_ERROR },
/* 90 k0 */ { 0, BX_IA_ERROR },
/* 90 */ { 0, BX_IA_ERROR },
/* 91 k0 */ { 0, BX_IA_ERROR },
/* 91 */ { 0, BX_IA_ERROR },
/* 92 k0 */ { 0, BX_IA_ERROR },
/* 92 */ { 0, BX_IA_ERROR },
/* 93 k0 */ { 0, BX_IA_ERROR },
/* 93 */ { 0, BX_IA_ERROR },
/* 94 k0 */ { 0, BX_IA_ERROR },
/* 94 */ { 0, BX_IA_ERROR },
/* 95 k0 */ { 0, BX_IA_ERROR },
/* 95 */ { 0, BX_IA_ERROR },
/* 96 k0 */ { 0, BX_IA_ERROR },
/* 96 */ { 0, BX_IA_ERROR },
/* 97 k0 */ { 0, BX_IA_ERROR },
/* 97 */ { 0, BX_IA_ERROR },
/* 98 k0 */ { 0, BX_IA_ERROR },
/* 98 */ { 0, BX_IA_ERROR },
/* 99 k0 */ { 0, BX_IA_ERROR },
/* 99 */ { 0, BX_IA_ERROR },
/* 9A k0 */ { 0, BX_IA_ERROR },
/* 9A */ { 0, BX_IA_ERROR },
/* 9B k0 */ { 0, BX_IA_ERROR },
/* 9B */ { 0, BX_IA_ERROR },
/* 9C k0 */ { 0, BX_IA_ERROR },
/* 9C */ { 0, BX_IA_ERROR },
/* 9D k0 */ { 0, BX_IA_ERROR },
/* 9D */ { 0, BX_IA_ERROR },
/* 9E k0 */ { 0, BX_IA_ERROR },
/* 9E */ { 0, BX_IA_ERROR },
/* 9F k0 */ { 0, BX_IA_ERROR },
/* 9F */ { 0, BX_IA_ERROR },
/* A0 k0 */ { 0, BX_IA_ERROR },
/* A0 */ { 0, BX_IA_ERROR },
/* A1 k0 */ { 0, BX_IA_ERROR },
/* A1 */ { 0, BX_IA_ERROR },
/* A2 k0 */ { 0, BX_IA_ERROR },
/* A2 */ { 0, BX_IA_ERROR },
/* A3 k0 */ { 0, BX_IA_ERROR },
/* A3 */ { 0, BX_IA_ERROR },
/* A4 k0 */ { 0, BX_IA_ERROR },
/* A4 */ { 0, BX_IA_ERROR },
/* A5 k0 */ { 0, BX_IA_ERROR },
/* A5 */ { 0, BX_IA_ERROR },
/* A6 k0 */ { 0, BX_IA_ERROR },
/* A6 */ { 0, BX_IA_ERROR },
/* A7 k0 */ { 0, BX_IA_ERROR },
/* A7 */ { 0, BX_IA_ERROR },
/* A8 k0 */ { 0, BX_IA_ERROR },
/* A8 */ { 0, BX_IA_ERROR },
/* A9 k0 */ { 0, BX_IA_ERROR },
/* A9 */ { 0, BX_IA_ERROR },
/* AA k0 */ { 0, BX_IA_ERROR },
/* AA */ { 0, BX_IA_ERROR },
/* AB k0 */ { 0, BX_IA_ERROR },
/* AB */ { 0, BX_IA_ERROR },
/* AC k0 */ { 0, BX_IA_ERROR },
/* AC */ { 0, BX_IA_ERROR },
/* AD k0 */ { 0, BX_IA_ERROR },
/* AD */ { 0, BX_IA_ERROR },
/* AE k0 */ { 0, BX_IA_ERROR },
/* AE */ { 0, BX_IA_ERROR },
/* AF k0 */ { 0, BX_IA_ERROR },
/* AF */ { 0, BX_IA_ERROR },
/* B0 k0 */ { 0, BX_IA_ERROR },
/* B0 */ { 0, BX_IA_ERROR },
/* B1 k0 */ { 0, BX_IA_ERROR },
/* B1 */ { 0, BX_IA_ERROR },
/* B2 k0 */ { 0, BX_IA_ERROR },
/* B2 */ { 0, BX_IA_ERROR },
/* B3 k0 */ { 0, BX_IA_ERROR },
/* B3 */ { 0, BX_IA_ERROR },
/* B4 k0 */ { 0, BX_IA_ERROR },
/* B4 */ { 0, BX_IA_ERROR },
/* B5 k0 */ { 0, BX_IA_ERROR },
/* B5 */ { 0, BX_IA_ERROR },
/* B6 k0 */ { 0, BX_IA_ERROR },
/* B6 */ { 0, BX_IA_ERROR },
/* B7 k0 */ { 0, BX_IA_ERROR },
/* B7 */ { 0, BX_IA_ERROR },
/* B8 k0 */ { 0, BX_IA_ERROR },
/* B8 */ { 0, BX_IA_ERROR },
/* B9 k0 */ { 0, BX_IA_ERROR },
/* B9 */ { 0, BX_IA_ERROR },
/* BA k0 */ { 0, BX_IA_ERROR },
/* BA */ { 0, BX_IA_ERROR },
/* BB k0 */ { 0, BX_IA_ERROR },
/* BB */ { 0, BX_IA_ERROR },
/* BC k0 */ { 0, BX_IA_ERROR },
/* BC */ { 0, BX_IA_ERROR },
/* BD k0 */ { 0, BX_IA_ERROR },
/* BD */ { 0, BX_IA_ERROR },
/* BE k0 */ { 0, BX_IA_ERROR },
/* BE */ { 0, BX_IA_ERROR },
/* BF k0 */ { 0, BX_IA_ERROR },
/* BF */ { 0, BX_IA_ERROR },
/* C0 k0 */ { 0, BX_IA_ERROR },
/* C0 */ { 0, BX_IA_ERROR },
/* C1 k0 */ { 0, BX_IA_ERROR },
/* C1 */ { 0, BX_IA_ERROR },
/* C2 k0 */ { 0, BX_IA_ERROR },
/* C2 */ { 0, BX_IA_ERROR },
/* C3 k0 */ { 0, BX_IA_ERROR },
/* C3 */ { 0, BX_IA_ERROR },
/* C4 k0 */ { 0, BX_IA_ERROR },
/* C4 */ { 0, BX_IA_ERROR },
/* C5 k0 */ { 0, BX_IA_ERROR },
/* C5 */ { 0, BX_IA_ERROR },
/* C6 k0 */ { 0, BX_IA_ERROR },
/* C6 */ { 0, BX_IA_ERROR },
/* C7 k0 */ { 0, BX_IA_ERROR },
/* C7 */ { 0, BX_IA_ERROR },
/* C8 k0 */ { 0, BX_IA_ERROR },
/* C8 */ { 0, BX_IA_ERROR },
/* C9 k0 */ { 0, BX_IA_ERROR },
/* C9 */ { 0, BX_IA_ERROR },
/* CA k0 */ { 0, BX_IA_ERROR },
/* CA */ { 0, BX_IA_ERROR },
/* CB k0 */ { 0, BX_IA_ERROR },
/* CB */ { 0, BX_IA_ERROR },
/* CC k0 */ { 0, BX_IA_ERROR },
/* CC */ { 0, BX_IA_ERROR },
/* CD k0 */ { 0, BX_IA_ERROR },
/* CD */ { 0, BX_IA_ERROR },
/* CE k0 */ { 0, BX_IA_ERROR },
/* CE */ { 0, BX_IA_ERROR },
/* CF k0 */ { 0, BX_IA_ERROR },
/* CF */ { 0, BX_IA_ERROR },
/* D0 k0 */ { 0, BX_IA_ERROR },
/* D0 */ { 0, BX_IA_ERROR },
/* D1 k0 */ { 0, BX_IA_ERROR },
/* D1 */ { 0, BX_IA_ERROR },
/* D2 k0 */ { 0, BX_IA_ERROR },
/* D2 */ { 0, BX_IA_ERROR },
/* D3 k0 */ { 0, BX_IA_ERROR },
/* D3 */ { 0, BX_IA_ERROR },
/* D4 k0 */ { 0, BX_IA_ERROR },
/* D4 */ { 0, BX_IA_ERROR },
/* D5 k0 */ { 0, BX_IA_ERROR },
/* D5 */ { 0, BX_IA_ERROR },
/* D6 k0 */ { 0, BX_IA_ERROR },
/* D6 */ { 0, BX_IA_ERROR },
/* D7 k0 */ { 0, BX_IA_ERROR },
/* D7 */ { 0, BX_IA_ERROR },
/* D8 k0 */ { 0, BX_IA_ERROR },
/* D8 */ { 0, BX_IA_ERROR },
/* D9 k0 */ { 0, BX_IA_ERROR },
/* D9 */ { 0, BX_IA_ERROR },
/* DA k0 */ { 0, BX_IA_ERROR },
/* DA */ { 0, BX_IA_ERROR },
/* DB k0 */ { 0, BX_IA_ERROR },
/* DB */ { 0, BX_IA_ERROR },
/* DC k0 */ { 0, BX_IA_ERROR },
/* DC */ { 0, BX_IA_ERROR },
/* DD k0 */ { 0, BX_IA_ERROR },
/* DD */ { 0, BX_IA_ERROR },
/* DE k0 */ { 0, BX_IA_ERROR },
/* DE */ { 0, BX_IA_ERROR },
/* DF k0 */ { 0, BX_IA_ERROR },
/* DF */ { 0, BX_IA_ERROR },
/* E0 k0 */ { 0, BX_IA_ERROR },
/* E0 */ { 0, BX_IA_ERROR },
/* E1 k0 */ { 0, BX_IA_ERROR },
/* E1 */ { 0, BX_IA_ERROR },
/* E2 k0 */ { 0, BX_IA_ERROR },
/* E2 */ { 0, BX_IA_ERROR },
/* E3 k0 */ { 0, BX_IA_ERROR },
/* E3 */ { 0, BX_IA_ERROR },
/* E4 k0 */ { 0, BX_IA_ERROR },
/* E4 */ { 0, BX_IA_ERROR },
/* E5 k0 */ { 0, BX_IA_ERROR },
/* E5 */ { 0, BX_IA_ERROR },
/* E6 k0 */ { 0, BX_IA_ERROR },
/* E6 */ { 0, BX_IA_ERROR },
/* E7 k0 */ { 0, BX_IA_ERROR },
/* E7 */ { 0, BX_IA_ERROR },
/* E8 k0 */ { 0, BX_IA_ERROR },
/* E8 */ { 0, BX_IA_ERROR },
/* E9 k0 */ { 0, BX_IA_ERROR },
/* E9 */ { 0, BX_IA_ERROR },
/* EA k0 */ { 0, BX_IA_ERROR },
/* EA */ { 0, BX_IA_ERROR },
/* EB k0 */ { 0, BX_IA_ERROR },
/* EB */ { 0, BX_IA_ERROR },
/* EC k0 */ { 0, BX_IA_ERROR },
/* EC */ { 0, BX_IA_ERROR },
/* ED k0 */ { 0, BX_IA_ERROR },
/* ED */ { 0, BX_IA_ERROR },
/* EE k0 */ { 0, BX_IA_ERROR },
/* EE */ { 0, BX_IA_ERROR },
/* EF k0 */ { 0, BX_IA_ERROR },
/* EF */ { 0, BX_IA_ERROR },
/* F0 k0 */ { 0, BX_IA_ERROR },
/* F0 */ { 0, BX_IA_ERROR },
/* F1 k0 */ { 0, BX_IA_ERROR },
/* F1 */ { 0, BX_IA_ERROR },
/* F2 k0 */ { 0, BX_IA_ERROR },
/* F2 */ { 0, BX_IA_ERROR },
/* F3 k0 */ { 0, BX_IA_ERROR },
/* F3 */ { 0, BX_IA_ERROR },
/* F4 k0 */ { 0, BX_IA_ERROR },
/* F4 */ { 0, BX_IA_ERROR },
/* F5 k0 */ { 0, BX_IA_ERROR },
/* F5 */ { 0, BX_IA_ERROR },
/* F6 k0 */ { 0, BX_IA_ERROR },
/* F6 */ { 0, BX_IA_ERROR },
/* F7 k0 */ { 0, BX_IA_ERROR },
/* F7 */ { 0, BX_IA_ERROR },
/* F8 k0 */ { 0, BX_IA_ERROR },
/* F8 */ { 0, BX_IA_ERROR },
/* F9 k0 */ { 0, BX_IA_ERROR },
/* F9 */ { 0, BX_IA_ERROR },
/* FA k0 */ { 0, BX_IA_ERROR },
/* FA */ { 0, BX_IA_ERROR },
/* FB k0 */ { 0, BX_IA_ERROR },
/* FB */ { 0, BX_IA_ERROR },
/* FC k0 */ { 0, BX_IA_ERROR },
/* FC */ { 0, BX_IA_ERROR },
/* FD k0 */ { 0, BX_IA_ERROR },
/* FD */ { 0, BX_IA_ERROR },
/* FE k0 */ { 0, BX_IA_ERROR },
/* FE */ { 0, BX_IA_ERROR },
/* FF k0 */ { 0, BX_IA_ERROR },
/* FF */ { 0, BX_IA_ERROR }
};
#endif // BX_SUPPORT_EVEX
#endif // BX_AVX_FETCHDECODE_TABLES_H
Reference in New Issue Copy Permalink