2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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2011-02-25 01:05:47 +03:00
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// $Id$
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2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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//
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2021-01-31 11:22:55 +03:00
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// Copyright (C) 2001-2021 The Bochs Project
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2001-04-10 05:04:59 +04:00
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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2009-02-08 12:05:52 +03:00
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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2009-02-08 00:05:31 +03:00
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//
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2001-04-10 05:04:59 +04:00
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2006-03-07 21:16:41 +03:00
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#ifndef BX_IODEV_SERIAL_H
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#define BX_IODEV_SERIAL_H
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2001-04-10 05:04:59 +04:00
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// Peter Grehan (grehan@iprg.nokia.com) coded most of this
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// serial emulation.
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#if BX_USE_SER_SMF
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# define BX_SER_SMF static
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2002-10-25 01:07:56 +04:00
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# define BX_SER_THIS theSerialDevice->
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2001-04-10 05:04:59 +04:00
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#else
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# define BX_SER_SMF
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# define BX_SER_THIS this->
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#endif
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2013-11-01 22:19:52 +04:00
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#ifdef BX_SER_WIN32
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2005-07-10 20:51:09 +04:00
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#define SERIAL_ENABLE
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#endif
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2013-11-01 22:19:52 +04:00
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#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__linux__) || defined(__GNU__) || defined(__GLIBC__) || defined(__APPLE__) || defined(__sun__) || defined(__CYGWIN__)
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2004-01-18 03:18:44 +03:00
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#define SERIAL_ENABLE
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extern "C" {
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#include <termios.h>
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};
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#endif
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2001-04-10 05:04:59 +04:00
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#define BX_SERIAL_MAXDEV 4
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#define BX_PC_CLOCK_XTL 1843200.0
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#define BX_SER_RXIDLE 0
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#define BX_SER_RXPOLL 1
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#define BX_SER_RXWAIT 2
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2004-01-17 18:51:09 +03:00
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#define BX_SER_THR 0
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#define BX_SER_RBR 0
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#define BX_SER_IER 1
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#define BX_SER_IIR 2
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#define BX_SER_FCR 2
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#define BX_SER_LCR 3
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#define BX_SER_MCR 4
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#define BX_SER_LSR 5
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#define BX_SER_MSR 6
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#define BX_SER_SCR 7
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2013-02-23 19:15:59 +04:00
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#define BX_SER_MODE_NULL 0
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#define BX_SER_MODE_FILE 1
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#define BX_SER_MODE_TERM 2
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#define BX_SER_MODE_RAW 3
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#define BX_SER_MODE_MOUSE 4
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#define BX_SER_MODE_SOCKET_CLIENT 5
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#define BX_SER_MODE_SOCKET_SERVER 6
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#define BX_SER_MODE_PIPE_CLIENT 7
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#define BX_SER_MODE_PIPE_SERVER 8
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2004-07-28 23:36:42 +04:00
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2003-10-31 20:23:56 +03:00
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enum {
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BX_SER_INT_IER,
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BX_SER_INT_RXDATA,
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BX_SER_INT_TXHOLD,
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BX_SER_INT_RXLSTAT,
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BX_SER_INT_MODSTAT,
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2003-11-09 03:14:43 +03:00
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BX_SER_INT_FIFO
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2003-10-31 20:23:56 +03:00
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};
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2004-09-06 01:09:46 +04:00
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#if USE_RAW_SERIAL
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class serial_raw;
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#endif
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2001-04-10 05:04:59 +04:00
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typedef struct {
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/*
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* UART internal state
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*/
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2021-01-31 13:50:53 +03:00
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bool ls_interrupt;
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bool ms_interrupt;
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bool rx_interrupt;
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bool tx_interrupt;
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bool fifo_interrupt;
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bool ls_ipending;
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bool ms_ipending;
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bool rx_ipending;
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bool fifo_ipending;
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2001-04-10 05:04:59 +04:00
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2003-10-30 00:00:04 +03:00
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Bit8u IRQ;
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2003-11-09 03:14:43 +03:00
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Bit8u rx_fifo_end;
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Bit8u tx_fifo_end;
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2021-01-31 13:50:53 +03:00
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int baudrate;
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2014-01-26 01:05:49 +04:00
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Bit32u databyte_usec;
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2001-04-10 05:04:59 +04:00
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int rx_timer_index;
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2014-01-26 01:05:49 +04:00
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int tx_timer_index;
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2003-11-09 03:14:43 +03:00
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int fifo_timer_index;
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2001-04-10 05:04:59 +04:00
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2004-07-28 23:36:42 +04:00
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int io_mode;
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2004-01-18 03:18:44 +03:00
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int tty_id;
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2010-11-23 17:59:36 +03:00
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SOCKET socket_id;
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2004-07-28 23:36:42 +04:00
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FILE *output;
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2017-01-27 19:20:04 +03:00
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bx_param_string_c *file;
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2013-11-01 22:19:52 +04:00
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#ifdef BX_SER_WIN32
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2008-05-22 12:13:22 +04:00
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HANDLE pipe;
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#endif
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2004-01-18 03:18:44 +03:00
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2004-01-18 14:58:07 +03:00
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#if USE_RAW_SERIAL
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serial_raw* raw;
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2004-09-06 01:09:46 +04:00
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#endif
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2013-11-01 22:19:52 +04:00
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#if defined(SERIAL_ENABLE) && !defined(BX_SER_WIN32)
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2004-01-18 03:18:44 +03:00
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struct termios term_orig, term_new;
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#endif
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2001-04-10 05:04:59 +04:00
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/*
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* Register definitions
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*/
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Bit8u rxbuffer; /* receiver buffer register (r/o) */
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2003-09-15 00:16:25 +04:00
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Bit8u thrbuffer; /* transmit holding register (w/o) */
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2001-04-10 05:04:59 +04:00
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/* Interrupt Enable Register */
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struct {
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2021-01-31 13:50:53 +03:00
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bool rxdata_enable; /* 1=enable receive data interrupts */
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bool txhold_enable; /* 1=enable tx. holding reg. empty ints */
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bool rxlstat_enable; /* 1=enable rx line status interrupts */
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bool modstat_enable; /* 1=enable modem status interrupts */
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2001-04-10 05:04:59 +04:00
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} int_enable;
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/* Interrupt Identification Register (r/o) */
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struct {
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2021-01-31 13:50:53 +03:00
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bool ipending; /* 0=interrupt pending */
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Bit8u int_ID; /* 3-bit interrupt ID */
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2001-04-10 05:04:59 +04:00
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} int_ident;
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/* FIFO Control Register (w/o) */
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struct {
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2021-01-31 13:50:53 +03:00
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bool enable; /* 1=enable tx and rx FIFOs */
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Bit8u rxtrigger; /* 2-bit code for rx fifo trigger level */
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2001-04-10 05:04:59 +04:00
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} fifo_cntl;
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/* Line Control Register (r/w) */
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struct {
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2021-01-31 13:50:53 +03:00
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Bit8u wordlen_sel; /* 2-bit code for char length */
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bool stopbits; /* select stop bit len */
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bool parity_enable; /* ... */
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bool evenparity_sel; /* ... */
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bool stick_parity; /* ... */
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bool break_cntl; /* 1=send break signal */
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bool dlab; /* divisor latch access bit */
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2001-04-10 05:04:59 +04:00
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} line_cntl;
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/* MODEM Control Register (r/w) */
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struct {
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2021-01-31 13:50:53 +03:00
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bool dtr; /* DTR output value */
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bool rts; /* RTS output value */
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bool out1; /* OUTPUT1 value */
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bool out2; /* OUTPUT2 value */
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bool local_loopback; /* 1=loopback mode */
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2001-04-10 05:04:59 +04:00
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} modem_cntl;
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/* Line Status Register (r/w) */
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struct {
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2021-01-31 13:50:53 +03:00
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bool rxdata_ready; /* 1=receiver data ready */
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bool overrun_error; /* 1=receive overrun detected */
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bool parity_error; /* 1=rx char has a bad parity bit */
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bool framing_error; /* 1=no stop bit detected for rx char */
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bool break_int; /* 1=break signal detected */
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bool thr_empty; /* 1=tx hold register (or fifo) is empty */
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bool tsr_empty; /* 1=shift reg and hold reg empty */
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bool fifo_error; /* 1=at least 1 err condition in fifo */
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2001-04-10 05:04:59 +04:00
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} line_status;
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/* Modem Status Register (r/w) */
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struct {
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2021-01-31 13:50:53 +03:00
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bool delta_cts; /* 1=CTS changed since last read */
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bool delta_dsr; /* 1=DSR changed since last read */
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bool ri_trailedge; /* 1=RI moved from low->high */
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bool delta_dcd; /* 1=CD changed since last read */
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bool cts; /* CTS input value */
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bool dsr; /* DSR input value */
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bool ri; /* RI input value */
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bool dcd; /* DCD input value */
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2001-04-10 05:04:59 +04:00
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} modem_status;
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Bit8u scratch; /* Scratch Register (r/w) */
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2003-09-15 00:16:25 +04:00
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Bit8u tsrbuffer; /* transmit shift register (internal) */
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2003-11-09 03:14:43 +03:00
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Bit8u rx_fifo[16]; /* receive FIFO (internal) */
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Bit8u tx_fifo[16]; /* transmit FIFO (internal) */
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2001-04-10 05:04:59 +04:00
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Bit8u divisor_lsb; /* Divisor latch, least-sig. byte */
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Bit8u divisor_msb; /* Divisor latch, most-sig. byte */
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} bx_serial_t;
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2009-03-03 23:34:50 +03:00
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class bx_serial_c : public bx_devmodel_c {
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2001-04-10 05:04:59 +04:00
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public:
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2006-03-07 21:16:41 +03:00
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bx_serial_c();
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2006-03-08 00:11:20 +03:00
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virtual ~bx_serial_c();
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2006-03-07 21:16:41 +03:00
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virtual void init(void);
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2011-04-30 22:22:35 +04:00
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virtual void reset(unsigned type) {}
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2006-05-27 19:54:49 +04:00
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virtual void register_state(void);
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2001-04-10 05:04:59 +04:00
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private:
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2004-01-18 03:18:44 +03:00
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bx_serial_t s[BX_SERIAL_MAXDEV];
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2001-04-10 05:04:59 +04:00
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2004-12-05 23:23:39 +03:00
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int detect_mouse;
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2004-12-03 00:34:26 +03:00
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int mouse_port;
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2006-12-31 14:56:14 +03:00
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int mouse_type;
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2004-12-03 00:34:26 +03:00
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int mouse_delayed_dx;
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int mouse_delayed_dy;
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2004-12-05 23:23:39 +03:00
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int mouse_delayed_dz;
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2014-01-26 17:48:10 +04:00
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Bit8u mouse_buttons;
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2021-01-31 13:50:53 +03:00
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bool mouse_update;
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2004-12-03 00:34:26 +03:00
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struct {
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int num_elements;
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Bit8u buffer[BX_MOUSE_BUFF_SIZE];
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int head;
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} mouse_internal_buffer;
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2003-10-30 00:00:04 +03:00
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static void lower_interrupt(Bit8u port);
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2003-10-31 20:23:56 +03:00
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static void raise_interrupt(Bit8u port, int type);
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2003-10-30 00:00:04 +03:00
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2003-11-09 03:14:43 +03:00
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static void rx_fifo_enq(Bit8u port, Bit8u data);
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2001-04-10 05:04:59 +04:00
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static void tx_timer_handler(void *);
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BX_SER_SMF void tx_timer(void);
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static void rx_timer_handler(void *);
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BX_SER_SMF void rx_timer(void);
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2003-11-09 03:14:43 +03:00
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static void fifo_timer_handler(void *);
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BX_SER_SMF void fifo_timer(void);
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2021-01-31 11:22:55 +03:00
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static void mouse_enq_static(void *dev, int delta_x, int delta_y, int delta_z, unsigned button_state, bool absxy);
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void mouse_enq(int delta_x, int delta_y, int delta_z, unsigned button_state, bool absxy);
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2014-01-26 17:48:10 +04:00
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void update_mouse_data(void);
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2009-03-03 23:34:50 +03:00
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2001-04-10 05:04:59 +04:00
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static Bit32u read_handler(void *this_ptr, Bit32u address, unsigned io_len);
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static void write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len);
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#if !BX_USE_SER_SMF
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Bit32u read(Bit32u address, unsigned io_len);
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void write(Bit32u address, Bit32u value, unsigned io_len);
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#endif
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2021-02-19 16:13:42 +03:00
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static const char* serial_file_param_handler(bx_param_string_c *param, bool set,
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2017-01-27 19:20:04 +03:00
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const char *oldval, const char *val,
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int maxlen);
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2006-03-07 21:16:41 +03:00
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};
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2001-04-10 05:04:59 +04:00
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2006-03-07 21:16:41 +03:00
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#endif
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