2010-03-26 00:33:07 +03:00
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/////////////////////////////////////////////////////////////////////////
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2011-02-25 00:54:04 +03:00
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// $Id$
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2010-03-26 00:33:07 +03:00
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/////////////////////////////////////////////////////////////////////////
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//
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2018-02-16 10:57:32 +03:00
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// Copyright (c) 2010-2018 Stanislav Shwartsman
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2010-03-26 00:33:07 +03:00
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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2018-02-16 10:57:32 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
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2010-03-26 00:33:07 +03:00
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{
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#if BX_SUPPORT_VMX
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2011-08-10 00:50:51 +04:00
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if (BX_CPU_THIS_PTR in_vmx_guest)
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2012-08-05 17:52:40 +04:00
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VMexit_DR_Access(0 /* write */, i->dst(), i->src());
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2010-03-26 00:33:07 +03:00
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#endif
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2011-08-16 20:49:04 +04:00
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#if BX_CPU_LEVEL >= 5
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2010-03-26 00:33:07 +03:00
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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2012-08-05 17:52:40 +04:00
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if ((i->dst() & 0xE) == 4) {
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: access to DR4/DR5 causes #UD", i->getIaOpcodeNameShort()));
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2010-03-26 00:33:07 +03:00
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exception(BX_UD_EXCEPTION, 0);
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}
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}
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#endif
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// Note: processor clears GD upon entering debug exception
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// handler, to allow access to the debug registers
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2011-03-15 23:20:15 +03:00
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if (BX_CPU_THIS_PTR dr7.get_GD()) {
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: DR7 GD bit is set", i->getIaOpcodeNameShort()));
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2010-03-26 00:33:07 +03:00
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BX_CPU_THIS_PTR debug_trap |= BX_DEBUG_DR_ACCESS_BIT;
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exception(BX_DB_EXCEPTION, 0);
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}
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2011-08-24 01:25:34 +04:00
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// CPL is always 0 in real mode
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if (/* !real_mode() && */ CPL!=0) {
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: CPL!=0 not in real mode", i->getIaOpcodeNameShort()));
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2010-03-26 00:33:07 +03:00
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exception(BX_GP_EXCEPTION, 0);
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}
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2011-12-25 23:35:29 +04:00
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#if BX_SUPPORT_SVM
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2011-12-31 17:58:55 +04:00
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if (BX_CPU_THIS_PTR in_svm_guest) {
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2012-11-02 11:46:50 +04:00
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if (SVM_DR_WRITE_INTERCEPTED(i->dst()))
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Svm_Vmexit(SVM_VMEXIT_DR0_WRITE + i->dst(), BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? i->src() : 0);
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2011-12-31 17:58:55 +04:00
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}
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2011-12-25 23:35:29 +04:00
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#endif
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2010-03-26 00:33:07 +03:00
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invalidate_prefetch_q();
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2012-08-05 17:52:40 +04:00
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Bit32u val_32 = BX_READ_32BIT_REG(i->src());
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2010-03-26 00:33:07 +03:00
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2012-08-05 17:52:40 +04:00
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switch (i->dst()) {
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2010-03-26 00:33:07 +03:00
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case 0: // DR0
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case 1: // DR1
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case 2: // DR2
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case 3: // DR3
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2012-08-05 17:52:40 +04:00
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BX_CPU_THIS_PTR dr[i->dst()] = val_32;
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2011-08-08 09:47:49 +04:00
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TLB_invlpg(val_32);
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2010-03-26 00:33:07 +03:00
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break;
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case 4: // DR4
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// DR4 aliased to DR6 by default. With Debug Extensions on,
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// access to DR4 causes #UD
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case 6: // DR6
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#if BX_CPU_LEVEL <= 4
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// On 386/486 bit12 is settable
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2011-03-15 23:20:15 +03:00
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BX_CPU_THIS_PTR dr6.val32 = (BX_CPU_THIS_PTR dr6.val32 & 0xffff0ff0) |
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2010-03-26 00:33:07 +03:00
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(val_32 & 0x0000f00f);
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#else
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// On Pentium+, bit12 is always zero
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2011-03-15 23:20:15 +03:00
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BX_CPU_THIS_PTR dr6.val32 = (BX_CPU_THIS_PTR dr6.val32 & 0xffff0ff0) |
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2010-03-26 00:33:07 +03:00
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(val_32 & 0x0000e00f);
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#endif
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break;
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case 5: // DR5
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// DR5 aliased to DR7 by default. With Debug Extensions on,
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// access to DR5 causes #UD
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case 7: // DR7
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// Note: 486+ ignore GE and LE flags. On the 386, exact
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// data breakpoint matching does not occur unless it is enabled
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// by setting the LE and/or GE flags.
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#if BX_CPU_LEVEL <= 4
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// 386/486: you can play with all the bits except b10 is always 1
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2011-03-15 23:20:15 +03:00
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BX_CPU_THIS_PTR dr7.set32(val_32 | 0x00000400);
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2010-03-26 00:33:07 +03:00
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#else
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// Pentium+: bits15,14,12 are hardwired to 0, rest are settable.
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// Even bits 11,10 are changeable though reserved.
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2011-03-15 23:20:15 +03:00
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BX_CPU_THIS_PTR dr7.set32((val_32 & 0xffff2fff) | 0x00000400);
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2010-03-26 00:33:07 +03:00
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#endif
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#if BX_X86_DEBUGGER
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2011-04-09 09:12:28 +04:00
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// Some sanity checks...
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if ((BX_CPU_THIS_PTR dr7.get_R_W0() == BX_HWDebugInstruction && BX_CPU_THIS_PTR dr7.get_LEN0()) ||
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(BX_CPU_THIS_PTR dr7.get_R_W1() == BX_HWDebugInstruction && BX_CPU_THIS_PTR dr7.get_LEN1()) ||
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(BX_CPU_THIS_PTR dr7.get_R_W2() == BX_HWDebugInstruction && BX_CPU_THIS_PTR dr7.get_LEN2()) ||
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(BX_CPU_THIS_PTR dr7.get_R_W3() == BX_HWDebugInstruction && BX_CPU_THIS_PTR dr7.get_LEN3()))
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{
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// Instruction breakpoint with LENx not 00b (1-byte length)
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: write of 0x%08x, R/W=00b LEN!=00b", i->getIaOpcodeNameShort(), val_32));
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2011-04-09 09:12:28 +04:00
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}
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2010-03-26 00:33:07 +03:00
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#endif
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2011-04-09 09:12:28 +04:00
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TLB_flush(); // the DR7 write could enable some breakpoints
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2010-03-26 00:33:07 +03:00
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break;
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default:
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: #UD - register index out of range", i->getIaOpcodeNameShort()));
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2010-03-26 00:33:07 +03:00
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exception(BX_UD_EXCEPTION, 0);
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}
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2011-07-07 00:01:18 +04:00
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BX_NEXT_TRACE(i);
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2010-03-26 00:33:07 +03:00
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}
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2018-02-16 10:57:32 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdDd(bxInstruction_c *i)
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2010-03-26 00:33:07 +03:00
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{
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Bit32u val_32;
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#if BX_SUPPORT_VMX
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2011-08-10 00:50:51 +04:00
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if (BX_CPU_THIS_PTR in_vmx_guest)
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2012-08-05 17:52:40 +04:00
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VMexit_DR_Access(1 /* read */, i->src(), i->dst());
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2010-03-26 00:33:07 +03:00
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#endif
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2011-08-16 20:49:04 +04:00
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#if BX_CPU_LEVEL >= 5
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2010-03-26 00:33:07 +03:00
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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2012-08-05 17:52:40 +04:00
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if ((i->src() & 0xE) == 4) {
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: access to DR4/DR5 causes #UD", i->getIaOpcodeNameShort()));
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2010-03-26 00:33:07 +03:00
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exception(BX_UD_EXCEPTION, 0);
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}
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}
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#endif
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// Note: processor clears GD upon entering debug exception
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// handler, to allow access to the debug registers
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2011-03-15 23:20:15 +03:00
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if (BX_CPU_THIS_PTR dr7.get_GD()) {
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: DR7 GD bit is set", i->getIaOpcodeNameShort()));
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2010-03-26 00:33:07 +03:00
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BX_CPU_THIS_PTR debug_trap |= BX_DEBUG_DR_ACCESS_BIT;
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exception(BX_DB_EXCEPTION, 0);
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}
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2011-08-24 01:25:34 +04:00
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// CPL is always 0 in real mode
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if (/* !real_mode() && */ CPL!=0) {
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: CPL!=0 not in real mode", i->getIaOpcodeNameShort()));
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2010-03-26 00:33:07 +03:00
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exception(BX_GP_EXCEPTION, 0);
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}
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2011-12-25 23:35:29 +04:00
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#if BX_SUPPORT_SVM
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2011-12-31 17:58:55 +04:00
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if (BX_CPU_THIS_PTR in_svm_guest) {
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2012-11-02 11:46:50 +04:00
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if (SVM_DR_READ_INTERCEPTED(i->src()))
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Svm_Vmexit(SVM_VMEXIT_DR0_READ + i->src(), BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? i->dst() : 0);
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2011-12-31 17:58:55 +04:00
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}
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2011-12-25 23:35:29 +04:00
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#endif
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2012-08-05 17:52:40 +04:00
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switch (i->src()) {
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2010-03-26 00:33:07 +03:00
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case 0: // DR0
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case 1: // DR1
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case 2: // DR2
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case 3: // DR3
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2012-08-05 17:52:40 +04:00
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val_32 = (Bit32u) BX_CPU_THIS_PTR dr[i->src()];
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2010-03-26 00:33:07 +03:00
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break;
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case 4: // DR4
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// DR4 aliased to DR6 by default. With Debug Extensions ON,
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// access to DR4 causes #UD
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case 6: // DR6
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2011-03-15 23:20:15 +03:00
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val_32 = BX_CPU_THIS_PTR dr6.get32();
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2010-03-26 00:33:07 +03:00
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break;
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case 5: // DR5
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// DR5 aliased to DR7 by default. With Debug Extensions ON,
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// access to DR5 causes #UD
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case 7: // DR7
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2011-03-15 23:20:15 +03:00
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val_32 = BX_CPU_THIS_PTR dr7.get32();
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2010-03-26 00:33:07 +03:00
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break;
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default:
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: #UD - register index out of range", i->getIaOpcodeNameShort()));
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2010-03-26 00:33:07 +03:00
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exception(BX_UD_EXCEPTION, 0);
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}
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2012-08-05 17:52:40 +04:00
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BX_WRITE_32BIT_REGZ(i->dst(), val_32);
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2011-07-07 00:01:18 +04:00
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BX_NEXT_INSTR(i);
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2010-03-26 00:33:07 +03:00
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}
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#if BX_SUPPORT_X86_64
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2018-02-16 10:57:32 +03:00
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DqRq(bxInstruction_c *i)
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2010-03-26 00:33:07 +03:00
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{
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#if BX_SUPPORT_VMX
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2011-08-10 00:50:51 +04:00
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if (BX_CPU_THIS_PTR in_vmx_guest)
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2012-08-05 17:52:40 +04:00
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VMexit_DR_Access(0 /* write */, i->dst(), i->src());
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2010-03-26 00:33:07 +03:00
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#endif
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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2012-08-05 17:52:40 +04:00
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if ((i->dst() & 0xE) == 4) {
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: access to DR4/DR5 causes #UD", i->getIaOpcodeNameShort()));
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2010-03-26 00:33:07 +03:00
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exception(BX_UD_EXCEPTION, 0);
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}
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}
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2012-08-05 17:52:40 +04:00
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if (i->dst() >= 8) {
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: #UD - register index out of range", i->getIaOpcodeNameShort()));
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2010-05-02 19:10:27 +04:00
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exception(BX_UD_EXCEPTION, 0);
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}
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2010-03-26 00:33:07 +03:00
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// Note: processor clears GD upon entering debug exception
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// handler, to allow access to the debug registers
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2011-03-15 23:20:15 +03:00
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if (BX_CPU_THIS_PTR dr7.get_GD()) {
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: DR7 GD bit is set", i->getIaOpcodeNameShort()));
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2010-03-26 00:33:07 +03:00
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BX_CPU_THIS_PTR debug_trap |= BX_DEBUG_DR_ACCESS_BIT;
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exception(BX_DB_EXCEPTION, 0);
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}
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/* #GP(0) if CPL is not 0 */
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if (CPL != 0) {
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2013-12-03 00:06:59 +04:00
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BX_ERROR(("%s: #GP(0) if CPL is not 0", i->getIaOpcodeNameShort()));
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2010-03-26 00:33:07 +03:00
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exception(BX_GP_EXCEPTION, 0);
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}
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2011-12-25 23:35:29 +04:00
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#if BX_SUPPORT_SVM
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2011-12-31 17:58:55 +04:00
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if (BX_CPU_THIS_PTR in_svm_guest) {
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2012-11-02 11:46:50 +04:00
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if (SVM_DR_WRITE_INTERCEPTED(i->dst()))
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Svm_Vmexit(SVM_VMEXIT_DR0_WRITE + i->dst(), BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? i->src() : 0);
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2011-12-31 17:58:55 +04:00
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}
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2011-12-25 23:35:29 +04:00
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#endif
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2010-03-26 00:33:07 +03:00
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invalidate_prefetch_q();
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2012-08-05 17:52:40 +04:00
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Bit64u val_64 = BX_READ_64BIT_REG(i->src());
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2010-03-26 00:33:07 +03:00
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2012-08-05 17:52:40 +04:00
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switch (i->dst()) {
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2010-03-26 00:33:07 +03:00
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case 0: // DR0
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case 1: // DR1
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case 2: // DR2
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case 3: // DR3
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2012-08-05 17:52:40 +04:00
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BX_CPU_THIS_PTR dr[i->dst()] = val_64;
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2011-08-08 09:47:49 +04:00
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TLB_invlpg(val_64);
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2010-03-26 00:33:07 +03:00
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break;
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case 4: // DR4
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// DR4 aliased to DR6 by default. With Debug Extensions ON,
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// access to DR4 causes #UD
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|
case 6: // DR6
|
|
|
|
if (GET32H(val_64)) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: attempt to set upper part of DR6", i->getIaOpcodeNameShort()));
|
2010-03-26 00:33:07 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
// On Pentium+, bit12 is always zero
|
2011-03-15 23:20:15 +03:00
|
|
|
BX_CPU_THIS_PTR dr6.val32 = (BX_CPU_THIS_PTR dr6.val32 & 0xffff0ff0) |
|
2010-03-26 00:33:07 +03:00
|
|
|
(val_64 & 0x0000e00f);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 5: // DR5
|
|
|
|
// DR5 aliased to DR7 by default. With Debug Extensions ON,
|
|
|
|
// access to DR5 causes #UD
|
|
|
|
case 7: // DR7
|
|
|
|
// Note: 486+ ignore GE and LE flags. On the 386, exact
|
|
|
|
// data breakpoint matching does not occur unless it is enabled
|
|
|
|
// by setting the LE and/or GE flags.
|
|
|
|
|
|
|
|
if (GET32H(val_64)) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: attempt to set upper part of DR7", i->getIaOpcodeNameShort()));
|
2010-03-26 00:33:07 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Pentium+: bits15,14,12 are hardwired to 0, rest are settable.
|
|
|
|
// Even bits 11,10 are changeable though reserved.
|
2011-03-15 23:20:15 +03:00
|
|
|
BX_CPU_THIS_PTR dr7.set32((val_64 & 0xffff2fff) | 0x00000400);
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
#if BX_X86_DEBUGGER
|
2011-04-09 09:12:28 +04:00
|
|
|
if ((BX_CPU_THIS_PTR dr7.get_R_W0() == BX_HWDebugInstruction && BX_CPU_THIS_PTR dr7.get_LEN0()) ||
|
|
|
|
(BX_CPU_THIS_PTR dr7.get_R_W1() == BX_HWDebugInstruction && BX_CPU_THIS_PTR dr7.get_LEN1()) ||
|
|
|
|
(BX_CPU_THIS_PTR dr7.get_R_W2() == BX_HWDebugInstruction && BX_CPU_THIS_PTR dr7.get_LEN2()) ||
|
|
|
|
(BX_CPU_THIS_PTR dr7.get_R_W3() == BX_HWDebugInstruction && BX_CPU_THIS_PTR dr7.get_LEN3()))
|
|
|
|
{
|
|
|
|
// Instruction breakpoint with LENx not 00b (1-byte length)
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: write of 0x%08x, R/W=00b LEN!=00b", i->getIaOpcodeNameShort(), BX_CPU_THIS_PTR dr7.get32()));
|
2011-04-09 09:12:28 +04:00
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
2011-04-09 09:12:28 +04:00
|
|
|
|
|
|
|
TLB_flush(); // the DR7 write could enable some breakpoints
|
2010-03-26 00:33:07 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #UD - register index out of range", i->getIaOpcodeNameShort()));
|
2010-03-26 00:33:07 +03:00
|
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_TRACE(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqDq(bxInstruction_c *i)
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
|
|
|
Bit64u val_64;
|
|
|
|
|
|
|
|
#if BX_SUPPORT_VMX
|
2011-08-10 00:50:51 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest)
|
2012-08-05 17:52:40 +04:00
|
|
|
VMexit_DR_Access(1 /* read */, i->src(), i->dst());
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
|
|
|
|
|
|
|
if (BX_CPU_THIS_PTR cr4.get_DE()) {
|
2012-08-05 17:52:40 +04:00
|
|
|
if ((i->src() & 0xE) == 4) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: access to DR4/DR5 causes #UD", i->getIaOpcodeNameShort()));
|
2010-03-26 00:33:07 +03:00
|
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
if (i->src() >= 8) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #UD - register index out of range", i->getIaOpcodeNameShort()));
|
2010-05-02 19:10:27 +04:00
|
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2010-03-26 00:33:07 +03:00
|
|
|
// Note: processor clears GD upon entering debug exception
|
|
|
|
// handler, to allow access to the debug registers
|
2011-03-15 23:20:15 +03:00
|
|
|
if (BX_CPU_THIS_PTR dr7.get_GD()) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: DR7 GD bit is set", i->getIaOpcodeNameShort()));
|
2010-03-26 00:33:07 +03:00
|
|
|
BX_CPU_THIS_PTR debug_trap |= BX_DEBUG_DR_ACCESS_BIT;
|
|
|
|
exception(BX_DB_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* #GP(0) if CPL is not 0 */
|
|
|
|
if (CPL != 0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #GP(0) if CPL is not 0", i->getIaOpcodeNameShort()));
|
2010-03-26 00:33:07 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2011-12-25 23:35:29 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
2011-12-31 17:58:55 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
2012-11-02 11:46:50 +04:00
|
|
|
if (SVM_DR_READ_INTERCEPTED(i->src()))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_DR0_READ + i->src(), BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? i->dst() : 0);
|
2011-12-31 17:58:55 +04:00
|
|
|
}
|
2011-12-25 23:35:29 +04:00
|
|
|
#endif
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
switch (i->src()) {
|
2010-03-26 00:33:07 +03:00
|
|
|
case 0: // DR0
|
|
|
|
case 1: // DR1
|
|
|
|
case 2: // DR2
|
|
|
|
case 3: // DR3
|
2012-08-05 17:52:40 +04:00
|
|
|
val_64 = BX_CPU_THIS_PTR dr[i->src()];
|
2010-03-26 00:33:07 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
case 4: // DR4
|
|
|
|
// DR4 aliased to DR6 by default. With Debug Extensions ON,
|
|
|
|
// access to DR4 causes #UD
|
|
|
|
case 6: // DR6
|
2011-03-15 23:20:15 +03:00
|
|
|
val_64 = BX_CPU_THIS_PTR dr6.get32();
|
2010-03-26 00:33:07 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
case 5: // DR5
|
|
|
|
// DR5 aliased to DR7 by default. With Debug Extensions ON,
|
|
|
|
// access to DR5 causes #UD
|
|
|
|
case 7: // DR7
|
2011-03-15 23:20:15 +03:00
|
|
|
val_64 = BX_CPU_THIS_PTR dr7.get32();
|
2010-03-26 00:33:07 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #UD - register index out of range", i->getIaOpcodeNameShort()));
|
2010-03-26 00:33:07 +03:00
|
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_WRITE_64BIT_REG(i->dst(), val_64);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
#endif // #if BX_SUPPORT_X86_64
|
|
|
|
|
2012-11-02 11:46:50 +04:00
|
|
|
#define BX_SVM_CR_WRITE_MASK (BX_CONST64(1) << 63)
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR0Rd(bxInstruction_c *i)
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
2011-08-24 01:25:34 +04:00
|
|
|
// CPL is always 0 in real mode
|
|
|
|
if (/* !real_mode() && */ CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: CPL!=0 not in real mode", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
Bit32u val_32 = BX_READ_32BIT_REG(i->src());
|
2011-09-03 19:22:56 +04:00
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
if (i->dst() == 0) {
|
2011-09-03 19:22:56 +04:00
|
|
|
// CR0
|
2010-12-20 01:36:19 +03:00
|
|
|
#if BX_SUPPORT_VMX
|
2011-09-03 19:22:56 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest)
|
|
|
|
val_32 = (Bit32u) VMexit_CR0_Write(i, val_32);
|
2010-05-02 19:10:27 +04:00
|
|
|
#endif
|
2012-11-02 11:46:50 +04:00
|
|
|
if (! SetCR0(i, val_32))
|
2011-09-03 19:22:56 +04:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
2011-03-23 01:18:40 +03:00
|
|
|
|
2011-09-03 19:22:56 +04:00
|
|
|
BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_MOV_CR0, val_32);
|
|
|
|
}
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
|
|
else {
|
|
|
|
// AMD feature: LOCK CR0 allows CR8 access even in 32-bit mode
|
|
|
|
WriteCR8(i, val_32);
|
|
|
|
}
|
|
|
|
#endif
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_TRACE(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
2010-05-02 19:10:27 +04:00
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR2Rd(bxInstruction_c *i)
|
2010-12-20 01:36:19 +03:00
|
|
|
{
|
2011-08-24 01:25:34 +04:00
|
|
|
// CPL is always 0 in real mode
|
|
|
|
if (/* !real_mode() && */ CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: CPL!=0 not in real mode", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
2010-05-02 19:10:27 +04:00
|
|
|
}
|
|
|
|
|
2011-12-26 20:33:13 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
2012-11-02 11:46:50 +04:00
|
|
|
if(SVM_CR_WRITE_INTERCEPTED(2)) {
|
|
|
|
if (BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR2_WRITE, BX_SVM_CR_WRITE_MASK | i->src());
|
|
|
|
else
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR2_WRITE);
|
|
|
|
}
|
2011-12-26 20:33:13 +04:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_CPU_THIS_PTR cr2 = BX_READ_32BIT_REG(i->src());
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR3Rd(bxInstruction_c *i)
|
2010-12-20 01:36:19 +03:00
|
|
|
{
|
2011-08-24 01:25:34 +04:00
|
|
|
// CPL is always 0 in real mode
|
|
|
|
if (/* !real_mode() && */ CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: CPL!=0 not in real mode", i->getIaOpcodeNameShort()));
|
2010-03-26 00:33:07 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2010-05-02 19:10:27 +04:00
|
|
|
invalidate_prefetch_q();
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
Bit32u val_32 = BX_READ_32BIT_REG(i->src());
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
#if BX_SUPPORT_VMX
|
2011-08-10 00:50:51 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest)
|
|
|
|
VMexit_CR3_Write(i, val_32);
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
|
|
|
|
2012-11-02 11:46:50 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
|
|
if(SVM_CR_WRITE_INTERCEPTED(3)) {
|
|
|
|
if (BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR3_WRITE, BX_SVM_CR_WRITE_MASK | i->src());
|
|
|
|
else
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR3_WRITE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-04-03 22:00:30 +04:00
|
|
|
#if BX_CPU_LEVEL >= 6
|
2010-12-20 01:36:19 +03:00
|
|
|
if (BX_CPU_THIS_PTR cr0.get_PG() && BX_CPU_THIS_PTR cr4.get_PAE() && !long_mode()) {
|
|
|
|
if (! CheckPDPTR(val_32)) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: PDPTR check failed !", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
|
|
|
|
2010-12-20 01:36:19 +03:00
|
|
|
if (! SetCR3(val_32))
|
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2010-12-20 01:36:19 +03:00
|
|
|
BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_MOV_CR3, val_32);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_TRACE(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR4Rd(bxInstruction_c *i)
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
2011-08-16 20:49:04 +04:00
|
|
|
#if BX_CPU_LEVEL >= 5
|
2011-08-24 01:25:34 +04:00
|
|
|
// CPL is always 0 in real mode
|
|
|
|
if (/* !real_mode() && */ CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: CPL!=0 not in real mode", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
Bit32u val_32 = BX_READ_32BIT_REG(i->src());
|
2010-12-20 01:36:19 +03:00
|
|
|
#if BX_SUPPORT_VMX
|
2011-08-10 00:50:51 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest)
|
|
|
|
val_32 = (Bit32u) VMexit_CR4_Write(i, val_32);
|
2010-12-20 01:36:19 +03:00
|
|
|
#endif
|
2012-11-02 11:46:50 +04:00
|
|
|
if (! SetCR4(i, val_32))
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
2011-03-23 01:18:40 +03:00
|
|
|
|
|
|
|
BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_MOV_CR4, val_32);
|
2011-08-16 20:49:04 +04:00
|
|
|
#endif
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_TRACE(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
2010-05-02 19:10:27 +04:00
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCR0(bxInstruction_c *i)
|
2010-12-20 01:36:19 +03:00
|
|
|
{
|
2011-08-24 01:25:34 +04:00
|
|
|
// CPL is always 0 in real mode
|
|
|
|
if (/* !real_mode() && */ CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: CPL!=0 not in real mode", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
2010-05-02 19:10:27 +04:00
|
|
|
}
|
|
|
|
|
2011-09-03 19:22:56 +04:00
|
|
|
Bit32u val_32 = 0;
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
if (i->src() == 0) {
|
2011-09-03 19:22:56 +04:00
|
|
|
// CR0
|
2012-11-02 11:46:50 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
|
|
if(SVM_CR_READ_INTERCEPTED(0))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR0_READ, BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? i->dst() : 0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-09-03 19:22:56 +04:00
|
|
|
val_32 = (Bit32u) read_CR0(); /* correctly handle VMX */
|
|
|
|
}
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
|
|
else {
|
|
|
|
// AMD feature: LOCK CR0 allows CR8 access even in 32-bit mode
|
|
|
|
val_32 = ReadCR8(i);
|
|
|
|
}
|
|
|
|
#endif
|
2010-12-20 01:36:19 +03:00
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_WRITE_32BIT_REGZ(i->dst(), val_32);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCR2(bxInstruction_c *i)
|
2010-12-20 01:36:19 +03:00
|
|
|
{
|
2011-08-24 01:25:34 +04:00
|
|
|
// CPL is always 0 in real mode
|
|
|
|
if (/* !real_mode() && */ CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: CPL!=0 not in real mode", i->getIaOpcodeNameShort()));
|
2010-03-26 00:33:07 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2011-12-26 20:33:13 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
2012-11-02 11:46:50 +04:00
|
|
|
if(SVM_CR_READ_INTERCEPTED(2))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR2_READ, BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? i->dst() : 0);
|
2011-12-26 20:33:13 +04:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) BX_CPU_THIS_PTR cr2);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCR3(bxInstruction_c *i)
|
2010-12-20 01:36:19 +03:00
|
|
|
{
|
2011-08-24 01:25:34 +04:00
|
|
|
// CPL is always 0 in real mode
|
|
|
|
if (/* !real_mode() && */ CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: CPL!=0 not in real mode", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2011-12-26 20:33:13 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
2012-11-02 11:46:50 +04:00
|
|
|
if(SVM_CR_READ_INTERCEPTED(3))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR3_READ, BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? i->dst() : 0);
|
2011-12-26 20:33:13 +04:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-03-26 00:33:07 +03:00
|
|
|
#if BX_SUPPORT_VMX
|
2011-08-10 00:50:51 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest)
|
|
|
|
VMexit_CR3_Read(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
2010-12-20 01:36:19 +03:00
|
|
|
|
|
|
|
Bit32u val_32 = (Bit32u) BX_CPU_THIS_PTR cr3;
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_WRITE_32BIT_REGZ(i->dst(), val_32);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdCR4(bxInstruction_c *i)
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
2011-08-16 20:49:04 +04:00
|
|
|
#if BX_CPU_LEVEL >= 5
|
2011-08-24 01:25:34 +04:00
|
|
|
// CPL is always 0 in real mode
|
|
|
|
if (/* !real_mode() && */ CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: CPL!=0 not in real mode", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
2010-05-02 19:10:27 +04:00
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2012-11-02 11:46:50 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
|
|
if(SVM_CR_READ_INTERCEPTED(4))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR4_READ, BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? i->dst() : 0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-12-20 01:36:19 +03:00
|
|
|
Bit32u val_32 = (Bit32u) read_CR4(); /* correctly handle VMX */
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_WRITE_32BIT_REGZ(i->dst(), val_32);
|
2011-08-16 20:49:04 +04:00
|
|
|
#endif
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
#if BX_SUPPORT_X86_64
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR0Rq(bxInstruction_c *i)
|
2010-12-20 01:36:19 +03:00
|
|
|
{
|
2010-03-26 00:33:07 +03:00
|
|
|
if (CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #GP(0) if CPL is not 0", i->getIaOpcodeNameShort()));
|
2010-03-26 00:33:07 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2010-05-02 19:10:27 +04:00
|
|
|
invalidate_prefetch_q();
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
Bit64u val_64 = BX_READ_64BIT_REG(i->src());
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
if (i->dst() == 0) {
|
2010-12-20 01:36:19 +03:00
|
|
|
// CR0
|
2010-03-26 00:33:07 +03:00
|
|
|
#if BX_SUPPORT_VMX
|
2011-08-10 00:50:51 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest)
|
|
|
|
val_64 = VMexit_CR0_Write(i, val_64);
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
2012-11-02 11:46:50 +04:00
|
|
|
if (! SetCR0(i, val_64))
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
2011-03-23 01:18:40 +03:00
|
|
|
|
|
|
|
BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_MOV_CR0, (Bit32u) val_64);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
|
|
|
else {
|
2011-09-03 19:22:56 +04:00
|
|
|
WriteCR8(i, val_64);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_TRACE(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR2Rq(bxInstruction_c *i)
|
2010-12-20 01:36:19 +03:00
|
|
|
{
|
2012-08-05 17:52:40 +04:00
|
|
|
if (i->dst() != 2) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #UD - register index out of range", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_UD_EXCEPTION, 0);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
2010-12-20 01:36:19 +03:00
|
|
|
|
|
|
|
if (CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #GP(0) if CPL is not 0", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2011-12-27 00:51:57 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
2012-11-02 11:46:50 +04:00
|
|
|
if(SVM_CR_WRITE_INTERCEPTED(2)) {
|
|
|
|
if (BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR2_WRITE, BX_SVM_CR_WRITE_MASK | i->src());
|
|
|
|
else
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR2_WRITE);
|
|
|
|
}
|
2011-12-27 00:51:57 +04:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_CPU_THIS_PTR cr2 = BX_READ_64BIT_REG(i->src());
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR3Rq(bxInstruction_c *i)
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
2012-08-05 17:52:40 +04:00
|
|
|
if (i->dst() != 3) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #UD - register index out of range", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #GP(0) if CPL is not 0", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
Bit64u val_64 = BX_READ_64BIT_REG(i->src());
|
2010-12-20 01:36:19 +03:00
|
|
|
|
|
|
|
#if BX_SUPPORT_VMX
|
2011-08-10 00:50:51 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest)
|
|
|
|
VMexit_CR3_Write(i, val_64);
|
2010-12-20 01:36:19 +03:00
|
|
|
#endif
|
2010-05-02 19:10:27 +04:00
|
|
|
|
2012-11-02 11:46:50 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
|
|
if(SVM_CR_WRITE_INTERCEPTED(3)) {
|
|
|
|
if (BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR3_WRITE, BX_SVM_CR_WRITE_MASK | i->src());
|
|
|
|
else
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR3_WRITE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2017-12-25 22:49:45 +03:00
|
|
|
// allow bit 63 (hint that TLB doesn't need to be cleared) to be set when
|
|
|
|
// PCIDE is set, but ignore the hint if given
|
|
|
|
if (BX_CPU_THIS_PTR cr4.get_PCIDE()) {
|
|
|
|
val_64 &= ~(BX_CONST64(1)<<63);
|
|
|
|
}
|
|
|
|
|
2010-12-20 01:36:19 +03:00
|
|
|
if (! SetCR3(val_64))
|
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
|
|
|
|
BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_MOV_CR3, val_64);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_TRACE(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CR4Rq(bxInstruction_c *i)
|
2010-12-20 01:36:19 +03:00
|
|
|
{
|
2012-08-05 17:52:40 +04:00
|
|
|
if (i->dst() != 4) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #UD - register index out of range", i->getIaOpcodeNameShort()));
|
2010-05-02 19:10:27 +04:00
|
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2010-12-20 01:36:19 +03:00
|
|
|
if (CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #GP(0) if CPL is not 0", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
invalidate_prefetch_q();
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
Bit64u val_64 = BX_READ_64BIT_REG(i->src());
|
2010-12-20 01:36:19 +03:00
|
|
|
#if BX_SUPPORT_VMX
|
2011-08-10 00:50:51 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest)
|
|
|
|
val_64 = VMexit_CR4_Write(i, val_64);
|
2010-12-20 01:36:19 +03:00
|
|
|
#endif
|
2012-11-02 11:46:50 +04:00
|
|
|
if (! SetCR4(i, val_64))
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
2011-03-23 01:18:40 +03:00
|
|
|
|
|
|
|
BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_MOV_CR4, (Bit32u) val_64);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_TRACE(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR0(bxInstruction_c *i)
|
2010-12-20 01:36:19 +03:00
|
|
|
{
|
2010-03-26 00:33:07 +03:00
|
|
|
if (CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #GP(0) if CPL is not 0", i->getIaOpcodeNameShort()));
|
2010-03-26 00:33:07 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2011-09-03 19:22:56 +04:00
|
|
|
Bit64u val_64;
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
if (i->src() == 0) {
|
2010-12-20 01:36:19 +03:00
|
|
|
// CR0
|
2012-11-02 11:46:50 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
|
|
if(SVM_CR_READ_INTERCEPTED(0))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR0_READ, BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? i->dst() : 0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-12-20 01:36:19 +03:00
|
|
|
val_64 = read_CR0(); /* correctly handle VMX */
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
// CR8
|
2011-09-03 19:22:56 +04:00
|
|
|
val_64 = ReadCR8(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_WRITE_64BIT_REG(i->dst(), val_64);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
2010-12-20 01:36:19 +03:00
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR2(bxInstruction_c *i)
|
2010-12-20 01:36:19 +03:00
|
|
|
{
|
2012-08-05 17:52:40 +04:00
|
|
|
if (i->src() != 2) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #UD - register index out of range", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #GP(0) if CPL is not 0", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2011-12-27 00:51:57 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
2012-11-02 11:46:50 +04:00
|
|
|
if(SVM_CR_READ_INTERCEPTED(2))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR2_READ, BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? i->dst() : 0);
|
2011-12-27 00:51:57 +04:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_WRITE_64BIT_REG(i->dst(), BX_CPU_THIS_PTR cr2);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR3(bxInstruction_c *i)
|
2010-12-20 01:36:19 +03:00
|
|
|
{
|
2012-08-05 17:52:40 +04:00
|
|
|
if (i->src() != 3) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #UD - register index out of range", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #GP(0) if CPL is not 0", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2011-12-27 00:51:57 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
2012-11-02 11:46:50 +04:00
|
|
|
if(SVM_CR_READ_INTERCEPTED(3))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR3_READ, BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? i->dst() : 0);
|
2011-12-27 00:51:57 +04:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-12-20 01:36:19 +03:00
|
|
|
#if BX_SUPPORT_VMX
|
2011-08-10 00:50:51 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest)
|
|
|
|
VMexit_CR3_Read(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
#endif
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_WRITE_64BIT_REG(i->dst(), BX_CPU_THIS_PTR cr3);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqCR4(bxInstruction_c *i)
|
2010-12-20 01:36:19 +03:00
|
|
|
{
|
2012-08-05 17:52:40 +04:00
|
|
|
if (i->src() != 4) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #UD - register index out of range", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_UD_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: #GP(0) if CPL is not 0", i->getIaOpcodeNameShort()));
|
2010-12-20 01:36:19 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2012-11-02 11:46:50 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
|
|
if(SVM_CR_READ_INTERCEPTED(4))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR4_READ, BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? i->dst() : 0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-12-20 01:36:19 +03:00
|
|
|
Bit64u val_64 = read_CR4(); /* correctly handle VMX */
|
|
|
|
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_WRITE_64BIT_REG(i->dst(), val_64);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-12-20 01:36:19 +03:00
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif // #if BX_SUPPORT_X86_64
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LMSW_Ew(bxInstruction_c *i)
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
|
|
|
Bit16u msw;
|
|
|
|
|
2011-08-24 01:25:34 +04:00
|
|
|
// CPL is always 0 in real mode
|
|
|
|
if (/* !real_mode() && */ CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: CPL!=0 not in real mode", i->getIaOpcodeNameShort()));
|
2010-03-26 00:33:07 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
2011-12-26 20:33:13 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
|
|
if(SVM_CR_WRITE_INTERCEPTED(0)) Svm_Vmexit(SVM_VMEXIT_CR0_WRITE);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-03-26 00:33:07 +03:00
|
|
|
if (i->modC0()) {
|
2012-08-05 17:52:40 +04:00
|
|
|
msw = BX_READ_16BIT_REG(i->src());
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
else {
|
|
|
|
/* use RMAddr(i) to save address for VMexit */
|
2015-05-17 00:06:59 +03:00
|
|
|
RMAddr(i) = BX_CPU_RESOLVE_ADDR(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
/* pointer, segment address pair */
|
|
|
|
msw = read_virtual_word(i->seg(), RMAddr(i));
|
|
|
|
}
|
|
|
|
|
|
|
|
// LMSW does not affect PG,CD,NW,AM,WP,NE,ET bits, and cannot clear PE
|
|
|
|
|
|
|
|
#if BX_SUPPORT_VMX
|
2011-08-10 00:50:51 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest)
|
|
|
|
msw = VMexit_LMSW(i, msw);
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
|
|
|
|
|
|
|
// LMSW cannot clear PE
|
|
|
|
if (BX_CPU_THIS_PTR cr0.get_PE())
|
2011-12-26 23:57:39 +04:00
|
|
|
msw |= BX_CR0_PE_MASK; // adjust PE bit to current value of 1
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
msw &= 0xf; // LMSW only affects last 4 flags
|
|
|
|
|
|
|
|
Bit32u cr0 = (BX_CPU_THIS_PTR cr0.get32() & 0xfffffff0) | msw;
|
2012-11-02 11:46:50 +04:00
|
|
|
if (! SetCR0(i, cr0))
|
2010-03-26 00:33:07 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_TRACE(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SMSW_EwR(bxInstruction_c *i)
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
2016-04-21 18:39:49 +03:00
|
|
|
#if BX_CPU_LEVEL >= 5
|
2016-04-15 14:35:32 +03:00
|
|
|
if (CPL!=0 && BX_CPU_THIS_PTR cr4.get_UMIP()) {
|
|
|
|
BX_ERROR(("SMSW: CPL != 0 causes #GP when CR4.UMIP set"));
|
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
2016-04-21 18:39:49 +03:00
|
|
|
#endif
|
2016-04-15 14:35:32 +03:00
|
|
|
|
2010-03-26 00:33:07 +03:00
|
|
|
Bit32u msw = (Bit32u) read_CR0(); // handle CR0 shadow in VMX
|
|
|
|
|
|
|
|
if (i->os32L()) {
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_WRITE_32BIT_REGZ(i->dst(), msw);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
else {
|
2012-08-05 17:52:40 +04:00
|
|
|
BX_WRITE_16BIT_REG(i->dst(), msw & 0xffff);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SMSW_EwM(bxInstruction_c *i)
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
2016-05-02 20:33:06 +03:00
|
|
|
#if BX_CPU_LEVEL >= 5
|
2016-04-15 14:35:32 +03:00
|
|
|
if (CPL!=0 && BX_CPU_THIS_PTR cr4.get_UMIP()) {
|
|
|
|
BX_ERROR(("SMSW: CPL != 0 causes #GP when CR4.UMIP set"));
|
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
2016-05-02 20:33:06 +03:00
|
|
|
#endif
|
2016-04-15 14:35:32 +03:00
|
|
|
|
2010-03-26 00:33:07 +03:00
|
|
|
Bit16u msw = read_CR0() & 0xffff; // handle CR0 shadow in VMX
|
2015-05-17 00:06:59 +03:00
|
|
|
bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
write_virtual_word(i->seg(), eaddr, msw);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
bx_address BX_CPU_C::read_CR0(void)
|
|
|
|
{
|
2011-12-26 20:33:13 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
2011-12-30 16:24:22 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
2012-11-02 11:46:50 +04:00
|
|
|
// used for SMSW instruction only
|
2011-12-26 20:33:13 +04:00
|
|
|
if(SVM_CR_READ_INTERCEPTED(0)) Svm_Vmexit(SVM_VMEXIT_CR0_READ);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-11-02 11:46:50 +04:00
|
|
|
bx_address cr0_val = BX_CPU_THIS_PTR cr0.get32();
|
|
|
|
|
2010-03-26 00:33:07 +03:00
|
|
|
#if BX_SUPPORT_VMX
|
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
|
|
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
|
|
|
|
cr0_val = (cr0_val & ~vm->vm_cr0_mask) | (vm->vm_cr0_read_shadow & vm->vm_cr0_mask);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return cr0_val;
|
|
|
|
}
|
|
|
|
|
2011-08-16 20:49:04 +04:00
|
|
|
#if BX_CPU_LEVEL >= 5
|
2010-03-26 00:33:07 +03:00
|
|
|
bx_address BX_CPU_C::read_CR4(void)
|
|
|
|
{
|
|
|
|
bx_address cr4_val = BX_CPU_THIS_PTR cr4.get32();
|
|
|
|
|
|
|
|
#if BX_SUPPORT_VMX
|
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
|
|
|
VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
|
|
|
|
cr4_val = (cr4_val & ~vm->vm_cr4_mask) | (vm->vm_cr4_read_shadow & vm->vm_cr4_mask);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return cr4_val;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::check_CR0(bx_address cr0_val)
|
|
|
|
{
|
|
|
|
bx_cr0_t temp_cr0;
|
|
|
|
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
|
|
if (GET32H(cr0_val)) {
|
|
|
|
BX_ERROR(("check_CR0(): trying to set CR0 > 32 bits"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-11-23 17:59:36 +03:00
|
|
|
temp_cr0.set32((Bit32u) cr0_val);
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2013-02-27 23:11:28 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (! BX_CPU_THIS_PTR in_svm_guest) // it should be fine to enter paged real mode in SVM guest
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
if (temp_cr0.get_PG() && !temp_cr0.get_PE()) {
|
|
|
|
BX_ERROR(("check_CR0(0x%08x): attempt to set CR0.PG with CR0.PE cleared !", temp_cr0.get32()));
|
|
|
|
return 0;
|
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
#if BX_CPU_LEVEL >= 4
|
|
|
|
if (temp_cr0.get_NW() && !temp_cr0.get_CD()) {
|
|
|
|
BX_ERROR(("check_CR0(0x%08x): attempt to set CR0.NW with CR0.CD cleared !", temp_cr0.get32()));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if BX_SUPPORT_VMX
|
|
|
|
if (BX_CPU_THIS_PTR in_vmx) {
|
2010-04-09 15:31:55 +04:00
|
|
|
if (!temp_cr0.get_NE()) {
|
|
|
|
BX_ERROR(("check_CR0(0x%08x): attempt to clear CR0.NE in vmx mode !", temp_cr0.get32()));
|
2010-03-26 00:33:07 +03:00
|
|
|
return 0;
|
|
|
|
}
|
2010-04-09 15:31:55 +04:00
|
|
|
if (!BX_CPU_THIS_PTR in_vmx_guest && !SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_UNRESTRICTED_GUEST)) {
|
|
|
|
if (!temp_cr0.get_PE() || !temp_cr0.get_PG()) {
|
|
|
|
BX_ERROR(("check_CR0(0x%08x): attempt to clear CR0.PE/CR0.PG in vmx mode !", temp_cr0.get32()));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2012-11-02 11:46:50 +04:00
|
|
|
bx_bool BX_CPU_C::SetCR0(bxInstruction_c *i, bx_address val)
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
|
|
|
if (! check_CR0(val)) return 0;
|
|
|
|
|
|
|
|
Bit32u val_32 = GET32L(val);
|
|
|
|
|
2011-05-30 00:42:47 +04:00
|
|
|
#if BX_CPU_LEVEL >= 6
|
2010-03-26 00:33:07 +03:00
|
|
|
bx_bool pg = (val_32 >> 31) & 0x1;
|
2011-05-30 00:42:47 +04:00
|
|
|
#endif
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
|
|
if (! BX_CPU_THIS_PTR cr0.get_PG() && pg) {
|
|
|
|
if (BX_CPU_THIS_PTR efer.get_LME()) {
|
|
|
|
if (!BX_CPU_THIS_PTR cr4.get_PAE()) {
|
|
|
|
BX_ERROR(("SetCR0: attempt to enter x86-64 long mode without enabling CR4.PAE !"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l) {
|
|
|
|
BX_ERROR(("SetCR0: attempt to enter x86-64 long mode with CS.L !"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
if (BX_CPU_THIS_PTR tr.cache.type <= 3) {
|
|
|
|
BX_ERROR(("SetCR0: attempt to enter x86-64 long mode with TSS286 in TR !"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
BX_CPU_THIS_PTR efer.set_LMA(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if (BX_CPU_THIS_PTR cr0.get_PG() && ! pg) {
|
|
|
|
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
|
|
|
|
BX_ERROR(("SetCR0(): attempt to leave 64 bit mode directly to legacy mode !"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
if (BX_CPU_THIS_PTR efer.get_LMA()) {
|
2010-04-29 23:34:32 +04:00
|
|
|
if (BX_CPU_THIS_PTR cr4.get_PCIDE()) {
|
|
|
|
BX_ERROR(("SetCR0(): attempt to leave 64 bit mode with CR4.PCIDE set !"));
|
|
|
|
return 0;
|
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
if (BX_CPU_THIS_PTR gen_reg[BX_64BIT_REG_RIP].dword.hrx != 0) {
|
2010-05-12 18:55:12 +04:00
|
|
|
BX_PANIC(("SetCR0(): attempt to leave x86-64 LONG mode with RIP upper != 0"));
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
BX_CPU_THIS_PTR efer.set_LMA(0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif // #if BX_SUPPORT_X86_64
|
|
|
|
|
|
|
|
// handle reserved bits behaviour
|
|
|
|
#if BX_CPU_LEVEL == 3
|
|
|
|
val_32 = val_32 | 0x7ffffff0;
|
|
|
|
#elif BX_CPU_LEVEL == 4
|
|
|
|
val_32 = (val_32 | 0x00000010) & 0xe005003f;
|
|
|
|
#elif BX_CPU_LEVEL == 5
|
|
|
|
val_32 = val_32 | 0x00000010;
|
|
|
|
#elif BX_CPU_LEVEL == 6
|
|
|
|
val_32 = (val_32 | 0x00000010) & 0xe005003f;
|
|
|
|
#else
|
|
|
|
#error "SetCR0: implement reserved bits behaviour for this CPU_LEVEL"
|
|
|
|
#endif
|
2011-12-26 20:33:13 +04:00
|
|
|
|
|
|
|
Bit32u oldCR0 = BX_CPU_THIS_PTR cr0.get32();
|
|
|
|
|
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
2012-11-02 11:46:50 +04:00
|
|
|
if(SVM_CR_WRITE_INTERCEPTED(0)) {
|
|
|
|
// LMSW instruction should VMEXIT before
|
|
|
|
if (BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR0_WRITE, BX_SVM_CR_WRITE_MASK | i->src());
|
|
|
|
else
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR0_WRITE);
|
|
|
|
}
|
2011-12-26 20:33:13 +04:00
|
|
|
|
2011-12-27 23:42:11 +04:00
|
|
|
if (SVM_INTERCEPT(SVM_INTERCEPT0_CR0_WRITE_NO_TS_MP)) {
|
2011-12-26 20:33:13 +04:00
|
|
|
if ((oldCR0 & 0xfffffff5) != (val_32 & 0xfffffff5)) {
|
|
|
|
// any other bit except TS or MP had changed
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR0_SEL_WRITE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
|
|
if (pg && BX_CPU_THIS_PTR cr4.get_PAE() && !long_mode()) {
|
|
|
|
if (! CheckPDPTR(BX_CPU_THIS_PTR cr3)) {
|
|
|
|
BX_ERROR(("SetCR0(): PDPTR check failed !"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-03-26 00:33:07 +03:00
|
|
|
BX_CPU_THIS_PTR cr0.set32(val_32);
|
|
|
|
|
2012-03-25 23:07:17 +04:00
|
|
|
#if BX_CPU_LEVEL >= 4
|
2010-04-22 21:51:37 +04:00
|
|
|
handleAlignmentCheck(/* CR0.AC reloaded */);
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
|
|
|
|
|
|
|
handleCpuModeChange();
|
|
|
|
|
2010-12-19 10:06:40 +03:00
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
|
|
handleSseModeChange();
|
2011-03-19 23:09:34 +03:00
|
|
|
#if BX_SUPPORT_AVX
|
|
|
|
handleAvxModeChange();
|
|
|
|
#endif
|
2010-12-19 10:06:40 +03:00
|
|
|
#endif
|
|
|
|
|
2010-03-26 00:33:07 +03:00
|
|
|
// Modification of PG,PE flushes TLB cache according to docs.
|
|
|
|
// Additionally, the TLB strategy is based on the current value of
|
|
|
|
// WP, so if that changes we must also flush the TLB.
|
2016-03-04 14:59:32 +03:00
|
|
|
if ((oldCR0 & 0x80010001) != (val_32 & 0x80010001)) {
|
2010-03-26 00:33:07 +03:00
|
|
|
TLB_flush(); // Flush Global entries also
|
2016-03-04 14:59:32 +03:00
|
|
|
#if BX_SUPPORT_PKEYS
|
|
|
|
set_PKRU(BX_CPU_THIS_PTR pkru); // recalculate protection keys due to CR0.WP change
|
|
|
|
#endif
|
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2011-08-16 20:49:04 +04:00
|
|
|
#if BX_CPU_LEVEL >= 5
|
2010-04-29 23:34:32 +04:00
|
|
|
Bit32u BX_CPU_C::get_cr4_allow_mask(void)
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
2010-11-23 17:59:36 +03:00
|
|
|
Bit32u allowMask = 0;
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
// CR4 bits definitions:
|
2012-10-01 16:08:23 +04:00
|
|
|
// [31-22] Reserved, Must be Zero
|
2016-04-15 14:35:32 +03:00
|
|
|
// [22] PKE: Protection Keys Enable R/W
|
2013-04-17 23:46:11 +04:00
|
|
|
// [21] SMAP: Supervisor Mode Access Prevention R/W
|
2011-05-29 20:28:26 +04:00
|
|
|
// [20] SMEP: Supervisor Mode Execution Protection R/W
|
|
|
|
// [19] Reserved, Must be Zero
|
2010-03-26 00:33:07 +03:00
|
|
|
// [18] OSXSAVE: Operating System XSAVE Support R/W
|
2010-03-31 18:00:46 +04:00
|
|
|
// [17] PCIDE: PCID Support R/W
|
2010-07-22 20:41:59 +04:00
|
|
|
// [16] FSGSBASE: FS/GS BASE access R/W
|
|
|
|
// [15] Reserved, Must be Zero
|
2010-03-26 00:33:07 +03:00
|
|
|
// [14] SMXE: SMX Extensions R/W
|
|
|
|
// [13] VMXE: VMX Extensions R/W
|
2016-04-15 14:35:32 +03:00
|
|
|
// [12] Reserved, Must be Zero
|
|
|
|
// [11] UMIP: User Mode Instruction Prevention R/W
|
2010-03-26 00:33:07 +03:00
|
|
|
// [10] OSXMMEXCPT: Operating System Unmasked Exception Support R/W
|
|
|
|
// [9] OSFXSR: Operating System FXSAVE/FXRSTOR Support R/W
|
|
|
|
// [8] PCE: Performance-Monitoring Counter Enable R/W
|
|
|
|
// [7] PGE: Page-Global Enable R/W
|
|
|
|
// [6] MCE: Machine Check Enable R/W
|
|
|
|
// [5] PAE: Physical-Address Extension R/W
|
|
|
|
// [4] PSE: Page Size Extensions R/W
|
|
|
|
// [3] DE: Debugging Extensions R/W
|
|
|
|
// [2] TSD: Time Stamp Disable R/W
|
|
|
|
// [1] PVI: Protected-Mode Virtual Interrupts R/W
|
|
|
|
// [0] VME: Virtual-8086 Mode Extensions R/W
|
|
|
|
|
2010-05-07 01:46:39 +04:00
|
|
|
/* VME */
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_VME))
|
2010-05-07 01:46:39 +04:00
|
|
|
allowMask |= BX_CR4_VME_MASK | BX_CR4_PVI_MASK;
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_PENTIUM))
|
2011-08-18 00:57:44 +04:00
|
|
|
allowMask |= BX_CR4_TSD_MASK;
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_DEBUG_EXTENSIONS))
|
2010-05-12 18:55:12 +04:00
|
|
|
allowMask |= BX_CR4_DE_MASK;
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_PSE))
|
2010-05-07 01:46:39 +04:00
|
|
|
allowMask |= BX_CR4_PSE_MASK;
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_PAE))
|
2010-05-07 01:46:39 +04:00
|
|
|
allowMask |= BX_CR4_PAE_MASK;
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
|
|
|
|
|
|
|
// NOTE: exception 18 (#MC) never appears in Bochs
|
2010-04-29 23:34:32 +04:00
|
|
|
allowMask |= BX_CR4_MCE_MASK;
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_PGE))
|
2010-05-07 01:46:39 +04:00
|
|
|
allowMask |= BX_CR4_PGE_MASK;
|
|
|
|
|
2010-04-29 23:34:32 +04:00
|
|
|
allowMask |= BX_CR4_PCE_MASK;
|
2010-03-30 22:12:19 +04:00
|
|
|
|
|
|
|
/* OSFXSR */
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_SSE))
|
2010-04-29 23:34:32 +04:00
|
|
|
allowMask |= BX_CR4_OSFXSR_MASK;
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2010-04-29 23:34:32 +04:00
|
|
|
/* OSXMMEXCPT */
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_SSE))
|
2010-04-29 23:34:32 +04:00
|
|
|
allowMask |= BX_CR4_OSXMMEXCPT_MASK;
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
#if BX_SUPPORT_VMX
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_VMX))
|
2011-08-11 22:06:09 +04:00
|
|
|
allowMask |= BX_CR4_VMXE_MASK;
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
|
|
|
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_SMX))
|
2011-07-30 00:22:35 +04:00
|
|
|
allowMask |= BX_CR4_SMXE_MASK;
|
2010-04-29 23:34:32 +04:00
|
|
|
|
|
|
|
#if BX_SUPPORT_X86_64
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_PCID))
|
2010-04-29 23:34:32 +04:00
|
|
|
allowMask |= BX_CR4_PCIDE_MASK;
|
2010-07-22 20:41:59 +04:00
|
|
|
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_FSGSBASE))
|
2010-07-22 20:41:59 +04:00
|
|
|
allowMask |= BX_CR4_FSGSBASE_MASK;
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* OSXSAVE */
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_XSAVE))
|
2010-04-29 23:34:32 +04:00
|
|
|
allowMask |= BX_CR4_OSXSAVE_MASK;
|
2011-05-29 20:28:26 +04:00
|
|
|
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_SMEP))
|
2011-05-29 20:28:26 +04:00
|
|
|
allowMask |= BX_CR4_SMEP_MASK;
|
2012-09-10 19:22:26 +04:00
|
|
|
|
2014-08-31 23:22:41 +04:00
|
|
|
if (is_cpu_extension_supported(BX_ISA_SMAP))
|
2012-09-10 19:22:26 +04:00
|
|
|
allowMask |= BX_CR4_SMAP_MASK;
|
2016-03-16 22:44:24 +03:00
|
|
|
|
|
|
|
if (is_cpu_extension_supported(BX_ISA_PKU))
|
|
|
|
allowMask |= BX_CR4_PKE_MASK;
|
2016-04-15 14:35:32 +03:00
|
|
|
|
|
|
|
if (is_cpu_extension_supported(BX_ISA_UMIP))
|
|
|
|
allowMask |= BX_CR4_UMIP_MASK;
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
|
|
|
|
|
|
|
return allowMask;
|
|
|
|
}
|
|
|
|
|
|
|
|
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::check_CR4(bx_address cr4_val)
|
|
|
|
{
|
2011-08-11 00:31:29 +04:00
|
|
|
// check if trying to set undefined bits
|
|
|
|
if (cr4_val & ~((bx_address) BX_CPU_THIS_PTR cr4_suppmask)) {
|
|
|
|
BX_ERROR(("check_CR4(): write of 0x%08x not supported (allowMask=0x%x)", (Bit32u) cr4_val, BX_CPU_THIS_PTR cr4_suppmask));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-03-26 00:33:07 +03:00
|
|
|
bx_cr4_t temp_cr4;
|
2011-08-11 00:31:29 +04:00
|
|
|
temp_cr4.set32((Bit32u) cr4_val);
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
#if BX_SUPPORT_X86_64
|
|
|
|
if (long_mode()) {
|
|
|
|
if(! temp_cr4.get_PAE()) {
|
|
|
|
BX_ERROR(("check_CR4(): attempt to clear CR4.PAE when EFER.LMA=1"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
2012-11-02 11:46:50 +04:00
|
|
|
else {
|
|
|
|
if (temp_cr4.get_PCIDE()) {
|
2010-04-29 23:34:32 +04:00
|
|
|
BX_ERROR(("check_CR4(): attempt to set CR4.PCIDE when EFER.LMA=0"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#if BX_SUPPORT_VMX
|
|
|
|
if(! temp_cr4.get_VMXE()) {
|
|
|
|
if (BX_CPU_THIS_PTR in_vmx) {
|
|
|
|
BX_ERROR(("check_CR4(): attempt to clear CR4.VMXE in vmx mode"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
if (BX_CPU_THIS_PTR in_smm) {
|
|
|
|
BX_ERROR(("check_CR4(): attempt to set CR4.VMXE in smm mode"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2012-11-02 11:46:50 +04:00
|
|
|
bx_bool BX_CPU_C::SetCR4(bxInstruction_c *i, bx_address val)
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
|
|
|
if (! check_CR4(val)) return 0;
|
|
|
|
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
2011-05-29 20:28:26 +04:00
|
|
|
// Modification of PGE,PAE,PSE,PCIDE,SMEP flushes TLB cache according to docs.
|
2010-04-29 23:34:32 +04:00
|
|
|
if ((val & BX_CR4_FLUSH_TLB_MASK) != (BX_CPU_THIS_PTR cr4.val32 & BX_CR4_FLUSH_TLB_MASK)) {
|
2011-05-29 20:28:26 +04:00
|
|
|
// reload PDPTR if needed
|
2010-04-29 23:34:32 +04:00
|
|
|
if (BX_CPU_THIS_PTR cr0.get_PG() && (val & BX_CR4_PAE_MASK) != 0 && !long_mode()) {
|
2010-04-06 23:26:03 +04:00
|
|
|
if (! CheckPDPTR(BX_CPU_THIS_PTR cr3)) {
|
|
|
|
BX_ERROR(("SetCR4(): PDPTR check failed !"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
2010-04-29 23:34:32 +04:00
|
|
|
#if BX_SUPPORT_X86_64
|
|
|
|
else {
|
|
|
|
// if trying to enable CR4.PCIDE
|
|
|
|
if (! BX_CPU_THIS_PTR cr4.get_PCIDE() && (val & BX_CR4_PCIDE_MASK)) {
|
|
|
|
if (BX_CPU_THIS_PTR cr3 & 0xfff) {
|
|
|
|
BX_ERROR(("SetCR4(): Attempt to enable CR4.PCIDE with non-zero PCID !"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
2010-03-26 00:33:07 +03:00
|
|
|
TLB_flush(); // Flush Global entries also.
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-11-02 11:46:50 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
|
|
if(SVM_CR_WRITE_INTERCEPTED(4)) {
|
|
|
|
if (BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR4_WRITE, BX_SVM_CR_WRITE_MASK | i->src());
|
|
|
|
else
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR4_WRITE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-11-23 17:59:36 +03:00
|
|
|
BX_CPU_THIS_PTR cr4.set32((Bit32u) val);
|
2010-04-06 23:26:03 +04:00
|
|
|
|
2010-12-19 10:06:40 +03:00
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
|
|
handleSseModeChange();
|
2011-03-19 23:09:34 +03:00
|
|
|
#if BX_SUPPORT_AVX
|
|
|
|
handleAvxModeChange();
|
|
|
|
#endif
|
2010-12-19 10:06:40 +03:00
|
|
|
#endif
|
|
|
|
|
2016-03-19 22:48:38 +03:00
|
|
|
// re-calculate protection keys if CR4.PKE was set
|
|
|
|
#if BX_SUPPORT_PKEYS
|
2016-03-20 00:15:56 +03:00
|
|
|
set_PKRU(BX_CPU_THIS_PTR pkru);
|
2016-03-19 22:48:38 +03:00
|
|
|
#endif
|
|
|
|
|
2010-03-26 00:33:07 +03:00
|
|
|
return 1;
|
|
|
|
}
|
2011-08-16 20:49:04 +04:00
|
|
|
#endif // BX_CPU_LEVEL >= 5
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetCR3(bx_address val)
|
|
|
|
{
|
|
|
|
#if BX_SUPPORT_X86_64
|
2010-04-04 13:04:12 +04:00
|
|
|
if (long_mode()) {
|
|
|
|
if (! IsValidPhyAddr(val)) {
|
|
|
|
BX_ERROR(("SetCR3(): Attempt to write to reserved bits of CR3 !"));
|
|
|
|
return 0;
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
BX_CPU_THIS_PTR cr3 = val;
|
|
|
|
|
|
|
|
// flush TLB even if value does not change
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
|
|
if (BX_CPU_THIS_PTR cr4.get_PGE())
|
|
|
|
TLB_flushNonGlobal(); // Don't flush Global entries.
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
TLB_flush(); // Flush Global entries also.
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2011-08-31 01:32:40 +04:00
|
|
|
#if BX_CPU_LEVEL >= 5
|
2011-07-30 00:22:35 +04:00
|
|
|
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetEFER(bx_address val_64)
|
|
|
|
{
|
2011-12-31 16:58:20 +04:00
|
|
|
Bit32u val32 = (Bit32u) val_64;
|
|
|
|
|
2011-08-04 23:02:49 +04:00
|
|
|
if (val_64 & ~((Bit64u) BX_CPU_THIS_PTR efer_suppmask)) {
|
2011-12-31 16:58:20 +04:00
|
|
|
BX_ERROR(("SetEFER(0x%08x): attempt to set reserved bits of EFER MSR !", val32));
|
2011-07-30 00:22:35 +04:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-08-11 02:04:33 +04:00
|
|
|
#if BX_SUPPORT_X86_64
|
2011-07-30 00:22:35 +04:00
|
|
|
/* #GP(0) if changing EFER.LME when cr0.pg = 1 */
|
|
|
|
if ((BX_CPU_THIS_PTR efer.get_LME() != ((val32 >> 8) & 1)) &&
|
|
|
|
BX_CPU_THIS_PTR cr0.get_PG())
|
|
|
|
{
|
|
|
|
BX_ERROR(("SetEFER: attempt to change LME when CR0.PG=1"));
|
|
|
|
return 0;
|
|
|
|
}
|
2011-08-11 02:04:33 +04:00
|
|
|
#endif
|
2011-07-30 00:22:35 +04:00
|
|
|
|
2011-08-04 23:02:49 +04:00
|
|
|
BX_CPU_THIS_PTR efer.set32((val32 & BX_CPU_THIS_PTR efer_suppmask & ~BX_EFER_LMA_MASK)
|
2011-07-30 00:22:35 +04:00
|
|
|
| (BX_CPU_THIS_PTR efer.get32() & BX_EFER_LMA_MASK)); // keep LMA untouched
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-09-03 19:22:56 +04:00
|
|
|
#if BX_CPU_LEVEL >= 6
|
2012-07-01 18:46:27 +04:00
|
|
|
|
2011-09-03 19:22:56 +04:00
|
|
|
void BX_CPU_C::WriteCR8(bxInstruction_c *i, bx_address val)
|
|
|
|
{
|
2011-12-27 23:42:11 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
2012-11-02 11:46:50 +04:00
|
|
|
if(SVM_CR_WRITE_INTERCEPTED(8)) {
|
|
|
|
if (BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST))
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR8_WRITE, BX_SVM_CR_WRITE_MASK | i->src());
|
|
|
|
else
|
|
|
|
Svm_Vmexit(SVM_VMEXIT_CR8_WRITE);
|
|
|
|
}
|
2011-12-27 23:42:11 +04:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-09-03 19:22:56 +04:00
|
|
|
#if BX_SUPPORT_VMX
|
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest)
|
|
|
|
VMexit_CR8_Write(i);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
// CR8 is aliased to APIC->TASK PRIORITY register
|
|
|
|
// APIC.TPR[7:4] = CR8[3:0]
|
|
|
|
// APIC.TPR[3:0] = 0
|
|
|
|
// Reads of CR8 return zero extended APIC.TPR[7:4]
|
|
|
|
// Write to CR8 update APIC.TPR[7:4]
|
|
|
|
if (val & BX_CONST64(0xfffffffffffffff0)) {
|
|
|
|
BX_ERROR(("WriteCR8: Attempt to set reserved bits of CR8"));
|
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
2011-12-27 23:42:11 +04:00
|
|
|
unsigned tpr = (val & 0xf) << 4;
|
|
|
|
|
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
|
|
SVM_V_TPR = tpr;
|
2012-10-04 00:24:29 +04:00
|
|
|
handleInterruptMaskChange();
|
2011-12-27 23:42:11 +04:00
|
|
|
if (SVM_V_INTR_MASKING) return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-09-26 22:08:31 +04:00
|
|
|
#if BX_SUPPORT_VMX && BX_SUPPORT_X86_64
|
2011-09-03 19:22:56 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest && VMEXIT(VMX_VM_EXEC_CTRL2_TPR_SHADOW)) {
|
2012-10-26 22:43:53 +04:00
|
|
|
VMX_Write_Virtual_APIC(BX_LAPIC_TPR, tpr);
|
|
|
|
VMX_TPR_Virtualization();
|
2011-12-27 23:42:11 +04:00
|
|
|
return;
|
2011-09-03 19:22:56 +04:00
|
|
|
}
|
|
|
|
#endif
|
2011-12-27 23:42:11 +04:00
|
|
|
|
|
|
|
BX_CPU_THIS_PTR lapic.set_tpr(tpr);
|
2011-09-03 19:22:56 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
Bit32u BX_CPU_C::ReadCR8(bxInstruction_c *i)
|
|
|
|
{
|
2011-12-27 23:42:11 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
2012-05-03 20:12:58 +04:00
|
|
|
if (SVM_CR_READ_INTERCEPTED(8)) Svm_Vmexit(SVM_VMEXIT_CR8_READ);
|
2011-12-27 23:42:11 +04:00
|
|
|
|
|
|
|
if (SVM_V_INTR_MASKING) return SVM_V_TPR;
|
|
|
|
}
|
|
|
|
#endif
|
2011-09-03 19:22:56 +04:00
|
|
|
|
2011-09-26 22:08:31 +04:00
|
|
|
#if BX_SUPPORT_VMX && BX_SUPPORT_X86_64
|
2011-09-03 19:22:56 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest)
|
|
|
|
VMexit_CR8_Read(i);
|
|
|
|
|
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest && VMEXIT(VMX_VM_EXEC_CTRL2_TPR_SHADOW)) {
|
2012-09-10 19:22:26 +04:00
|
|
|
Bit32u tpr = (VMX_Read_Virtual_APIC(BX_LAPIC_TPR) >> 4) & 0xf;
|
2011-12-27 23:42:11 +04:00
|
|
|
return tpr;
|
2011-09-03 19:22:56 +04:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-12-27 23:42:11 +04:00
|
|
|
// CR8 is aliased to APIC->TASK PRIORITY register
|
|
|
|
// APIC.TPR[7:4] = CR8[3:0]
|
|
|
|
// APIC.TPR[3:0] = 0
|
|
|
|
// Reads of CR8 return zero extended APIC.TPR[7:4]
|
|
|
|
// Write to CR8 update APIC.TPR[7:4]
|
2012-06-28 22:27:26 +04:00
|
|
|
return BX_CPU_THIS_PTR get_cr8();
|
2011-09-03 19:22:56 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2018-02-16 10:57:32 +03:00
|
|
|
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CLTS(bxInstruction_c *i)
|
2010-12-23 00:16:02 +03:00
|
|
|
{
|
2011-08-24 01:25:34 +04:00
|
|
|
// CPL is always 0 in real mode
|
|
|
|
if (/* !real_mode() && */ CPL!=0) {
|
2013-12-03 00:06:59 +04:00
|
|
|
BX_ERROR(("%s: priveledge check failed, generate #GP(0)", i->getIaOpcodeNameShort()));
|
2010-12-23 00:16:02 +03:00
|
|
|
exception(BX_GP_EXCEPTION, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
#if BX_SUPPORT_VMX
|
2011-08-10 00:50:51 +04:00
|
|
|
if (BX_CPU_THIS_PTR in_vmx_guest) {
|
2012-07-26 20:03:26 +04:00
|
|
|
if(VMexit_CLTS()) {
|
2011-08-10 00:50:51 +04:00
|
|
|
BX_NEXT_TRACE(i);
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
}
|
2010-12-23 00:16:02 +03:00
|
|
|
#endif
|
|
|
|
|
2011-12-27 00:51:57 +04:00
|
|
|
#if BX_SUPPORT_SVM
|
|
|
|
if (BX_CPU_THIS_PTR in_svm_guest) {
|
|
|
|
if(SVM_CR_WRITE_INTERCEPTED(0)) Svm_Vmexit(SVM_VMEXIT_CR0_WRITE);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-12-23 00:16:02 +03:00
|
|
|
BX_CPU_THIS_PTR cr0.set_TS(0);
|
|
|
|
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
|
|
handleSseModeChange();
|
2011-03-19 23:09:34 +03:00
|
|
|
#if BX_SUPPORT_AVX
|
|
|
|
handleAvxModeChange();
|
|
|
|
#endif
|
2010-12-23 00:16:02 +03:00
|
|
|
#endif
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_TRACE(i);
|
2010-12-23 00:16:02 +03:00
|
|
|
}
|
|
|
|
|
2010-03-26 00:33:07 +03:00
|
|
|
#if BX_X86_DEBUGGER
|
2011-11-29 01:16:40 +04:00
|
|
|
|
2011-04-09 09:12:28 +04:00
|
|
|
bx_bool BX_CPU_C::hwbreakpoint_check(bx_address laddr, unsigned opa, unsigned opb)
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
|
|
|
laddr = LPFOf(laddr);
|
|
|
|
|
2011-04-09 09:12:28 +04:00
|
|
|
Bit32u dr_op[4];
|
|
|
|
|
|
|
|
dr_op[0] = BX_CPU_THIS_PTR dr7.get_R_W0();
|
|
|
|
dr_op[1] = BX_CPU_THIS_PTR dr7.get_R_W1();
|
|
|
|
dr_op[2] = BX_CPU_THIS_PTR dr7.get_R_W2();
|
|
|
|
dr_op[3] = BX_CPU_THIS_PTR dr7.get_R_W3();
|
|
|
|
|
|
|
|
for (int n=0;n<4;n++) {
|
|
|
|
if ((dr_op[n] == opa || dr_op[n] == opb) && laddr == LPFOf(BX_CPU_THIS_PTR dr[n])) {
|
2010-03-26 00:33:07 +03:00
|
|
|
return 1;
|
2011-04-09 09:12:28 +04:00
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-03-24 22:06:58 +03:00
|
|
|
Bit32u BX_CPU_C::code_breakpoint_match(bx_address laddr)
|
2011-02-26 23:43:11 +03:00
|
|
|
{
|
2011-03-24 22:06:58 +03:00
|
|
|
if (BX_CPU_THIS_PTR get_RF() || BX_CPU_THIS_PTR in_repeat)
|
|
|
|
return 0;
|
|
|
|
|
2011-03-15 23:31:49 +03:00
|
|
|
if (BX_CPU_THIS_PTR dr7.get_bp_enabled()) {
|
2011-02-26 23:50:26 +03:00
|
|
|
Bit32u dr6_bits = hwdebug_compare(laddr, 1, BX_HWDebugInstruction, BX_HWDebugInstruction);
|
2012-07-11 19:07:54 +04:00
|
|
|
return dr6_bits;
|
2011-02-26 23:43:11 +03:00
|
|
|
}
|
2011-03-24 22:06:58 +03:00
|
|
|
|
|
|
|
return 0;
|
2011-02-26 23:43:11 +03:00
|
|
|
}
|
|
|
|
|
2010-03-26 00:33:07 +03:00
|
|
|
void BX_CPU_C::hwbreakpoint_match(bx_address laddr, unsigned len, unsigned rw)
|
|
|
|
{
|
2011-03-15 23:31:49 +03:00
|
|
|
if (BX_CPU_THIS_PTR dr7.get_bp_enabled()) {
|
2010-03-26 00:33:07 +03:00
|
|
|
// Only compare debug registers if any breakpoints are enabled
|
|
|
|
unsigned opa, opb, write = rw & 1;
|
|
|
|
opa = BX_HWDebugMemRW; // Read or Write always compares vs 11b
|
|
|
|
if (! write) // only compares vs 11b
|
|
|
|
opb = opa;
|
|
|
|
else // BX_WRITE or BX_RW; also compare vs 01b
|
|
|
|
opb = BX_HWDebugMemW;
|
|
|
|
Bit32u dr6_bits = hwdebug_compare(laddr, len, opa, opb);
|
|
|
|
if (dr6_bits) {
|
|
|
|
BX_CPU_THIS_PTR debug_trap |= dr6_bits;
|
2012-07-11 19:07:54 +04:00
|
|
|
if (BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_HIT) {
|
|
|
|
BX_ERROR(("#DB: Code/Data breakpoint hit - report debug trap on next instruction"));
|
|
|
|
BX_CPU_THIS_PTR async_event = 1;
|
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
Bit32u BX_CPU_C::hwdebug_compare(bx_address laddr_0, unsigned size,
|
|
|
|
unsigned opa, unsigned opb)
|
|
|
|
{
|
2011-03-15 23:20:15 +03:00
|
|
|
Bit32u dr7 = BX_CPU_THIS_PTR dr7.get32();
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
static bx_address alignment_mask[4] =
|
|
|
|
// 00b=1 01b=2 10b=undef(8) 11b=4
|
|
|
|
{ 0x0, 0x1, 0x7, 0x3 };
|
|
|
|
|
|
|
|
bx_address laddr_n = laddr_0 + (size - 1);
|
|
|
|
Bit32u dr_op[4], dr_len[4];
|
2012-07-11 19:07:54 +04:00
|
|
|
|
|
|
|
// If *any* enabled breakpoints matched, then we need to
|
|
|
|
// set status bits for *all* breakpoints, even disabled ones,
|
|
|
|
// as long as they meet the other breakpoint criteria.
|
|
|
|
// dr6_mask is the return value. These bits represent the bits
|
|
|
|
// to be OR'd into DR6 as a result of the debug event.
|
|
|
|
Bit32u dr6_mask = 0;
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2011-03-15 23:20:15 +03:00
|
|
|
dr_len[0] = BX_CPU_THIS_PTR dr7.get_LEN0();
|
|
|
|
dr_len[1] = BX_CPU_THIS_PTR dr7.get_LEN1();
|
|
|
|
dr_len[2] = BX_CPU_THIS_PTR dr7.get_LEN2();
|
|
|
|
dr_len[3] = BX_CPU_THIS_PTR dr7.get_LEN3();
|
2010-03-26 00:33:07 +03:00
|
|
|
|
2011-03-15 23:20:15 +03:00
|
|
|
dr_op[0] = BX_CPU_THIS_PTR dr7.get_R_W0();
|
|
|
|
dr_op[1] = BX_CPU_THIS_PTR dr7.get_R_W1();
|
|
|
|
dr_op[2] = BX_CPU_THIS_PTR dr7.get_R_W2();
|
|
|
|
dr_op[3] = BX_CPU_THIS_PTR dr7.get_R_W3();
|
2010-03-26 00:33:07 +03:00
|
|
|
|
|
|
|
for (unsigned n=0;n<4;n++) {
|
|
|
|
bx_address dr_start = BX_CPU_THIS_PTR dr[n] & ~alignment_mask[dr_len[n]];
|
|
|
|
bx_address dr_end = dr_start + alignment_mask[dr_len[n]];
|
|
|
|
|
|
|
|
// See if this instruction address matches any breakpoints
|
2012-07-11 19:07:54 +04:00
|
|
|
if ((dr_op[n]==opa || dr_op[n]==opb) &&
|
|
|
|
(laddr_0 <= dr_end) &&
|
|
|
|
(laddr_n >= dr_start)) {
|
|
|
|
dr6_mask |= (1<<n);
|
|
|
|
// tell if breakpoint was enabled
|
|
|
|
if (dr7 & (3 << n*2)) {
|
|
|
|
dr6_mask |= BX_DEBUG_TRAP_HIT;
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return dr6_mask;
|
|
|
|
}
|
|
|
|
|
2011-11-29 01:16:40 +04:00
|
|
|
#if BX_CPU_LEVEL >= 5
|
2010-03-26 00:33:07 +03:00
|
|
|
void BX_CPU_C::iobreakpoint_match(unsigned port, unsigned len)
|
|
|
|
{
|
|
|
|
// Only compare debug registers if any breakpoints are enabled
|
2011-03-15 23:31:49 +03:00
|
|
|
if (BX_CPU_THIS_PTR cr4.get_DE() && BX_CPU_THIS_PTR dr7.get_bp_enabled())
|
2010-03-26 00:33:07 +03:00
|
|
|
{
|
|
|
|
Bit32u dr6_bits = hwdebug_compare(port, len, BX_HWDebugIO, BX_HWDebugIO);
|
|
|
|
if (dr6_bits) {
|
|
|
|
BX_CPU_THIS_PTR debug_trap |= dr6_bits;
|
2012-07-11 19:07:54 +04:00
|
|
|
if (BX_CPU_THIS_PTR debug_trap & BX_DEBUG_TRAP_HIT) {
|
|
|
|
BX_ERROR(("#DB: I/O breakpoint hit - report debug trap on next instruction"));
|
|
|
|
BX_CPU_THIS_PTR async_event = 1;
|
|
|
|
}
|
2010-03-26 00:33:07 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
2011-11-29 01:16:40 +04:00
|
|
|
|
|
|
|
#endif
|
2019-12-06 12:23:28 +03:00
|
|
|
|
|
|
|
#if BX_CPU_LEVEL >= 6
|
|
|
|
Bit32u BX_CPU_C::get_xcr0_allow_mask()
|
|
|
|
{
|
|
|
|
Bit32u allowMask = 0x3;
|
|
|
|
#if BX_SUPPORT_AVX
|
|
|
|
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_AVX))
|
|
|
|
allowMask |= BX_XCR0_YMM_MASK;
|
|
|
|
#if BX_SUPPORT_EVEX
|
|
|
|
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_AVX512))
|
|
|
|
allowMask |= BX_XCR0_OPMASK_MASK | BX_XCR0_ZMM_HI256_MASK | BX_XCR0_HI_ZMM_MASK;
|
|
|
|
#endif
|
|
|
|
#endif // BX_SUPPORT_AVX
|
|
|
|
#if BX_SUPPORT_PKEYS
|
|
|
|
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_PKU))
|
|
|
|
allowMask |= BX_XCR0_PKRU_MASK;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return allowMask;
|
|
|
|
}
|
|
|
|
#endif
|