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Bochs/bochs/cpu/logical32.cc

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- add RCS Id to header of every file. This makes it easier to know what's going on when someone sends in a modified file.
2001-10-03 17:10:38 +04:00
/////////////////////////////////////////////////////////////////////////
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
// $Id: logical32.cc,v 1.6 2002-09-06 21:54:58 kevinlawton Exp $
- add RCS Id to header of every file. This makes it easier to know what's going on when someone sends in a modified file.
2001-10-03 17:10:38 +04:00
/////////////////////////////////////////////////////////////////////////
//
- update copyright dates to 2001 for all mandrake headers - for bochs files with other header, replaced with current mandrake header
2001-04-10 06:20:02 +04:00
// Copyright (C) 2001 MandrakeSoft S.A.
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
//
// MandrakeSoft S.A.
// 43, rue d'Aboukir
// 75002 Paris - France
// http://www.linux-mandrake.com/
// http://www.mandrakesoft.com/
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- parts of the SMP merge apparantly broke the debugger and this revision tries to fix it. The shortcuts to register names such as AX and DL are #defines in cpu/cpu.h, and they are defined in terms of BX_CPU_THIS_PTR. When BX_USE_CPU_SMF=1, this works fine. (This is what bochs used for a long time, and nobody used the SMF=0 mode at all.) To make SMP bochs work, I had to get SMF=0 mode working for the CPU so that there could be an array of cpus. When SMF=0 for the CPU, BX_CPU_THIS_PTR is defined to be "this->" which only works within methods of BX_CPU_C. Code outside of BX_CPU_C must reference BX_CPU(num) instead. - to try to enforce the correct use of AL/AX/DL/etc. shortcuts, they are now only #defined when "NEED_CPU_REG_SHORTCUTS" is #defined. This is only done in the cpu/*.cc code.
2001-05-24 22:46:34 +04:00
#define NEED_CPU_REG_SHORTCUTS 1
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
#include "bochs.h"
merge in BRANCH-io-cleanup. To see the commit logs for this use either cvsweb or cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files. In general this provides a generic interface for logging. logfunctions:: is a class that is inherited by some classes, and also . allocated as a standalone global called 'genlog'. All logging uses . one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this . class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros . respectively. . . An example usage: . BX_INFO(("Hello, World!\n")); iofunctions:: is a class that is allocated once by default, and assigned as the iofunction of each logfunctions instance. It is this class that maintains the file descriptor and other output related code, at this point using vfprintf(). At some future point, someone may choose to write a gui 'console' for bochs to which messages would be redirected simply by assigning a different iofunction class to the various logfunctions objects. More cleanup is coming, but this works for now. If you want to see alot of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1. Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
#define LOG_THIS BX_CPU_THIS_PTR
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
void
BX_CPU_C::XOR_EdGd(BxInstruction_t *i)
{
/* for 32 bit operand size mode */
Bit32u op2_32, op1_32, result_32;
/* op2_32 is a register, op2_addr is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn);
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 ^ op2_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_dword(result_32);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
}
void
BX_CPU_C::XOR_GdEd(BxInstruction_t *i)
{
/* for 32 bit operand size mode */
Bit32u op1_32, op2_32, result_32;
op1_32 = BX_READ_32BIT_REG(i->nnn);
/* op2_32 is a register or memory reference */
if (i->mod == 0xc0) {
op2_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg, i->rm_addr, &op2_32);
}
result_32 = op1_32 ^ op2_32;
/* now write result back to destination */
BX_WRITE_32BIT_REG(i->nnn, result_32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
}
void
BX_CPU_C::XOR_EAXId(BxInstruction_t *i)
{
/* for 32 bit operand size mode */
Bit32u op1_32, op2_32, sum_32;
op1_32 = EAX;
op2_32 = i->Id;
sum_32 = op1_32 ^ op2_32;
/* now write sum back to destination */
EAX = sum_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_XOR32);
}
void
BX_CPU_C::XOR_EdId(BxInstruction_t *i)
{
Bit32u op2_32, op1_32, result_32;
op2_32 = i->Id;
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 ^ op2_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_dword(result_32);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
}
void
BX_CPU_C::OR_EdId(BxInstruction_t *i)
{
Bit32u op2_32, op1_32, result_32;
op2_32 = i->Id;
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 | op2_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_dword(result_32);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
}
void
BX_CPU_C::NOT_Ed(BxInstruction_t *i)
{
Bit32u op1_32, result_32;
/* op1 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = ~op1_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_dword(result_32);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
}
void
BX_CPU_C::OR_EdGd(BxInstruction_t *i)
{
Bit32u op2_32, op1_32, result_32;
/* op2_32 is a register, op2_addr is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn);
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 | op2_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_dword(result_32);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
}
void
BX_CPU_C::OR_GdEd(BxInstruction_t *i)
{
Bit32u op1_32, op2_32, result_32;
op1_32 = BX_READ_32BIT_REG(i->nnn);
/* op2_32 is a register or memory reference */
if (i->mod == 0xc0) {
op2_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg, i->rm_addr, &op2_32);
}
result_32 = op1_32 | op2_32;
/* now write result back to destination */
BX_WRITE_32BIT_REG(i->nnn, result_32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
}
void
BX_CPU_C::OR_EAXId(BxInstruction_t *i)
{
Bit32u op1_32, op2_32, sum_32;
op1_32 = EAX;
op2_32 = i->Id;
sum_32 = op1_32 | op2_32;
/* now write sum back to destination */
EAX = sum_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_OR32);
}
void
BX_CPU_C::AND_EdGd(BxInstruction_t *i)
{
Bit32u op2_32, op1_32, result_32;
/* op2_32 is a register, op2_addr is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn);
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 & op2_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_dword(result_32);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
}
void
BX_CPU_C::AND_GdEd(BxInstruction_t *i)
{
Bit32u op1_32, op2_32, result_32;
op1_32 = BX_READ_32BIT_REG(i->nnn);
/* op2_32 is a register or memory reference */
if (i->mod == 0xc0) {
op2_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg, i->rm_addr, &op2_32);
}
result_32 = op1_32 & op2_32;
/* now write result back to destination */
BX_WRITE_32BIT_REG(i->nnn, result_32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
}
void
BX_CPU_C::AND_EAXId(BxInstruction_t *i)
{
Bit32u op1_32, op2_32, sum_32;
op1_32 = EAX;
op2_32 = i->Id;
sum_32 = op1_32 & op2_32;
/* now write sum back to destination */
EAX = sum_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_AND32);
}
void
BX_CPU_C::AND_EdId(BxInstruction_t *i)
{
Bit32u op2_32, op1_32, result_32;
op2_32 = i->Id;
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 & op2_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
I extended the guest-to-host TLB acceleration across the Read-Modify-Write instructions. The first read phase stores the host pointer in the "pages" field if a direct use pointer is available. The Write phase first checks if a pointer was issued and uses it for a direct write if available. I chose the "pages" field since it needs to be checked by the write_RMW_virtual variants anyways and thus needs to be cached anyways. Mostly the mods where to access.cc, but I did also macro-ize the calls to write_RMW_virtual...() in files which use it and cpu.h. Right now, the macro is just a straight pass-through. I tried expanding it to a quick initial check for the pointer availability to do the write in-place, with a function call as a fall-back. That didn't seemed to matter at all. Booting is not helped by this really. The upper bound of the gain is 5 or 6%, and that's only if you have a loop that looks like: label: add [eax], ebx ;; mega read-modify-write instruction jmp label ;; intensive loop.
2002-09-07 01:54:58 +04:00
Write_RMW_virtual_dword(result_32);
- entered original Bochs snapshot bochs-2000_0325a.tar.gz from ftp.bochs.com
2001-04-10 05:04:59 +04:00
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
}
void
BX_CPU_C::TEST_EdGd(BxInstruction_t *i)
{
Bit32u op2_32, op1_32, result_32;
/* op2_32 is a register, op2_addr is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn);
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 & op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
}
void
BX_CPU_C::TEST_EAXId(BxInstruction_t *i)
{
Bit32u op2_32, op1_32, result_32;
/* op1 is EAX register */
op1_32 = EAX;
/* op2 is imm32 */
op2_32 = i->Id;
result_32 = op1_32 & op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
}
void
BX_CPU_C::TEST_EdId(BxInstruction_t *i)
{
Bit32u op2_32, op1_32, result_32;
/* op2 is imm32 */
op2_32 = i->Id;
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 & op2_32;
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_TEST32);
}
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