2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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2003-07-16 21:56:25 +04:00
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// $Id: vga.h,v 1.34 2003-07-16 17:56:25 vruppert Exp $
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2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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//
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2002-02-04 23:31:35 +03:00
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// Copyright (C) 2002 MandrakeSoft S.A.
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2001-04-10 05:04:59 +04:00
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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2002-03-10 07:51:24 +03:00
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#if BX_SUPPORT_VBE
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2002-03-13 21:33:00 +03:00
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#define VBE_DISPI_TOTAL_VIDEO_MEMORY_MB 4
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2003-06-30 22:53:12 +04:00
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2002-03-10 07:51:24 +03:00
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#define VBE_DISPI_BANK_ADDRESS 0xA0000
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#define VBE_DISPI_BANK_SIZE_KB 64
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2003-06-30 22:53:12 +04:00
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2002-03-10 07:51:24 +03:00
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#define VBE_DISPI_MAX_XRES 1024
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#define VBE_DISPI_MAX_YRES 768
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2003-06-30 22:53:12 +04:00
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2002-03-10 07:51:24 +03:00
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#define VBE_DISPI_IOPORT_INDEX 0xFF80
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#define VBE_DISPI_IOPORT_DATA 0xFF81
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2003-06-30 22:53:12 +04:00
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2002-03-10 07:51:24 +03:00
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#define VBE_DISPI_INDEX_ID 0x0
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#define VBE_DISPI_INDEX_XRES 0x1
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#define VBE_DISPI_INDEX_YRES 0x2
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#define VBE_DISPI_INDEX_BPP 0x3
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#define VBE_DISPI_INDEX_ENABLE 0x4
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#define VBE_DISPI_INDEX_BANK 0x5
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2002-04-29 17:06:06 +04:00
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#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
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#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
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#define VBE_DISPI_INDEX_X_OFFSET 0x8
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#define VBE_DISPI_INDEX_Y_OFFSET 0x9
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2003-06-30 22:53:12 +04:00
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2002-03-10 07:51:24 +03:00
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#define VBE_DISPI_ID0 0xB0C0
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2002-04-29 17:06:06 +04:00
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#define VBE_DISPI_ID1 0xB0C1
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2003-06-30 22:53:12 +04:00
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#define VBE_DISPI_ID2 0xB0C2
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#define VBE_DISPI_BPP_4 0x04
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#define VBE_DISPI_BPP_8 0x08
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2003-07-10 00:15:38 +04:00
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#define VBE_DISPI_BPP_15 0x0F
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2003-06-30 22:53:12 +04:00
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#define VBE_DISPI_BPP_16 0x10
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#define VBE_DISPI_BPP_24 0x18
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#define VBE_DISPI_BPP_32 0x20
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2001-04-10 05:04:59 +04:00
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2002-03-10 07:51:24 +03:00
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#define VBE_DISPI_DISABLED 0x00
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#define VBE_DISPI_ENABLED 0x01
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2003-07-01 20:07:59 +04:00
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#define VBE_DISPI_NOCLEARMEM 0x80
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2003-07-16 21:56:25 +04:00
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#define VBE_DISPI_LFB_ENABLED 0x40
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2003-07-01 20:07:59 +04:00
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2002-04-03 20:48:15 +04:00
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#define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
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2003-06-30 22:53:12 +04:00
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2002-09-22 15:31:48 +04:00
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#define VBE_DISPI_TOTAL_VIDEO_MEMORY_KB (VBE_DISPI_TOTAL_VIDEO_MEMORY_MB * 1024)
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#define VBE_DISPI_TOTAL_VIDEO_MEMORY_BYTES (VBE_DISPI_TOTAL_VIDEO_MEMORY_KB * 1024)
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2002-03-10 07:51:24 +03:00
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#define BX_MAX_XRES VBE_DISPI_MAX_XRES
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#define BX_MAX_YRES VBE_DISPI_MAX_YRES
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#else
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2003-06-05 22:18:14 +04:00
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#define BX_MAX_XRES 800
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#define BX_MAX_YRES 600
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2002-03-10 07:51:24 +03:00
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#endif //BX_SUPPORT_VBE
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2001-04-10 05:04:59 +04:00
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2002-09-19 05:32:38 +04:00
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#define X_TILESIZE 16
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#define Y_TILESIZE 24
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2002-03-10 07:51:24 +03:00
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#define BX_NUM_X_TILES (BX_MAX_XRES /X_TILESIZE)
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#define BX_NUM_Y_TILES (BX_MAX_YRES /Y_TILESIZE)
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2001-04-10 05:04:59 +04:00
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// Support varying number of rows of text. This used to
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// be limited to only 25 lines.
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2003-06-05 22:18:14 +04:00
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#define BX_MAX_TEXT_LINES 100
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2001-04-10 05:04:59 +04:00
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#if BX_USE_VGA_SMF
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# define BX_VGA_SMF static
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2002-10-25 01:07:56 +04:00
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# define BX_VGA_THIS theVga->
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2001-04-10 05:04:59 +04:00
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#else
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# define BX_VGA_SMF
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# define BX_VGA_THIS this->
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#endif
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2002-03-10 07:51:24 +03:00
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2002-10-25 01:07:56 +04:00
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class bx_vga_c : public bx_vga_stub_c {
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2001-04-10 05:04:59 +04:00
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public:
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bx_vga_c(void);
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~bx_vga_c(void);
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2002-10-25 01:07:56 +04:00
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virtual void init(void);
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virtual void reset(unsigned type);
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virtual Bit8u mem_read(Bit32u addr);
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2001-04-10 05:04:59 +04:00
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// Note: either leave value of type Bit8u, or mask it when
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// used to 8 bits, in memory.cc
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2002-10-25 01:07:56 +04:00
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virtual void mem_write(Bit32u addr, Bit8u value);
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virtual void trigger_timer(void *this_ptr);
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2002-03-10 07:51:24 +03:00
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2003-03-03 02:59:12 +03:00
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#if BX_SUPPORT_VBE
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BX_VGA_SMF Bit8u vbe_mem_read(Bit32u addr) BX_CPP_AttrRegparmN(1);
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BX_VGA_SMF void vbe_mem_write(Bit32u addr, Bit8u value) BX_CPP_AttrRegparmN(2);
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2002-03-10 07:51:24 +03:00
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#endif
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2003-03-03 02:59:12 +03:00
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2002-10-25 01:07:56 +04:00
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virtual void redraw_area(unsigned x0, unsigned y0,
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unsigned width, unsigned height);
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virtual void set_update_interval (unsigned interval);
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virtual void get_text_snapshot(Bit8u **text_snapshot, unsigned *txHeight,
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unsigned *txWidth);
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2002-12-28 14:49:17 +03:00
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virtual Bit8u get_actl_palette_idx(Bit8u index);
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2001-04-10 05:04:59 +04:00
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private:
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static Bit32u read_handler(void *this_ptr, Bit32u address, unsigned io_len);
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static void write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len);
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static void write_handler_no_log(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len);
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2002-03-10 07:51:24 +03:00
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#if BX_SUPPORT_VBE
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static Bit32u vbe_read_handler(void *this_ptr, Bit32u address, unsigned io_len);
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static void vbe_write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len);
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#endif
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2001-04-10 05:04:59 +04:00
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struct {
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struct {
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2002-10-25 15:44:41 +04:00
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bx_bool color_emulation; // 1=color emulation, base address = 3Dx
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2001-04-10 05:04:59 +04:00
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// 0=mono emulation, base address = 3Bx
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2002-10-25 15:44:41 +04:00
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bx_bool enable_ram; // enable CPU access to video memory if set
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2001-04-10 05:04:59 +04:00
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Bit8u clock_select; // 0=25Mhz 1=28Mhz
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2002-10-25 15:44:41 +04:00
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bx_bool select_high_bank; // when in odd/even modes, select
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2001-04-10 05:04:59 +04:00
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// high 64k bank if set
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2002-10-25 15:44:41 +04:00
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bx_bool horiz_sync_pol; // bit6: negative if set
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bx_bool vert_sync_pol; // bit7: negative if set
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2001-04-10 05:04:59 +04:00
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// bit7,bit6 represent number of lines on display:
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// 0 = reserved
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// 1 = 400 lines
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// 2 = 350 lines
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// 3 - 480 lines
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} misc_output;
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struct {
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Bit8u address;
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Bit8u reg[0x19];
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} CRTC;
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struct {
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2002-10-25 15:44:41 +04:00
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bx_bool flip_flop; /* 0 = address, 1 = data-write */
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2001-04-10 05:04:59 +04:00
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unsigned address; /* register number */
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2002-10-25 15:44:41 +04:00
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bx_bool video_enabled;
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2001-04-10 05:04:59 +04:00
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Bit8u palette_reg[16];
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Bit8u overscan_color;
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Bit8u color_plane_enable;
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Bit8u horiz_pel_panning;
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Bit8u color_select;
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struct {
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2002-10-25 15:44:41 +04:00
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bx_bool graphics_alpha;
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bx_bool display_type;
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bx_bool enable_line_graphics;
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bx_bool blink_intensity;
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bx_bool pixel_panning_compat;
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bx_bool pixel_clock_select;
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bx_bool internal_palette_size;
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2001-04-10 05:04:59 +04:00
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} mode_ctrl;
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} attribute_ctrl;
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struct {
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Bit8u write_data_register;
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Bit8u write_data_cycle; /* 0, 1, 2 */
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Bit8u read_data_register;
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Bit8u read_data_cycle; /* 0, 1, 2 */
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2003-01-11 14:18:04 +03:00
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Bit8u dac_state;
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2001-04-10 05:04:59 +04:00
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struct {
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Bit8u red;
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Bit8u green;
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Bit8u blue;
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} data[256];
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Bit8u mask;
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} pel;
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struct {
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Bit8u index;
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Bit8u set_reset;
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Bit8u enable_set_reset;
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Bit8u color_compare;
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Bit8u data_rotate;
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Bit8u raster_op;
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Bit8u read_map_select;
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Bit8u write_mode;
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2002-10-25 15:44:41 +04:00
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bx_bool read_mode;
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bx_bool odd_even;
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bx_bool chain_odd_even;
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2001-04-10 05:04:59 +04:00
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Bit8u shift_reg;
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2002-10-25 15:44:41 +04:00
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bx_bool graphics_alpha;
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2001-04-10 05:04:59 +04:00
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Bit8u memory_mapping; /* 0 = use A0000-BFFFF
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* 1 = use A0000-AFFFF EGA/VGA graphics modes
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* 2 = use B0000-B7FFF Monochrome modes
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* 3 = use B8000-BFFFF CGA modes
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*/
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Bit8u color_dont_care;
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Bit8u bitmask;
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Bit8u latch[4];
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} graphics_ctrl;
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struct {
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Bit8u index;
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Bit8u map_mask;
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2002-10-25 15:44:41 +04:00
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bx_bool map_mask_bit[4];
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bx_bool reset1;
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bx_bool reset2;
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2001-04-10 05:04:59 +04:00
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Bit8u reg1;
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Bit8u char_map_select;
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2002-10-25 15:44:41 +04:00
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bx_bool extended_mem;
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bx_bool odd_even;
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bx_bool chain_four;
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2001-04-10 05:04:59 +04:00
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} sequencer;
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2002-10-25 15:44:41 +04:00
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bx_bool vga_mem_updated;
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2001-04-10 05:04:59 +04:00
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unsigned x_tilesize;
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unsigned y_tilesize;
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2003-04-28 22:15:31 +04:00
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unsigned line_offset;
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2003-05-02 11:32:06 +04:00
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unsigned line_compare;
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unsigned vertical_display_end;
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2002-10-25 15:44:41 +04:00
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bx_bool vga_tile_updated[BX_NUM_X_TILES][BX_NUM_Y_TILES];
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2001-04-10 05:04:59 +04:00
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Bit8u vga_memory[256 * 1024];
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2003-06-05 22:18:14 +04:00
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Bit8u text_snapshot[32 * 1024]; // current text snapshot
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2001-04-10 05:04:59 +04:00
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Bit8u rgb[3 * 256];
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2003-06-30 22:53:12 +04:00
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Bit8u tile[X_TILESIZE * Y_TILESIZE * 4]; /**< Currently allocates the tile as large as needed. */
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2002-09-19 22:59:50 +04:00
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Bit16u charmap_address;
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2003-05-03 20:09:39 +04:00
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bx_bool x_dotclockdiv2;
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2003-04-21 23:03:46 +04:00
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bx_bool y_doublescan;
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2002-03-10 07:51:24 +03:00
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#if BX_SUPPORT_VBE
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2002-09-22 15:31:48 +04:00
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Bit8u vbe_memory[VBE_DISPI_TOTAL_VIDEO_MEMORY_BYTES];
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2002-04-29 17:06:06 +04:00
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Bit16u vbe_cur_dispi;
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2002-03-10 07:51:24 +03:00
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Bit16u vbe_xres;
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Bit16u vbe_yres;
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Bit16u vbe_bpp;
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Bit16u vbe_bank;
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2002-10-25 15:44:41 +04:00
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bx_bool vbe_enabled;
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2002-03-10 07:51:24 +03:00
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Bit16u vbe_curindex;
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2003-06-30 22:53:12 +04:00
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Bit32u vbe_visable_screen_size; /**< in bytes */
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Bit16u vbe_offset_x; /**< Virtual screen x start (in pixels) */
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Bit16u vbe_offset_y; /**< Virtual screen y start (in pixels) */
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2002-04-29 17:06:06 +04:00
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Bit16u vbe_virtual_xres;
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Bit16u vbe_virtual_yres;
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2003-07-16 21:56:25 +04:00
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Bit16u vbe_line_byte_width; /**< For dealing with bpp>8, this is they width of a line in bytes. */
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Bit32u vbe_virtual_start; /**< For dealing with bpp>8, this is where the virtual screen starts. */
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Bit8u vbe_bpp_multiplier; /**< We have to save this b/c sometimes we need to recalculate stuff with it. */
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bx_bool vbe_lfb_enabled;
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2002-03-10 07:51:24 +03:00
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#endif
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2001-04-10 05:04:59 +04:00
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} s; // state information
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#if !BX_USE_VGA_SMF
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Bit32u read(Bit32u address, unsigned io_len);
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2002-10-25 15:44:41 +04:00
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void write(Bit32u address, Bit32u value, unsigned io_len, bx_bool no_log);
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2001-04-10 05:04:59 +04:00
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#else
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2002-10-25 15:44:41 +04:00
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void write(Bit32u address, Bit32u value, unsigned io_len, bx_bool no_log);
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2001-04-10 05:04:59 +04:00
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#endif
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2002-03-10 07:51:24 +03:00
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#if BX_SUPPORT_VBE
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2003-06-30 22:53:12 +04:00
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2002-03-10 07:51:24 +03:00
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#if !BX_USE_VGA_SMF
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Bit32u vbe_read(Bit32u address, unsigned io_len);
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2002-10-25 15:44:41 +04:00
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void vbe_write(Bit32u address, Bit32u value, unsigned io_len, bx_bool no_log);
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2002-03-10 07:51:24 +03:00
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#else
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2002-10-25 15:44:41 +04:00
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void vbe_write(Bit32u address, Bit32u value, unsigned io_len, bx_bool no_log);
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2002-03-10 07:51:24 +03:00
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#endif
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#endif
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2001-06-09 23:57:56 +04:00
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int timer_id;
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2001-04-10 05:04:59 +04:00
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public:
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static void timer_handler(void *);
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BX_VGA_SMF void timer(void);
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2002-10-25 01:07:56 +04:00
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2001-04-10 05:04:59 +04:00
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private:
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BX_VGA_SMF void update(void);
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BX_VGA_SMF void dump_status(void);
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BX_VGA_SMF void determine_screen_dimensions(unsigned *piHeight,
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unsigned *piWidth);
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};
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