236 lines
6.7 KiB
Plaintext
236 lines
6.7 KiB
Plaintext
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----------------------------------------------------------------------
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Patch name: patch.eflags-bitfield
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Author: cbbochs@free.fr
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Date: July, 31th 2002
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Detailed description:
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- turns the eflags structure to a 32bits bitfield
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Patch was created with:
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cvs diff -u
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Apply patch to what version:
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cvs checked out on July, 31th 2002
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Instructions:
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To patch, go to main bochs directory.
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Type "patch -p0 < THIS_PATCH_FILE".
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----------------------------------------------------------------------
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Index: cpu/cpu.h
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v
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retrieving revision 1.22
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diff -u -r1.22 cpu.h
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--- cpu/cpu.h 5 Jun 2002 21:51:30 -0000 1.22
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+++ cpu/cpu.h 31 Jul 2002 13:23:58 -0000
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@@ -243,36 +243,45 @@
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* 0|NT| IOPL|OF|DF|IF|TF|SF|ZF| 0|AF| 0|PF| 1|CF
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*/
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- // In order to get access to these fields from the Dynamic Translation
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- // code, using only 8bit offsets, I needed to move these fields
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- // together.
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- Bit32u cf;
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- Bit32u af;
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- Bit32u zf;
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- Bit32u sf;
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- Bit32u of;
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-
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- Boolean bit1;
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- Bit8u pf_byte; /* PF derived from last result byte when needed */
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- Boolean bit3;
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- Boolean bit5;
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- Boolean tf;
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- Boolean if_;
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- Boolean df;
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+ Bit32u cf :1;
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+ Bit32u bit1 :1;
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+ Bit32u pf :1;
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+ Bit32u bit3 :1;
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+ Bit32u af :1;
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+ Bit32u bit5 :1;
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+ Bit32u zf :1;
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+ Bit32u sf :1;
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+ Bit32u tf :1;
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+ Bit32u if_ :1;
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+ Bit32u df :1;
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+ Bit32u of :1;
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#if BX_CPU_LEVEL >= 2
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- Bit8u iopl;
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- Boolean nt;
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+ Bit32u iopl :2;
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+ Bit32u nt :1;
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+#else
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+ Bit32u :2;
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+ Bit32u :1;
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#endif
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- Boolean bit15;
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+ Bit32u bit15 :1;
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+
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#if BX_CPU_LEVEL >= 3
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- Boolean rf;
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- Boolean vm;
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+ Boolean rf :1;
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+ Boolean vm :1;
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+#else
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+ Boolean :1;
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+ Boolean :1;
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#endif
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+
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#if BX_CPU_LEVEL >= 4
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- Boolean ac; // alignment check
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- // Boolean vif; // Virtual Interrupt Flag
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- // Boolean vip; // Virtual Interrupt Pending
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- Boolean id; // late model 486 and beyond had CPUID
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+ Boolean ac :1; // alignment check
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+ Boolean vif :1; // Virtual Interrupt Flag
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+ Boolean vip :1; // Virtual Interrupt Pending
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+ Boolean id :1; // late model 486 and beyond had CPUID
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+#else
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+ Boolean :1;
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+ Boolean :1;
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+ Boolean :1;
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+ Boolean :1;
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#endif
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} bx_flags_reg_t;
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@@ -755,7 +764,7 @@
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// status and control flags register set
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Bit32u lf_flags_status;
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- Boolean lf_pf;
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+ Bit8u lf_pf_byte;
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bx_flags_reg_t eflags;
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bx_lf_flags_entry oszapc;
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@@ -1649,7 +1658,6 @@
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#endif
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-
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#if BX_CPU_LEVEL >= 2
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BX_CPP_INLINE Boolean BX_CPU_C::real_mode(void) { return( !BX_CPU_THIS_PTR cr0.pe ); };
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#endif
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@@ -1717,12 +1725,12 @@
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BX_CPP_INLINE void
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BX_CPU_C::set_PF(Boolean val) {
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BX_CPU_THIS_PTR lf_flags_status &= 0xffff0f;
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- BX_CPU_THIS_PTR lf_pf = val;
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+ BX_CPU_THIS_PTR eflags.pf = val;
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}
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BX_CPP_INLINE void
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BX_CPU_C::set_PF_base(Bit8u val) {
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- BX_CPU_THIS_PTR eflags.pf_byte = val;
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+ BX_CPU_THIS_PTR lf_pf_byte = val;
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BX_CPU_THIS_PTR lf_flags_status = (BX_CPU_THIS_PTR lf_flags_status & 0xffff0f) | BX_LF_MASK_P;
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}
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@@ -1809,7 +1817,6 @@
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BX_CPU_THIS_PTR lf_flags_status &= 0x0ffff0; \
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/* ??? could also mark other bits undefined here */ \
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}
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-
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Index: cpu/lazy_flags.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/lazy_flags.cc,v
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retrieving revision 1.6
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diff -u -r1.6 lazy_flags.cc
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--- cpu/lazy_flags.cc 3 Oct 2001 13:10:37 -0000 1.6
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+++ cpu/lazy_flags.cc 31 Jul 2002 13:23:59 -0000
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@@ -707,7 +707,7 @@
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{
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switch ( (BX_CPU_THIS_PTR lf_flags_status>>4) & 0x00000f ) {
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case BX_LF_INDEX_KNOWN:
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- return(BX_CPU_THIS_PTR lf_pf);
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+ return(BX_CPU_THIS_PTR eflags.pf);
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case BX_LF_INDEX_OSZAPC:
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switch (BX_CPU_THIS_PTR oszapc.instr) {
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case BX_INSTR_ADD8:
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@@ -725,7 +725,7 @@
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case BX_INSTR_SCAS8:
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case BX_INSTR_SHR8:
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case BX_INSTR_SHL8:
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- BX_CPU_THIS_PTR lf_pf =
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+ BX_CPU_THIS_PTR eflags.pf =
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bx_parity_lookup[BX_CPU_THIS_PTR oszapc.result_8];
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break;
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case BX_INSTR_ADD16:
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@@ -743,7 +743,7 @@
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case BX_INSTR_SCAS16:
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case BX_INSTR_SHR16:
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case BX_INSTR_SHL16:
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- BX_CPU_THIS_PTR lf_pf =
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+ BX_CPU_THIS_PTR eflags.pf =
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bx_parity_lookup[(Bit8u) BX_CPU_THIS_PTR oszapc.result_16];
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break;
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case BX_INSTR_ADD32:
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@@ -761,42 +761,42 @@
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case BX_INSTR_SCAS32:
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case BX_INSTR_SHR32:
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case BX_INSTR_SHL32:
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- BX_CPU_THIS_PTR lf_pf =
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+ BX_CPU_THIS_PTR eflags.pf =
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bx_parity_lookup[(Bit8u) BX_CPU_THIS_PTR oszapc.result_32];
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break;
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default:
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BX_PANIC(("get_PF: OSZAPC: unknown instr"));
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}
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BX_CPU_THIS_PTR lf_flags_status &= 0xffff0f;
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- return(BX_CPU_THIS_PTR lf_pf);
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+ return(BX_CPU_THIS_PTR eflags.pf);
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case BX_LF_INDEX_OSZAP:
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switch (BX_CPU_THIS_PTR oszap.instr) {
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case BX_INSTR_INC8:
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case BX_INSTR_DEC8:
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- BX_CPU_THIS_PTR lf_pf =
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+ BX_CPU_THIS_PTR eflags.pf =
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bx_parity_lookup[BX_CPU_THIS_PTR oszap.result_8];
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break;
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case BX_INSTR_INC16:
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case BX_INSTR_DEC16:
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- BX_CPU_THIS_PTR lf_pf =
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+ BX_CPU_THIS_PTR eflags.pf =
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bx_parity_lookup[(Bit8u) BX_CPU_THIS_PTR oszap.result_16];
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break;
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case BX_INSTR_INC32:
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case BX_INSTR_DEC32:
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- BX_CPU_THIS_PTR lf_pf =
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+ BX_CPU_THIS_PTR eflags.pf =
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bx_parity_lookup[(Bit8u) BX_CPU_THIS_PTR oszap.result_32];
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break;
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default:
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BX_PANIC(("get_PF: OSZAP: unknown instr"));
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}
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BX_CPU_THIS_PTR lf_flags_status &= 0xffff0f;
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- return(BX_CPU_THIS_PTR lf_pf);
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+ return(BX_CPU_THIS_PTR eflags.pf);
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case BX_LF_INDEX_P:
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- BX_CPU_THIS_PTR lf_pf = bx_parity_lookup[BX_CPU_THIS_PTR eflags.pf_byte];
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+ BX_CPU_THIS_PTR eflags.pf = bx_parity_lookup[BX_CPU_THIS_PTR lf_pf_byte];
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BX_CPU_THIS_PTR lf_flags_status &= 0xffff0f;
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- return(BX_CPU_THIS_PTR lf_pf);
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+ return(BX_CPU_THIS_PTR eflags.pf);
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default:
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BX_PANIC(("get_PF: unknown case"));
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Index: cpu/init.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/init.cc,v
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retrieving revision 1.16
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diff -u -r1.16 init.cc
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--- cpu/init.cc 5 Jun 2002 21:51:30 -0000 1.16
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+++ cpu/init.cc 31 Jul 2002 14:33:49 -0000
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@@ -231,7 +231,7 @@
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// all status flags at known values, use BX_CPU_THIS_PTR eflags structure
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BX_CPU_THIS_PTR lf_flags_status = 0x000000;
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- BX_CPU_THIS_PTR lf_pf = 0;
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+ BX_CPU_THIS_PTR lf_pf_byte = 0;
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// status and control flags register set
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BX_CPU_THIS_PTR set_CF(0);
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