Bochs/bochs/cpudb.h

/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
//   Copyright (c) 2011-2017 Stanislav Shwartsman
//          Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
//  This library is free software; you can redistribute it and/or
//  modify it under the terms of the GNU Lesser General Public
//  License as published by the Free Software Foundation; either
//  version 2 of the License, or (at your option) any later version.
//
//  This library is distributed in the hope that it will be useful,
//  but WITHOUT ANY WARRANTY; without even the implied warranty of
//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
//  Lesser General Public License for more details.
//
//  You should have received a copy of the GNU Lesser General Public
//  License along with this library; if not, write to the Free Software
//  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
//
/////////////////////////////////////////////////////////////////////////

bx_define_cpudb(bx_generic)
#if BX_CPU_LEVEL >= 5
bx_define_cpudb(pentium)
bx_define_cpudb(pentium_mmx)
bx_define_cpudb(amd_k6_2_chomper)
#if BX_CPU_LEVEL >= 6
bx_define_cpudb(p2_klamath)
bx_define_cpudb(p3_katmai)
bx_define_cpudb(p4_willamette)
bx_define_cpudb(core_duo_t2400_yonah)
bx_define_cpudb(atom_n270)
#if BX_SUPPORT_X86_64
bx_define_cpudb(p4_prescott_celeron_336)
bx_define_cpudb(athlon64_clawhammer)
bx_define_cpudb(athlon64_venice)
bx_define_cpudb(turion64_tyler)
bx_define_cpudb(phenom_8650_toliman)
bx_define_cpudb(core2_penryn_t9600)
bx_define_cpudb(corei5_lynnfield_750)
bx_define_cpudb(corei5_arrandale_m520)
bx_define_cpudb(corei7_sandy_bridge_2600k)
#if BX_SUPPORT_AVX
bx_define_cpudb(zambezi)
bx_define_cpudb(trinity_apu)
bx_define_cpudb(ryzen)
bx_define_cpudb(corei7_ivy_bridge_3770k)
bx_define_cpudb(corei7_haswell_4770)
bx_define_cpudb(broadwell_ult)
bx_define_cpudb(corei7_skylake_x)
bx_define_cpudb(corei3_cnl)
bx_define_cpudb(corei7_icelake_u)
#endif
#endif
#endif
#endif
Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). Reimplemented CPUDB using pure C macros magic. Fixed compilation errors when compiling with SMP on. 2011-07-31 22:43:46 +04:00			`/////////////////////////////////////////////////////////////////////////`
			`// $Id$`
			`/////////////////////////////////////////////////////////////////////////`
			`//`
implemented CLZERO instruction from AMD Ryzen CPU 2017-03-25 23:12:31 +03:00			`// Copyright (c) 2011-2017 Stanislav Shwartsman`
Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). Reimplemented CPUDB using pure C macros magic. Fixed compilation errors when compiling with SMP on. 2011-07-31 22:43:46 +04:00			`// Written by Stanislav Shwartsman [sshwarts at sourceforge net]`
			`//`
			`// This library is free software; you can redistribute it and/or`
			`// modify it under the terms of the GNU Lesser General Public`
			`// License as published by the Free Software Foundation; either`
			`// version 2 of the License, or (at your option) any later version.`
			`//`
			`// This library is distributed in the hope that it will be useful,`
			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
			`// Lesser General Public License for more details.`
			`//`
			`// You should have received a copy of the GNU Lesser General Public`
			`// License along with this library; if not, write to the Free Software`
			`// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA`
			`//`
			`/////////////////////////////////////////////////////////////////////////`

			`bx_define_cpudb(bx_generic)`
allow to select CPU level = 5 from .bochsrc even when Bochs is compiled with CPU_LEVEL=6 2013-04-17 23:46:11 +04:00			`#if BX_CPU_LEVEL >= 5`
Cleanup of CPUDB modules, moved common functionality into bx_cpuid_t base class Added Pentium (P54C) AKA Pentium with no MMX to CPUDB 2015-02-12 00:31:17 +03:00			`bx_define_cpudb(pentium)`
added pentium mmx to cpudb. for now only can be enabled when cpu-level=5 2011-08-16 23:04:36 +04:00			`bx_define_cpudb(pentium_mmx)`
- Fixed compilation issue with cpu-level=5 - SYSCALL/SYSRET: SYSCALL/SYSRET instructions are not supported in legacy mode for Intel processors - CPUID: CPUID.0x80000001.EDX[11] SYSCALL/SYSRET support should not be reported outside long64 mode if legacy mode SYSCALL/SYSRET is not supported - Added new CPUDB entry - AMD K6-2 3D proc3essor (Chomper) 2011-08-31 02:00:27 +04:00			`bx_define_cpudb(amd_k6_2_chomper)`
allow to select CPU level = 5 from .bochsrc even when Bochs is compiled with CPU_LEVEL=6 2013-04-17 23:46:11 +04:00			`#if BX_CPU_LEVEL >= 6`
Added P2 Klamath CPUID + some code reorg again 2011-08-11 22:06:09 +04:00			`bx_define_cpudb(p2_klamath)`
Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). Reimplemented CPUDB using pure C macros magic. Fixed compilation errors when compiling with SMP on. 2011-07-31 22:43:46 +04:00			`bx_define_cpudb(p3_katmai)`
			`bx_define_cpudb(p4_willamette)`
added yonah CPUID to cpudb. remove bxversion.h from dep files 2011-08-16 23:58:56 +04:00			`bx_define_cpudb(core_duo_t2400_yonah)`
added atom n270 cpuid + small fixes 2011-08-03 21:49:49 +04:00			`bx_define_cpudb(atom_n270)`
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate 32-bit CPU using Bochs binary compiled with x86-64 support. The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg. 2011-09-25 21:36:20 +04:00			`#if BX_SUPPORT_X86_64`
Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). Reimplemented CPUDB using pure C macros magic. Fixed compilation errors when compiling with SMP on. 2011-07-31 22:43:46 +04:00			`bx_define_cpudb(p4_prescott_celeron_336)`
			`bx_define_cpudb(athlon64_clawhammer)`
added two AMD CPUs to CPUDB 2011-12-29 18:23:22 +04:00			`bx_define_cpudb(athlon64_venice)`
			`bx_define_cpudb(turion64_tyler)`
Major commit ! ------------ Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest ! A lot of code duplication was added for now - major cleanup will follow later. ! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled. Some CPUID modules rework done to enable Toliman configuration. Ckean up 'executable' attribute from all CPU source files. 2012-02-14 03:29:01 +04:00			`bx_define_cpudb(phenom_8650_toliman)`
dos2unix for generic_cpuid.cc fixed xsave leaf CPUID (again) added one more CPUID configuration: Intel Mobile Core 2 Duo T9600 2011-08-08 22:20:29 +04:00			`bx_define_cpudb(core2_penryn_t9600)`
Added Corei5 750 (Lynnfield) configuration to the CPUDB 2012-01-03 00:59:02 +04:00			`bx_define_cpudb(corei5_lynnfield_750)`
added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 23:32:44 +04:00			`bx_define_cpudb(corei5_arrandale_m520)`
following many users requests - allow sandy bridge configuration even when AVX is not compiled in, just disable AVX in it 2014-06-06 22:29:28 +04:00			`bx_define_cpudb(corei7_sandy_bridge_2600k)`
Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). Reimplemented CPUDB using pure C macros magic. Fixed compilation errors when compiling with SMP on. 2011-07-31 22:43:46 +04:00			`#if BX_SUPPORT_AVX`
added AMD Bulldozer architecture CPU (Zambezi) to CPUDB 2013-01-07 23:33:04 +04:00			`bx_define_cpudb(zambezi)`
CPUDB: added AMD Trinity to the database 2014-03-15 22:30:13 +04:00			`bx_define_cpudb(trinity_apu)`
reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct) 2017-03-13 22:44:14 +03:00			`bx_define_cpudb(ryzen)`
Added Corei7 ivyBridge configuration to CPUDB 2012-05-07 16:31:22 +04:00			`bx_define_cpudb(corei7_ivy_bridge_3770k)`
implemented fcs/fds deprecation. added haswell to cpudb.h as well 2013-06-21 00:12:53 +04:00			`bx_define_cpudb(corei7_haswell_4770)`
added Broadwell ULT CPUID definition to CPUDB 2015-02-13 00:28:24 +03:00			`bx_define_cpudb(broadwell_ult)`
added Skylake-X model to CPUDB -> with EVEX and AVX512 support 2017-08-09 23:36:17 +03:00			`bx_define_cpudb(corei7_skylake_x)`
add Intel Cannonlake CPU model to CPUDB featuring AVF512FMA52 and SHA instructions 2018-10-26 12:23:58 +03:00			`bx_define_cpudb(corei3_cnl)`
add Icelake-U model to CPUDB database. TODO: verify its VMX features 2019-09-24 23:26:14 +03:00			`bx_define_cpudb(corei7_icelake_u)`
added Skylake-X model to CPUDB -> with EVEX and AVX512 support 2017-08-09 23:36:17 +03:00			`#endif`
Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). Reimplemented CPUDB using pure C macros magic. Fixed compilation errors when compiling with SMP on. 2011-07-31 22:43:46 +04:00			`#endif`
			`#endif`
			`#endif`