2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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2007-11-17 21:08:46 +03:00
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// $Id: shift32.cc,v 1.33 2007-11-17 18:08:46 sshwarts Exp $
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2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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//
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2001-04-10 06:20:02 +04:00
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// Copyright (C) 2001 MandrakeSoft S.A.
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2001-04-10 05:04:59 +04:00
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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2007-11-17 21:08:46 +03:00
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/////////////////////////////////////////////////////////////////////////
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2001-04-10 05:04:59 +04:00
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2001-05-24 22:46:34 +04:00
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#define NEED_CPU_REG_SHORTCUTS 1
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2001-04-10 05:04:59 +04:00
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#include "bochs.h"
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2006-03-07 01:03:16 +03:00
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#include "cpu.h"
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merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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#define LOG_THIS BX_CPU_THIS_PTR
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2001-04-10 05:04:59 +04:00
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2004-12-25 01:44:13 +03:00
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void BX_CPU_C::SHLD_EdGd(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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Bit32u op1_32, op2_32, result_32;
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unsigned count;
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/* op1:op2 << count. result stored in op1 */
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2002-09-18 12:00:43 +04:00
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if (i->b1() == 0x1a4)
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2002-09-18 02:50:53 +04:00
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count = i->Ib() & 0x1f;
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2001-04-10 05:04:59 +04:00
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else // 0x1a5
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count = CL & 0x1f;
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2004-12-25 01:44:13 +03:00
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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if (!count) return;
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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result_32 = (op1_32 << count) | (op2_32 >> (32 - count));
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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2006-03-26 22:58:01 +04:00
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write_RMW_virtual_dword(result_32);
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2004-12-25 01:44:13 +03:00
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}
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/* set eflags:
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* SHLD count affects the following flags: O,S,Z,A,P,C
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*/
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SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHL32);
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2001-04-10 05:04:59 +04:00
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}
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2004-12-25 01:44:13 +03:00
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void BX_CPU_C::SHRD_EdGd(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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Bit32u op1_32, op2_32, result_32;
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unsigned count;
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2002-09-18 12:00:43 +04:00
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if (i->b1() == 0x1ac)
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2002-09-18 02:50:53 +04:00
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count = i->Ib() & 0x1f;
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2001-04-10 05:04:59 +04:00
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else // 0x1ad
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count = CL & 0x1f;
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2004-12-25 01:44:13 +03:00
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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if (!count) return;
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op2_32 = BX_READ_32BIT_REG(i->nnn());
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result_32 = (op2_32 << (32 - count)) | (op1_32 >> count);
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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2006-03-26 22:58:01 +04:00
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write_RMW_virtual_dword(result_32);
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2004-12-25 01:44:13 +03:00
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}
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/* set eflags:
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2005-10-14 00:21:35 +04:00
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* SHRD count affects the following flags: O,S,Z,A,P,C
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2004-12-25 01:44:13 +03:00
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*/
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2005-10-14 00:21:35 +04:00
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SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHRD32);
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2001-04-10 05:04:59 +04:00
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}
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2004-12-25 01:44:13 +03:00
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void BX_CPU_C::ROL_Ed(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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Bit32u op1_32, result_32;
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unsigned count;
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2002-09-18 12:00:43 +04:00
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if (i->b1() == 0xc1)
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2002-09-18 02:50:53 +04:00
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count = i->Ib() & 0x1f;
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2002-09-18 12:00:43 +04:00
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else if (i->b1() == 0xd1)
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2001-04-10 05:04:59 +04:00
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count = 1;
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2002-09-18 12:00:43 +04:00
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else // (i->b1() == 0xd3)
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2001-04-10 05:04:59 +04:00
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count = CL & 0x1f;
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2004-12-25 01:44:13 +03:00
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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if (! count) return;
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result_32 = (op1_32 << count) | (op1_32 >> (32 - count));
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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2006-03-26 22:58:01 +04:00
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write_RMW_virtual_dword(result_32);
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2004-12-25 01:44:13 +03:00
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}
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/* set eflags:
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* ROL count affects the following flags: C, O
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*/
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bx_bool temp_CF = (result_32 & 0x01);
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2007-10-22 02:07:33 +04:00
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setB_CF(temp_CF);
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setB_OF(temp_CF ^ (result_32 >> 31));
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2001-04-10 05:04:59 +04:00
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}
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2004-12-25 01:44:13 +03:00
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void BX_CPU_C::ROR_Ed(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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2004-08-28 00:13:32 +04:00
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Bit32u op1_32, result_32;
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2001-04-10 05:04:59 +04:00
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unsigned count;
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2002-09-18 12:00:43 +04:00
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if (i->b1() == 0xc1)
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2002-09-18 02:50:53 +04:00
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count = i->Ib() & 0x1f;
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2002-09-18 12:00:43 +04:00
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else if (i->b1() == 0xd1)
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2001-04-10 05:04:59 +04:00
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count = 1;
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2002-09-18 12:00:43 +04:00
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else // (i->b1() == 0xd3)
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2001-04-10 05:04:59 +04:00
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count = CL & 0x1f;
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2004-12-25 01:44:13 +03:00
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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if (! count) return;
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result_32 = (op1_32 >> count) | (op1_32 << (32 - count));
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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2006-03-26 22:58:01 +04:00
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write_RMW_virtual_dword(result_32);
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2004-12-25 01:44:13 +03:00
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}
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/* set eflags:
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* ROR count affects the following flags: C, O
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*/
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bx_bool result_b31 = (result_32 & 0x80000000) != 0;
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2005-10-13 23:28:10 +04:00
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bx_bool result_b30 = (result_32 & 0x40000000) != 0;
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2004-12-25 01:44:13 +03:00
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2007-10-22 02:07:33 +04:00
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setB_CF(result_b31);
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setB_OF(result_b31 ^ result_b30);
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2001-04-10 05:04:59 +04:00
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}
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2004-12-25 01:44:13 +03:00
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void BX_CPU_C::RCL_Ed(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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Bit32u op1_32, result_32;
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unsigned count;
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2002-09-18 12:00:43 +04:00
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if (i->b1() == 0xc1)
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2002-09-18 02:50:53 +04:00
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count = i->Ib() & 0x1f;
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2002-09-18 12:00:43 +04:00
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else if (i->b1() == 0xd1)
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2001-04-10 05:04:59 +04:00
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count = 1;
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2002-09-18 12:00:43 +04:00
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else // (i->b1() == 0xd3)
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2001-04-10 05:04:59 +04:00
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count = CL & 0x1f;
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2004-12-25 01:44:13 +03:00
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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if (!count) return;
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if (count==1) {
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result_32 = (op1_32 << 1) | getB_CF();
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}
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else {
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result_32 = (op1_32 << count) | (getB_CF() << (count - 1)) |
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2001-04-10 05:04:59 +04:00
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(op1_32 >> (33 - count));
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2004-12-25 01:44:13 +03:00
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}
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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2006-03-26 22:58:01 +04:00
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write_RMW_virtual_dword(result_32);
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2004-12-25 01:44:13 +03:00
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}
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/* set eflags:
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* RCL count affects the following flags: C, O
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*/
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bx_bool temp_CF = (op1_32 >> (32 - count)) & 0x01;
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2007-10-22 02:07:33 +04:00
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setB_CF(temp_CF);
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setB_OF(temp_CF ^ (result_32 >> 31));
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2004-08-28 00:13:32 +04:00
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}
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2001-04-10 05:04:59 +04:00
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2004-12-25 01:44:13 +03:00
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void BX_CPU_C::RCR_Ed(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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Bit32u op1_32, result_32;
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unsigned count;
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2002-09-18 12:00:43 +04:00
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if (i->b1() == 0xc1)
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2002-09-18 02:50:53 +04:00
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count = i->Ib() & 0x1f;
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2002-09-18 12:00:43 +04:00
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else if (i->b1() == 0xd1)
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2001-04-10 05:04:59 +04:00
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count = 1;
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2002-09-18 12:00:43 +04:00
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else // (i->b1() == 0xd3)
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2001-04-10 05:04:59 +04:00
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count = CL & 0x1f;
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2004-12-25 01:44:13 +03:00
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/* op1 is a register or memory reference */
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if (i->modC0()) {
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op1_32 = BX_READ_32BIT_REG(i->rm());
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}
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else {
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/* pointer, segment address pair */
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read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
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}
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if (!count) return;
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if (count==1) {
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result_32 = (op1_32 >> 1) | (getB_CF() << 31);
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}
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else {
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result_32 = (op1_32 >> count) | (getB_CF() << (32 - count)) |
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2001-04-10 05:04:59 +04:00
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(op1_32 << (33 - count));
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2004-12-25 01:44:13 +03:00
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}
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/* now write result back to destination */
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if (i->modC0()) {
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BX_WRITE_32BIT_REGZ(i->rm(), result_32);
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}
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else {
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2006-03-26 22:58:01 +04:00
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write_RMW_virtual_dword(result_32);
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2004-12-25 01:44:13 +03:00
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}
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/* set eflags:
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* RCR count affects the following flags: C, O
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*/
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2007-10-22 02:07:33 +04:00
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setB_CF((op1_32 >> (count - 1)) & 0x01);
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setB_OF((((result_32 << 1) ^ result_32) & 0x80000000) > 0);
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2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
void BX_CPU_C::SHL_Ed(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
Bit32u op1_32, result_32;
|
|
|
|
unsigned count;
|
|
|
|
|
2002-09-18 12:00:43 +04:00
|
|
|
if (i->b1() == 0xc1)
|
2002-09-18 02:50:53 +04:00
|
|
|
count = i->Ib() & 0x1f;
|
2002-09-18 12:00:43 +04:00
|
|
|
else if (i->b1() == 0xd1)
|
2001-04-10 05:04:59 +04:00
|
|
|
count = 1;
|
2002-09-18 12:00:43 +04:00
|
|
|
else // (i->b1() == 0xd3)
|
2001-04-10 05:04:59 +04:00
|
|
|
count = CL & 0x1f;
|
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
/* op1 is a register or memory reference */
|
|
|
|
if (i->modC0()) {
|
|
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
/* pointer, segment address pair */
|
|
|
|
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
if (!count) return;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
result_32 = (op1_32 << count);
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
/* now write result back to destination */
|
|
|
|
if (i->modC0()) {
|
|
|
|
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
|
|
|
}
|
|
|
|
else {
|
2006-03-26 22:58:01 +04:00
|
|
|
write_RMW_virtual_dword(result_32);
|
2004-12-25 01:44:13 +03:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHL32);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
void BX_CPU_C::SHR_Ed(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
Bit32u op1_32, result_32;
|
|
|
|
unsigned count;
|
|
|
|
|
2002-09-18 12:00:43 +04:00
|
|
|
if (i->b1() == 0xc1)
|
2002-09-18 02:50:53 +04:00
|
|
|
count = i->Ib() & 0x1f;
|
2002-09-18 12:00:43 +04:00
|
|
|
else if (i->b1() == 0xd1)
|
2001-04-10 05:04:59 +04:00
|
|
|
count = 1;
|
2002-09-18 12:00:43 +04:00
|
|
|
else // (i->b1() == 0xd3)
|
2001-04-10 05:04:59 +04:00
|
|
|
count = CL & 0x1f;
|
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
/* op1 is a register or memory reference */
|
|
|
|
if (i->modC0()) {
|
|
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
/* pointer, segment address pair */
|
|
|
|
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2007-10-22 02:07:33 +04:00
|
|
|
if (!count) return;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
result_32 = (op1_32 >> count);
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SHR32);
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
/* now write result back to destination */
|
|
|
|
if (i->modC0()) {
|
|
|
|
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
|
|
|
}
|
|
|
|
else {
|
2006-03-26 22:58:01 +04:00
|
|
|
write_RMW_virtual_dword(result_32);
|
2004-12-25 01:44:13 +03:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
void BX_CPU_C::SAR_Ed(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
Bit32u op1_32, result_32;
|
|
|
|
unsigned count;
|
|
|
|
|
2002-09-18 12:00:43 +04:00
|
|
|
if (i->b1() == 0xc1)
|
2002-09-18 02:50:53 +04:00
|
|
|
count = i->Ib() & 0x1f;
|
2002-09-18 12:00:43 +04:00
|
|
|
else if (i->b1() == 0xd1)
|
2001-04-10 05:04:59 +04:00
|
|
|
count = 1;
|
2002-09-18 12:00:43 +04:00
|
|
|
else // (i->b1() == 0xd3)
|
2001-04-10 05:04:59 +04:00
|
|
|
count = CL & 0x1f;
|
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
/* op1 is a register or memory reference */
|
|
|
|
if (i->modC0()) {
|
|
|
|
op1_32 = BX_READ_32BIT_REG(i->rm());
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
/* pointer, segment address pair */
|
|
|
|
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-12-25 01:44:13 +03:00
|
|
|
if (!count) return;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2005-07-01 18:06:02 +04:00
|
|
|
/* count < 32, since only lower 5 bits used */
|
2004-12-25 01:44:13 +03:00
|
|
|
if (op1_32 & 0x80000000) {
|
|
|
|
result_32 = (op1_32 >> count) | (0xffffffff << (32 - count));
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
result_32 = (op1_32 >> count);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* now write result back to destination */
|
|
|
|
if (i->modC0()) {
|
|
|
|
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
|
|
|
|
}
|
|
|
|
else {
|
2006-03-26 22:58:01 +04:00
|
|
|
write_RMW_virtual_dword(result_32);
|
2004-12-25 01:44:13 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
SET_FLAGS_OSZAPC_32(op1_32, count, result_32, BX_INSTR_SAR32);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|