2004-06-18 18:11:11 +04:00
|
|
|
/////////////////////////////////////////////////////////////////////////
|
2011-02-25 01:05:47 +03:00
|
|
|
// $Id$
|
2005-03-21 00:19:38 +03:00
|
|
|
/////////////////////////////////////////////////////////////////////////
|
2004-06-18 18:11:11 +04:00
|
|
|
//
|
2009-10-15 00:45:29 +04:00
|
|
|
// Copyright (c) 2003-2009 Stanislav Shwartsman
|
2007-03-24 00:27:13 +03:00
|
|
|
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
|
2004-06-18 18:11:11 +04:00
|
|
|
//
|
|
|
|
// This library is free software; you can redistribute it and/or
|
|
|
|
// modify it under the terms of the GNU Lesser General Public
|
|
|
|
// License as published by the Free Software Foundation; either
|
|
|
|
// version 2 of the License, or (at your option) any later version.
|
|
|
|
//
|
|
|
|
// This library is distributed in the hope that it will be useful,
|
|
|
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
// Lesser General Public License for more details.
|
|
|
|
//
|
|
|
|
// You should have received a copy of the GNU Lesser General Public
|
|
|
|
// License along with this library; if not, write to the Free Software
|
2009-02-08 20:29:34 +03:00
|
|
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
2005-05-12 22:07:48 +04:00
|
|
|
//
|
2004-06-18 18:11:11 +04:00
|
|
|
/////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
#define NEED_CPU_REG_SHORTCUTS 1
|
|
|
|
#include "bochs.h"
|
2006-03-07 01:03:16 +03:00
|
|
|
#include "cpu/cpu.h"
|
2004-06-18 18:11:11 +04:00
|
|
|
#define LOG_THIS BX_CPU_THIS_PTR
|
|
|
|
|
2008-04-05 01:05:37 +04:00
|
|
|
#if BX_SUPPORT_FPU
|
|
|
|
|
2004-06-18 18:11:11 +04:00
|
|
|
#include "softfloatx80.h"
|
|
|
|
#include "softfloat-specialize.h"
|
|
|
|
|
2015-05-02 23:08:36 +03:00
|
|
|
extern float_status_t i387cw_to_softfloat_status_word(Bit16u control_word);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
/* D9 F0 */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::F2XM1(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
|
|
|
|
2008-05-10 13:17:24 +04:00
|
|
|
if (IS_TAG_EMPTY(0)) {
|
2009-05-28 23:25:33 +04:00
|
|
|
FPU_stack_underflow(0);
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word() | FPU_PR_80_BITS);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
floatx80 result = f2xm1(BX_READ_FPU_REG(0), status);
|
|
|
|
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags))
|
2009-03-11 00:43:11 +03:00
|
|
|
BX_WRITE_FPU_REG(result, 0);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 F1 */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FYL2X(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
|
|
|
|
|
|
|
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(1))
|
|
|
|
{
|
2009-11-01 20:37:14 +03:00
|
|
|
FPU_stack_underflow(1, 1 /* pop_stack */);
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word() | FPU_PR_80_BITS);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
floatx80 result = fyl2x(BX_READ_FPU_REG(0), BX_READ_FPU_REG(1), status);
|
|
|
|
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags)) {
|
2009-03-11 00:43:11 +03:00
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
BX_WRITE_FPU_REG(result, 0);
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 F2 */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FPTAN(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
|
|
|
clear_C2();
|
|
|
|
|
2008-05-10 14:15:01 +04:00
|
|
|
if (IS_TAG_EMPTY(0) || ! IS_TAG_EMPTY(-1))
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
2008-05-10 14:15:01 +04:00
|
|
|
if(IS_TAG_EMPTY(0))
|
2009-05-28 23:25:33 +04:00
|
|
|
FPU_exception(FPU_EX_Stack_Underflow);
|
2008-05-10 14:15:01 +04:00
|
|
|
else
|
2009-05-28 23:25:33 +04:00
|
|
|
FPU_exception(FPU_EX_Stack_Overflow);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2008-05-10 13:17:24 +04:00
|
|
|
/* The masked response */
|
|
|
|
if (BX_CPU_THIS_PTR the_i387.is_IA_masked())
|
|
|
|
{
|
2008-05-10 17:34:01 +04:00
|
|
|
BX_WRITE_FPU_REG(floatx80_default_nan, 0);
|
2008-05-10 13:17:24 +04:00
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_push();
|
2008-05-10 17:34:01 +04:00
|
|
|
BX_WRITE_FPU_REG(floatx80_default_nan, 0);
|
2008-05-10 13:17:24 +04:00
|
|
|
}
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2004-06-19 19:20:15 +04:00
|
|
|
extern const floatx80 Const_1;
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word() | FPU_PR_80_BITS);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
floatx80 y = BX_READ_FPU_REG(0);
|
|
|
|
if (ftan(y, status) == -1)
|
|
|
|
{
|
2008-05-10 13:17:24 +04:00
|
|
|
FPU_PARTIAL_STATUS |= FPU_SW_C2;
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
if (floatx80_is_nan(y))
|
|
|
|
{
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags))
|
2008-05-10 13:17:24 +04:00
|
|
|
{
|
2008-05-10 17:34:01 +04:00
|
|
|
BX_WRITE_FPU_REG(y, 0);
|
2008-05-10 13:17:24 +04:00
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_push();
|
2008-05-10 17:34:01 +04:00
|
|
|
BX_WRITE_FPU_REG(y, 0);
|
2008-05-10 13:17:24 +04:00
|
|
|
}
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags)) {
|
2009-03-11 00:43:11 +03:00
|
|
|
BX_WRITE_FPU_REG(y, 0);
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_push();
|
|
|
|
BX_WRITE_FPU_REG(Const_1, 0);
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 F3 */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FPATAN(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
2008-07-14 22:54:10 +04:00
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
|
|
|
|
|
|
|
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(1))
|
|
|
|
{
|
2009-11-01 20:37:14 +03:00
|
|
|
FPU_stack_underflow(1, 1 /* pop_stack */);
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word() | FPU_PR_80_BITS);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
floatx80 result = fpatan(BX_READ_FPU_REG(0), BX_READ_FPU_REG(1), status);
|
|
|
|
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags)) {
|
2009-03-11 00:43:11 +03:00
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
BX_WRITE_FPU_REG(result, 0);
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 F4 */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FXTRACT(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
|
|
|
|
2008-05-10 14:15:01 +04:00
|
|
|
if (IS_TAG_EMPTY(0) || ! IS_TAG_EMPTY(-1))
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
2008-05-10 14:15:01 +04:00
|
|
|
if(IS_TAG_EMPTY(0))
|
2009-05-28 23:25:33 +04:00
|
|
|
FPU_exception(FPU_EX_Stack_Underflow);
|
2008-05-10 14:15:01 +04:00
|
|
|
else
|
2009-05-28 23:25:33 +04:00
|
|
|
FPU_exception(FPU_EX_Stack_Overflow);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2008-05-10 13:17:24 +04:00
|
|
|
/* The masked response */
|
|
|
|
if (BX_CPU_THIS_PTR the_i387.is_IA_masked())
|
|
|
|
{
|
2008-05-10 17:34:01 +04:00
|
|
|
BX_WRITE_FPU_REG(floatx80_default_nan, 0);
|
2008-05-10 13:17:24 +04:00
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_push();
|
2008-05-10 17:34:01 +04:00
|
|
|
BX_WRITE_FPU_REG(floatx80_default_nan, 0);
|
2008-05-10 13:17:24 +04:00
|
|
|
}
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
floatx80 a = BX_READ_FPU_REG(0);
|
|
|
|
floatx80 b = floatx80_extract(a, status);
|
|
|
|
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags)) {
|
2009-03-11 00:43:11 +03:00
|
|
|
BX_WRITE_FPU_REG(b, 0); // exponent
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_push();
|
|
|
|
BX_WRITE_FPU_REG(a, 0); // fraction
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 F5 */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FPREM1(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
2009-05-21 22:24:00 +04:00
|
|
|
clear_C2();
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(1))
|
|
|
|
{
|
2009-05-28 23:25:33 +04:00
|
|
|
FPU_stack_underflow(0);
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
Bit64u quotient;
|
|
|
|
|
|
|
|
floatx80 a = BX_READ_FPU_REG(0);
|
|
|
|
floatx80 b = BX_READ_FPU_REG(1);
|
2010-03-23 01:11:00 +03:00
|
|
|
floatx80 result;
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2010-03-23 01:11:00 +03:00
|
|
|
int flags = floatx80_ieee754_remainder(a, b, result, quotient, status);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags)) {
|
2010-03-23 01:11:00 +03:00
|
|
|
if (flags >= 0) {
|
2010-03-22 21:09:40 +03:00
|
|
|
int cc = 0;
|
2010-03-23 01:11:00 +03:00
|
|
|
if (flags) cc = FPU_SW_C2;
|
2010-03-22 21:09:40 +03:00
|
|
|
else {
|
|
|
|
if (quotient & 1) cc |= FPU_SW_C1;
|
|
|
|
if (quotient & 2) cc |= FPU_SW_C3;
|
|
|
|
if (quotient & 4) cc |= FPU_SW_C0;
|
|
|
|
}
|
|
|
|
setcc(cc);
|
2009-03-11 00:43:11 +03:00
|
|
|
}
|
|
|
|
BX_WRITE_FPU_REG(result, 0);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 F8 */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FPREM(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
2009-05-21 22:24:00 +04:00
|
|
|
clear_C2();
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(1))
|
|
|
|
{
|
2009-05-28 23:25:33 +04:00
|
|
|
FPU_stack_underflow(0);
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
Bit64u quotient;
|
|
|
|
|
|
|
|
floatx80 a = BX_READ_FPU_REG(0);
|
|
|
|
floatx80 b = BX_READ_FPU_REG(1);
|
2010-03-23 01:11:00 +03:00
|
|
|
floatx80 result;
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2010-03-23 01:11:00 +03:00
|
|
|
int flags = floatx80_remainder(a, b, result, quotient, status);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags)) {
|
2010-03-23 01:11:00 +03:00
|
|
|
if (flags >= 0) {
|
2010-03-22 21:09:40 +03:00
|
|
|
int cc = 0;
|
2010-03-23 01:11:00 +03:00
|
|
|
if (flags) cc = FPU_SW_C2;
|
2010-03-22 21:09:40 +03:00
|
|
|
else {
|
|
|
|
if (quotient & 1) cc |= FPU_SW_C1;
|
|
|
|
if (quotient & 2) cc |= FPU_SW_C3;
|
|
|
|
if (quotient & 4) cc |= FPU_SW_C0;
|
|
|
|
}
|
|
|
|
setcc(cc);
|
2009-03-11 00:43:11 +03:00
|
|
|
}
|
|
|
|
BX_WRITE_FPU_REG(result, 0);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 F9 */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FYL2XP1(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
|
|
|
|
|
|
|
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(1))
|
|
|
|
{
|
2009-11-01 20:37:14 +03:00
|
|
|
FPU_stack_underflow(1, 1 /* pop_stack */);
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word() | FPU_PR_80_BITS);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
floatx80 result = fyl2xp1(BX_READ_FPU_REG(0), BX_READ_FPU_REG(1), status);
|
|
|
|
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags)) {
|
2009-03-11 00:43:11 +03:00
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_pop();
|
|
|
|
BX_WRITE_FPU_REG(result, 0);
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 FB */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FSINCOS(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
|
|
|
clear_C2();
|
|
|
|
|
2008-05-10 14:15:01 +04:00
|
|
|
if (IS_TAG_EMPTY(0) || ! IS_TAG_EMPTY(-1))
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
2008-05-10 14:15:01 +04:00
|
|
|
if(IS_TAG_EMPTY(0))
|
2009-05-28 23:25:33 +04:00
|
|
|
FPU_exception(FPU_EX_Stack_Underflow);
|
2008-05-10 14:15:01 +04:00
|
|
|
else
|
2009-05-28 23:25:33 +04:00
|
|
|
FPU_exception(FPU_EX_Stack_Overflow);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2008-05-10 13:17:24 +04:00
|
|
|
/* The masked response */
|
|
|
|
if (BX_CPU_THIS_PTR the_i387.is_IA_masked())
|
|
|
|
{
|
2008-05-10 17:34:01 +04:00
|
|
|
BX_WRITE_FPU_REG(floatx80_default_nan, 0);
|
2008-05-10 13:17:24 +04:00
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_push();
|
2008-05-10 17:34:01 +04:00
|
|
|
BX_WRITE_FPU_REG(floatx80_default_nan, 0);
|
2008-05-10 13:17:24 +04:00
|
|
|
}
|
2004-06-18 18:11:11 +04:00
|
|
|
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word() | FPU_PR_80_BITS);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
floatx80 y = BX_READ_FPU_REG(0);
|
|
|
|
floatx80 sin_y, cos_y;
|
2008-02-06 01:33:35 +03:00
|
|
|
if (fsincos(y, &sin_y, &cos_y, status) == -1)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
2008-05-10 13:17:24 +04:00
|
|
|
FPU_PARTIAL_STATUS |= FPU_SW_C2;
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags)) {
|
2009-03-11 00:43:11 +03:00
|
|
|
BX_WRITE_FPU_REG(sin_y, 0);
|
|
|
|
BX_CPU_THIS_PTR the_i387.FPU_push();
|
|
|
|
BX_WRITE_FPU_REG(cos_y, 0);
|
|
|
|
}
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 FD */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FSCALE(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
|
|
|
|
|
|
|
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(1))
|
|
|
|
{
|
2009-05-28 23:25:33 +04:00
|
|
|
FPU_stack_underflow(0);
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word());
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
floatx80 result = floatx80_scale(BX_READ_FPU_REG(0), BX_READ_FPU_REG(1), status);
|
|
|
|
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags))
|
2009-03-11 00:43:11 +03:00
|
|
|
BX_WRITE_FPU_REG(result, 0);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 FE */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FSIN(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
|
|
|
clear_C2();
|
|
|
|
|
2008-05-10 13:17:24 +04:00
|
|
|
if (IS_TAG_EMPTY(0)) {
|
2009-05-28 23:25:33 +04:00
|
|
|
FPU_stack_underflow(0);
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word() | FPU_PR_80_BITS);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
floatx80 y = BX_READ_FPU_REG(0);
|
|
|
|
if (fsin(y, status) == -1)
|
|
|
|
{
|
2008-05-10 13:17:24 +04:00
|
|
|
FPU_PARTIAL_STATUS |= FPU_SW_C2;
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags))
|
2009-03-11 00:43:11 +03:00
|
|
|
BX_WRITE_FPU_REG(y, 0);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* D9 FF */
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCOS(bxInstruction_c *i)
|
2004-06-18 18:11:11 +04:00
|
|
|
{
|
|
|
|
BX_CPU_THIS_PTR prepareFPU(i);
|
2009-04-27 18:00:55 +04:00
|
|
|
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
clear_C1();
|
|
|
|
clear_C2();
|
|
|
|
|
2008-05-10 13:17:24 +04:00
|
|
|
if (IS_TAG_EMPTY(0)) {
|
2009-05-28 23:25:33 +04:00
|
|
|
FPU_stack_underflow(0);
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2008-02-06 01:33:35 +03:00
|
|
|
float_status_t status =
|
2015-05-02 23:08:36 +03:00
|
|
|
i387cw_to_softfloat_status_word(BX_CPU_THIS_PTR the_i387.get_control_word() | FPU_PR_80_BITS);
|
2004-06-18 18:11:11 +04:00
|
|
|
|
|
|
|
floatx80 y = BX_READ_FPU_REG(0);
|
|
|
|
if (fcos(y, status) == -1)
|
|
|
|
{
|
2008-05-10 13:17:24 +04:00
|
|
|
FPU_PARTIAL_STATUS |= FPU_SW_C2;
|
2011-07-07 00:01:18 +04:00
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
|
|
|
|
2009-05-28 23:25:33 +04:00
|
|
|
if (! FPU_exception(status.float_exception_flags))
|
2009-03-11 00:43:11 +03:00
|
|
|
BX_WRITE_FPU_REG(y, 0);
|
2011-07-07 00:01:18 +04:00
|
|
|
|
|
|
|
BX_NEXT_INSTR(i);
|
2004-06-18 18:11:11 +04:00
|
|
|
}
|
2008-04-05 01:05:37 +04:00
|
|
|
|
|
|
|
#endif
|