2005-08-10 23:04:19 +04:00
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TODO (know issues in CPU model):
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-------------------------------
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[!] The following 3DNow! instructions still not implemented:
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PF2IW_PqQq
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PFNACC_PqQq
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PFPNACC_PqQq
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PFCMPGE_PqQq
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PFCMPGT_PqQq
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PFCMPEQ_PqQq
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PFMIN_PqQq
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PFMAX_PqQq
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PFRCP_PqQq
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PFRSQRT_PqQq
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PFSUB_PqQq
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PFSUBR_PqQq
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PFADD_PqQq
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PFACC_PqQq,
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PFMUL_PqQq
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PFRCPIT1_PqQq
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PFRSQIT1_PqQq
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PFRCPIT2_PqQq
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[!] CPUID does not report 3DNow! instruction set
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2006-01-11 21:22:12 +03:00
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[!] Some of APIC functionality still not implemented, for example
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- Globally disabled APIC
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- NMI, SMI, INIT signals, LVT pins handling
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- Filter interrupts according processor priority (PPR)
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2005-08-10 23:04:19 +04:00
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2006-01-06 00:40:07 +03:00
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[!] No support of AC flag (alignment checking) and #AC exception
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2005-10-14 02:53:03 +04:00
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2005-11-22 00:15:35 +03:00
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#AC exception should be generated if trying to do unaligned memory
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access when
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CPL == 3 && CR.AM == 1 && EFLAGS.AC == 1
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2005-10-14 02:53:03 +04:00
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[!] REP NOP is PAUSE (on P4/XEON)
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When running in SMP mode, this means that we are in a spin loop.
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This processor should yield to the other one, as we are anyhow waiting
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for a lock, and any other processor is responsible for this.
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