2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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2005-07-10 20:51:09 +04:00
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// $Id: serial.cc,v 1.65 2005-07-10 16:51:08 vruppert Exp $
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2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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//
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2004-01-17 18:51:09 +03:00
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// Copyright (C) 2004 MandrakeSoft S.A.
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2001-04-10 05:04:59 +04:00
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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2003-11-09 03:14:43 +03:00
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// Peter Grehan (grehan@iprg.nokia.com) coded the original version of this
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// serial emulation. He implemented a single 8250, and allow terminal
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// input/output to stdout on FreeBSD.
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2004-01-18 14:58:07 +03:00
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// The current version emulates up to 4 UART 16550A with FIFO. Terminal
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2003-11-09 03:14:43 +03:00
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// input/output now works on some more platforms.
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2001-04-10 05:04:59 +04:00
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2002-10-25 01:07:56 +04:00
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// Define BX_PLUGGABLE in files that can be compiled into plugins. For
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// platforms that require a special tag on exported symbols, BX_PLUGGABLE
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// is used to know when we are exporting symbols and when we are importing.
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#define BX_PLUGGABLE
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2004-06-19 19:20:15 +04:00
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#include "iodev.h"
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2005-07-10 20:51:09 +04:00
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#ifndef WIN32
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#include <sys/socket.h>
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#include <netdb.h>
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#endif
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2002-10-25 01:07:56 +04:00
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2004-09-05 14:30:19 +04:00
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#if USE_RAW_SERIAL
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#include "serial_raw.h"
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#endif // USE_RAW_SERIAL
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2002-10-25 01:07:56 +04:00
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#define LOG_THIS theSerialDevice->
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2001-04-10 05:04:59 +04:00
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2002-10-25 01:07:56 +04:00
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bx_serial_c *theSerialDevice = NULL;
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int
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libserial_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
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{
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theSerialDevice = new bx_serial_c ();
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bx_devices.pluginSerialDevice = theSerialDevice;
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BX_REGISTER_DEVICE_DEVMODEL(plugin, type, theSerialDevice, BX_PLUGIN_SERIAL);
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return(0); // Success
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}
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void
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libserial_LTX_plugin_fini(void)
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{
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}
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2001-04-10 05:04:59 +04:00
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bx_serial_c::bx_serial_c(void)
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{
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2001-06-27 23:16:01 +04:00
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put("SER");
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merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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settype(SERLOG);
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2002-10-06 23:04:47 +04:00
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for (int i=0; i<BX_SERIAL_MAXDEV; i++) {
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2004-01-18 03:18:44 +03:00
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s[i].tty_id = -1;
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2002-10-06 23:04:47 +04:00
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s[i].tx_timer_index = BX_NULL_TIMER_HANDLE;
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s[i].rx_timer_index = BX_NULL_TIMER_HANDLE;
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2003-11-09 03:14:43 +03:00
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s[i].fifo_timer_index = BX_NULL_TIMER_HANDLE;
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2002-10-06 23:04:47 +04:00
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}
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2002-03-03 09:03:29 +03:00
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}
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bx_serial_c::~bx_serial_c(void)
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{
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2004-01-18 03:18:44 +03:00
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for (int i=0; i<BX_SERIAL_MAXDEV; i++) {
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2004-02-29 01:06:36 +03:00
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if (bx_options.com[i].Oenabled->get ()) {
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2004-07-28 23:36:42 +04:00
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switch (BX_SER_THIS s[i].io_mode) {
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case BX_SER_MODE_FILE:
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if (BX_SER_THIS s[i].output != NULL)
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fclose(BX_SER_THIS s[i].output);
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break;
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case BX_SER_MODE_TERM:
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2005-07-10 20:51:09 +04:00
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#if defined(SERIAL_ENABLE) && !defined(WIN32)
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2004-07-28 23:36:42 +04:00
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if (s[i].tty_id >= 0) {
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tcsetattr(s[i].tty_id, TCSAFLUSH, &s[i].term_orig);
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}
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#endif
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break;
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case BX_SER_MODE_RAW:
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2004-02-29 00:28:28 +03:00
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#if USE_RAW_SERIAL
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2004-07-28 23:36:42 +04:00
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delete [] BX_SER_THIS s[i].raw;
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2002-03-03 09:03:29 +03:00
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#endif
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2004-07-28 23:36:42 +04:00
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break;
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2005-07-10 20:51:09 +04:00
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case BX_SER_MODE_SOCKET:
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if (BX_SER_THIS s[i].socket_id >= 0) ::close(BX_SER_THIS s[i].socket_id);
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break;
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2004-07-28 23:36:42 +04:00
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}
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2004-02-29 01:06:36 +03:00
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}
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2004-02-29 00:28:28 +03:00
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}
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2002-03-03 09:03:29 +03:00
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}
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void
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2002-10-25 01:07:56 +04:00
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bx_serial_c::init(void)
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2002-03-03 09:03:29 +03:00
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{
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2003-10-30 00:00:04 +03:00
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Bit16u ports[BX_SERIAL_MAXDEV] = {0x03f8, 0x02f8, 0x03e8, 0x02e8};
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char name[16];
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2005-01-19 21:21:40 +03:00
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unsigned i;
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2003-10-30 00:00:04 +03:00
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2004-12-05 23:23:39 +03:00
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BX_SER_THIS detect_mouse = 0;
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2004-12-03 00:34:26 +03:00
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BX_SER_THIS mouse_port = -1;
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BX_SER_THIS mouse_internal_buffer.num_elements = 0;
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2005-01-19 21:21:40 +03:00
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for (i=0; i<BX_MOUSE_BUFF_SIZE; i++)
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2004-12-03 00:34:26 +03:00
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BX_SER_THIS mouse_internal_buffer.buffer[i] = 0;
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BX_SER_THIS mouse_internal_buffer.head = 0;
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BX_SER_THIS mouse_delayed_dx = 0;
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BX_SER_THIS mouse_delayed_dy = 0;
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2001-04-10 05:04:59 +04:00
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/*
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* Put the UART registers into their RESET state
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*/
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2005-01-19 21:21:40 +03:00
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for (i=0; i<BX_N_SERIAL_PORTS; i++) {
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2003-10-30 00:00:04 +03:00
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if (bx_options.com[i].Oenabled->get ()) {
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sprintf(name, "Serial Port %d", i + 1);
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/* serial interrupt */
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BX_SER_THIS s[i].IRQ = 4 - (i & 1);
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if (i < 2) {
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DEV_register_irq(BX_SER_THIS s[i].IRQ, name);
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}
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/* internal state */
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BX_SER_THIS s[i].ls_ipending = 0;
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BX_SER_THIS s[i].ms_ipending = 0;
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BX_SER_THIS s[i].rx_ipending = 0;
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2003-11-09 03:14:43 +03:00
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BX_SER_THIS s[i].fifo_ipending = 0;
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2003-10-30 00:00:04 +03:00
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BX_SER_THIS s[i].ls_interrupt = 0;
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BX_SER_THIS s[i].ms_interrupt = 0;
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BX_SER_THIS s[i].rx_interrupt = 0;
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BX_SER_THIS s[i].tx_interrupt = 0;
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2003-11-09 03:14:43 +03:00
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BX_SER_THIS s[i].fifo_interrupt = 0;
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2003-10-30 00:00:04 +03:00
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if (BX_SER_THIS s[i].tx_timer_index == BX_NULL_TIMER_HANDLE) {
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BX_SER_THIS s[i].tx_timer_index =
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bx_pc_system.register_timer(this, tx_timer_handler, 0,
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0,0, "serial.tx"); // one-shot, inactive
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}
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2002-10-06 23:04:47 +04:00
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2003-10-30 00:00:04 +03:00
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if (BX_SER_THIS s[i].rx_timer_index == BX_NULL_TIMER_HANDLE) {
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BX_SER_THIS s[i].rx_timer_index =
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bx_pc_system.register_timer(this, rx_timer_handler, 0,
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0,0, "serial.rx"); // one-shot, inactive
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}
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2003-11-09 03:14:43 +03:00
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if (BX_SER_THIS s[i].fifo_timer_index == BX_NULL_TIMER_HANDLE) {
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BX_SER_THIS s[i].fifo_timer_index =
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bx_pc_system.register_timer(this, fifo_timer_handler, 0,
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0,0, "serial.fifo"); // one-shot, inactive
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}
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2003-10-30 00:00:04 +03:00
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BX_SER_THIS s[i].rx_pollstate = BX_SER_RXIDLE;
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/* int enable: b0000 0000 */
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BX_SER_THIS s[i].int_enable.rxdata_enable = 0;
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BX_SER_THIS s[i].int_enable.txhold_enable = 0;
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BX_SER_THIS s[i].int_enable.rxlstat_enable = 0;
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BX_SER_THIS s[i].int_enable.modstat_enable = 0;
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/* int ID: b0000 0001 */
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BX_SER_THIS s[i].int_ident.ipending = 1;
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BX_SER_THIS s[i].int_ident.int_ID = 0;
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/* FIFO control: b0000 0000 */
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BX_SER_THIS s[i].fifo_cntl.enable = 0;
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BX_SER_THIS s[i].fifo_cntl.rxtrigger = 0;
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2003-11-09 03:14:43 +03:00
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BX_SER_THIS s[i].rx_fifo_end = 0;
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BX_SER_THIS s[i].tx_fifo_end = 0;
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2003-10-30 00:00:04 +03:00
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/* Line Control reg: b0000 0000 */
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BX_SER_THIS s[i].line_cntl.wordlen_sel = 0;
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BX_SER_THIS s[i].line_cntl.stopbits = 0;
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BX_SER_THIS s[i].line_cntl.parity_enable = 0;
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BX_SER_THIS s[i].line_cntl.evenparity_sel = 0;
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BX_SER_THIS s[i].line_cntl.stick_parity = 0;
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BX_SER_THIS s[i].line_cntl.break_cntl = 0;
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BX_SER_THIS s[i].line_cntl.dlab = 0;
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/* Modem Control reg: b0000 0000 */
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BX_SER_THIS s[i].modem_cntl.dtr = 0;
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BX_SER_THIS s[i].modem_cntl.rts = 0;
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BX_SER_THIS s[i].modem_cntl.out1 = 0;
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BX_SER_THIS s[i].modem_cntl.out2 = 0;
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BX_SER_THIS s[i].modem_cntl.local_loopback = 0;
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/* Line Status register: b0110 0000 */
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BX_SER_THIS s[i].line_status.rxdata_ready = 0;
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BX_SER_THIS s[i].line_status.overrun_error = 0;
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BX_SER_THIS s[i].line_status.parity_error = 0;
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BX_SER_THIS s[i].line_status.framing_error = 0;
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BX_SER_THIS s[i].line_status.break_int = 0;
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BX_SER_THIS s[i].line_status.thr_empty = 1;
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BX_SER_THIS s[i].line_status.tsr_empty = 1;
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BX_SER_THIS s[i].line_status.fifo_error = 0;
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/* Modem Status register: bXXXX 0000 */
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BX_SER_THIS s[i].modem_status.delta_cts = 0;
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BX_SER_THIS s[i].modem_status.delta_dsr = 0;
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BX_SER_THIS s[i].modem_status.ri_trailedge = 0;
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BX_SER_THIS s[i].modem_status.delta_dcd = 0;
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BX_SER_THIS s[i].modem_status.cts = 0;
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BX_SER_THIS s[i].modem_status.dsr = 0;
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BX_SER_THIS s[i].modem_status.ri = 0;
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BX_SER_THIS s[i].modem_status.dcd = 0;
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BX_SER_THIS s[i].scratch = 0; /* scratch register */
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2003-10-31 20:23:56 +03:00
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BX_SER_THIS s[i].divisor_lsb = 1; /* divisor-lsb register */
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2003-10-30 00:00:04 +03:00
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BX_SER_THIS s[i].divisor_msb = 0; /* divisor-msb register */
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2003-10-31 20:23:56 +03:00
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BX_SER_THIS s[i].baudrate = 115200;
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2003-10-30 00:00:04 +03:00
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for (unsigned addr=ports[i]; addr<(unsigned)(ports[i]+8); addr++) {
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2005-01-02 13:42:15 +03:00
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BX_DEBUG(("com%d initialize register for read/write: 0x%04x",i+1, addr));
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2003-10-30 00:00:04 +03:00
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DEV_register_ioread_handler(this, read_handler, addr, name, 1);
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DEV_register_iowrite_handler(this, write_handler, addr, name, 1);
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}
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2004-07-28 23:36:42 +04:00
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BX_SER_THIS s[i].io_mode = BX_SER_MODE_NULL;
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char *mode = bx_options.com[i].Omode->get_choice(bx_options.com[i].Omode->get());
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if (!strcmp(mode, "file")) {
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if (strlen(bx_options.com[i].Odev->getptr ()) > 0) {
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BX_SER_THIS s[i].output = fopen(bx_options.com[i].Odev->getptr (), "wb");
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if (BX_SER_THIS s[i].output)
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BX_SER_THIS s[i].io_mode = BX_SER_MODE_FILE;
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}
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} else if (!strcmp(mode, "term")) {
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2005-07-10 20:51:09 +04:00
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#if defined(SERIAL_ENABLE) && !defined(WIN32)
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2004-07-28 23:36:42 +04:00
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if (strlen(bx_options.com[i].Odev->getptr ()) > 0) {
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BX_SER_THIS s[i].tty_id = open(bx_options.com[i].Odev->getptr (), O_RDWR|O_NONBLOCK,600);
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if (BX_SER_THIS s[i].tty_id < 0) {
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2005-07-10 20:51:09 +04:00
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BX_PANIC(("open of com%d (%s) failed", i+1, bx_options.com[i].Odev->getptr ()));
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2004-07-28 23:36:42 +04:00
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} else {
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BX_SER_THIS s[i].io_mode = BX_SER_MODE_TERM;
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BX_DEBUG(("com%d tty_id: %d", i+1, BX_SER_THIS s[i].tty_id));
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tcgetattr(BX_SER_THIS s[i].tty_id, &BX_SER_THIS s[i].term_orig);
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|
|
bcopy((caddr_t) &BX_SER_THIS s[i].term_orig, (caddr_t) &BX_SER_THIS s[i].term_new, sizeof(struct termios));
|
|
|
|
cfmakeraw(&BX_SER_THIS s[i].term_new);
|
|
|
|
BX_SER_THIS s[i].term_new.c_oflag |= OPOST | ONLCR; // Enable NL to CR-NL translation
|
2004-01-18 03:18:44 +03:00
|
|
|
#ifndef TRUE_CTLC
|
2004-07-28 23:36:42 +04:00
|
|
|
// ctl-C will exit Bochs, or trap to the debugger
|
|
|
|
BX_SER_THIS s[i].term_new.c_iflag &= ~IGNBRK;
|
|
|
|
BX_SER_THIS s[i].term_new.c_iflag |= BRKINT;
|
|
|
|
BX_SER_THIS s[i].term_new.c_lflag |= ISIG;
|
2004-01-18 03:18:44 +03:00
|
|
|
#else
|
2004-07-28 23:36:42 +04:00
|
|
|
// ctl-C will be delivered to the serial port
|
|
|
|
BX_SER_THIS s[i].term_new.c_iflag |= IGNBRK;
|
|
|
|
BX_SER_THIS s[i].term_new.c_iflag &= ~BRKINT;
|
2004-01-18 03:18:44 +03:00
|
|
|
#endif /* !def TRUE_CTLC */
|
2004-07-28 23:36:42 +04:00
|
|
|
BX_SER_THIS s[i].term_new.c_iflag = 0;
|
|
|
|
BX_SER_THIS s[i].term_new.c_oflag = 0;
|
|
|
|
BX_SER_THIS s[i].term_new.c_cflag = CS8|CREAD|CLOCAL;
|
|
|
|
BX_SER_THIS s[i].term_new.c_lflag = 0;
|
|
|
|
BX_SER_THIS s[i].term_new.c_cc[VMIN] = 1;
|
|
|
|
BX_SER_THIS s[i].term_new.c_cc[VTIME] = 0;
|
|
|
|
//BX_SER_THIS s[i].term_new.c_iflag |= IXOFF;
|
|
|
|
tcsetattr(BX_SER_THIS s[i].tty_id, TCSAFLUSH, &BX_SER_THIS s[i].term_new);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
BX_PANIC(("serial terminal support not available"));
|
2004-01-18 03:18:44 +03:00
|
|
|
#endif /* def SERIAL_ENABLE */
|
2004-07-28 23:36:42 +04:00
|
|
|
} else if (!strcmp(mode, "raw")) {
|
|
|
|
#if USE_RAW_SERIAL
|
|
|
|
BX_SER_THIS s[i].raw = new serial_raw(bx_options.com[i].Odev->getptr ());
|
|
|
|
BX_SER_THIS s[i].io_mode = BX_SER_MODE_RAW;
|
|
|
|
#else
|
|
|
|
BX_PANIC(("raw serial support not present"));
|
|
|
|
#endif
|
2004-11-27 13:09:41 +03:00
|
|
|
} else if (!strcmp(mode, "mouse")) {
|
|
|
|
BX_SER_THIS s[i].io_mode = BX_SER_MODE_MOUSE;
|
2004-12-03 00:34:26 +03:00
|
|
|
BX_SER_THIS mouse_port = i;
|
2005-07-10 20:51:09 +04:00
|
|
|
} else if (!strcmp(mode, "socket")) {
|
|
|
|
BX_SER_THIS s[i].io_mode = BX_SER_MODE_SOCKET;
|
|
|
|
struct sockaddr_in sin;
|
|
|
|
struct hostent *hp;
|
|
|
|
char host[BX_PATHNAME_LEN];
|
|
|
|
int port;
|
|
|
|
int socket;
|
|
|
|
|
|
|
|
#if defined(WIN32)
|
|
|
|
static bool winsock_init = false;
|
|
|
|
if (!winsock_init) {
|
|
|
|
WORD wVersionRequested;
|
|
|
|
WSADATA wsaData;
|
|
|
|
int err;
|
|
|
|
wVersionRequested = MAKEWORD (2, 0);
|
|
|
|
err = WSAStartup (wVersionRequested, &wsaData);
|
|
|
|
if (err != 0)
|
|
|
|
BX_PANIC (("WSAStartup failed"));
|
|
|
|
winsock_init = true;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
char *substr = strtok(bx_options.com[i].Odev->getptr(), ":");
|
|
|
|
strcpy(host, substr);
|
|
|
|
substr = strtok(NULL, ":");
|
|
|
|
if (!substr) {
|
|
|
|
BX_PANIC(("com%d: inet address is wrong (%s)", i+1,
|
|
|
|
bx_options.com[i].Odev->getptr ()));
|
|
|
|
}
|
|
|
|
port = atoi (substr);
|
|
|
|
|
|
|
|
hp = gethostbyname (host);
|
|
|
|
if (!hp) {
|
|
|
|
BX_PANIC(("com%d: gethostbyname failed (%s)", i+1, host));
|
|
|
|
}
|
|
|
|
|
|
|
|
memset ((char*) &sin, 0, sizeof (sin));
|
|
|
|
memcpy ((char*) &(sin.sin_addr), hp->h_addr, hp->h_length);
|
|
|
|
sin.sin_family = hp->h_addrtype;
|
|
|
|
sin.sin_port = htons (port);
|
|
|
|
|
|
|
|
socket = ::socket (AF_INET, SOCK_STREAM, 0);
|
|
|
|
if (socket < 0) {
|
|
|
|
BX_PANIC(("com%d: socket() failed",i+1));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (::connect (socket, (sockaddr *) &sin, sizeof (sin)) < 0) {
|
|
|
|
socket = -1;
|
|
|
|
BX_INFO(("com%d: connect() failed (host:%s, port:%d)",i+1, host, port));
|
|
|
|
} else {
|
|
|
|
BX_INFO(("com%d - inet - socket_id: %d, ip:%s, port:%d", i+1, socket, host, port));
|
|
|
|
}
|
|
|
|
BX_SER_THIS s[i].socket_id = socket;
|
2004-07-28 23:36:42 +04:00
|
|
|
} else if (strcmp(mode, "null")) {
|
|
|
|
BX_PANIC(("unknown serial i/o mode"));
|
|
|
|
}
|
|
|
|
// simulate device connected
|
|
|
|
if (BX_SER_THIS s[i].io_mode != BX_SER_MODE_RAW) {
|
|
|
|
BX_SER_THIS s[i].modem_status.cts = 1;
|
|
|
|
BX_SER_THIS s[i].modem_status.dsr = 1;
|
|
|
|
}
|
2003-10-30 00:00:04 +03:00
|
|
|
BX_INFO(("com%d at 0x%04x irq %d", i+1, ports[i], BX_SER_THIS s[i].IRQ));
|
2002-10-06 23:04:47 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2002-08-27 23:54:46 +04:00
|
|
|
void
|
|
|
|
bx_serial_c::reset(unsigned type)
|
|
|
|
{
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2003-10-30 00:00:04 +03:00
|
|
|
void
|
|
|
|
bx_serial_c::lower_interrupt(Bit8u port)
|
|
|
|
{
|
|
|
|
/* If there are no more ints pending, clear the irq */
|
|
|
|
if ((BX_SER_THIS s[port].rx_interrupt == 0) &&
|
|
|
|
(BX_SER_THIS s[port].tx_interrupt == 0) &&
|
|
|
|
(BX_SER_THIS s[port].ls_interrupt == 0) &&
|
2003-11-09 03:14:43 +03:00
|
|
|
(BX_SER_THIS s[port].ms_interrupt == 0) &&
|
|
|
|
(BX_SER_THIS s[port].fifo_interrupt == 0)) {
|
2003-10-30 00:00:04 +03:00
|
|
|
DEV_pic_lower_irq(BX_SER_THIS s[port].IRQ);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2003-10-31 20:23:56 +03:00
|
|
|
void
|
|
|
|
bx_serial_c::raise_interrupt(Bit8u port, int type)
|
|
|
|
{
|
|
|
|
bx_bool gen_int = 0;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case BX_SER_INT_IER: /* IER has changed */
|
|
|
|
gen_int = 1;
|
|
|
|
break;
|
|
|
|
case BX_SER_INT_RXDATA:
|
|
|
|
if (BX_SER_THIS s[port].int_enable.rxdata_enable) {
|
|
|
|
BX_SER_THIS s[port].rx_interrupt = 1;
|
|
|
|
gen_int = 1;
|
|
|
|
} else {
|
|
|
|
BX_SER_THIS s[port].rx_ipending = 1;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case BX_SER_INT_TXHOLD:
|
|
|
|
if (BX_SER_THIS s[port].int_enable.txhold_enable) {
|
|
|
|
BX_SER_THIS s[port].tx_interrupt = 1;
|
|
|
|
gen_int = 1;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case BX_SER_INT_RXLSTAT:
|
|
|
|
if (BX_SER_THIS s[port].int_enable.rxlstat_enable) {
|
|
|
|
BX_SER_THIS s[port].ls_interrupt = 1;
|
|
|
|
gen_int = 1;
|
|
|
|
} else {
|
|
|
|
BX_SER_THIS s[port].ls_ipending = 1;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case BX_SER_INT_MODSTAT:
|
|
|
|
if ((BX_SER_THIS s[port].ms_ipending == 1) &&
|
|
|
|
(BX_SER_THIS s[port].int_enable.modstat_enable == 1)) {
|
|
|
|
BX_SER_THIS s[port].ms_interrupt = 1;
|
|
|
|
BX_SER_THIS s[port].ms_ipending = 0;
|
|
|
|
gen_int = 1;
|
|
|
|
}
|
|
|
|
break;
|
2003-11-09 03:14:43 +03:00
|
|
|
case BX_SER_INT_FIFO:
|
|
|
|
if (BX_SER_THIS s[port].int_enable.rxdata_enable) {
|
|
|
|
BX_SER_THIS s[port].fifo_interrupt = 1;
|
|
|
|
gen_int = 1;
|
|
|
|
} else {
|
|
|
|
BX_SER_THIS s[port].fifo_ipending = 1;
|
|
|
|
}
|
|
|
|
break;
|
2003-10-31 20:23:56 +03:00
|
|
|
}
|
|
|
|
if (gen_int && BX_SER_THIS s[port].modem_cntl.out2) {
|
|
|
|
DEV_pic_raise_irq(BX_SER_THIS s[port].IRQ);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2001-04-10 05:04:59 +04:00
|
|
|
// static IO port read callback handler
|
|
|
|
// redirects to non-static class handler to avoid virtual functions
|
|
|
|
|
|
|
|
Bit32u
|
|
|
|
bx_serial_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
|
|
|
|
{
|
|
|
|
#if !BX_USE_SER_SMF
|
|
|
|
bx_serial_c *class_ptr = (bx_serial_c *) this_ptr;
|
|
|
|
|
|
|
|
return( class_ptr->read(address, io_len) );
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
Bit32u
|
|
|
|
bx_serial_c::read(Bit32u address, unsigned io_len)
|
|
|
|
{
|
|
|
|
#else
|
|
|
|
UNUSED(this_ptr);
|
|
|
|
#endif // !BX_USE_SER_SMF
|
2004-03-09 00:51:19 +03:00
|
|
|
bx_bool prev_cts, prev_dsr, prev_ri, prev_dcd;
|
2004-01-17 18:51:09 +03:00
|
|
|
Bit8u offset, val;
|
|
|
|
Bit8u port = 0;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
offset = address & 0x07;
|
|
|
|
switch (address & 0x03f8) {
|
|
|
|
case 0x03f8: port = 0; break;
|
|
|
|
case 0x02f8: port = 1; break;
|
|
|
|
case 0x03e8: port = 2; break;
|
|
|
|
case 0x02e8: port = 3; break;
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
switch (offset) {
|
|
|
|
case BX_SER_RBR: /* receive buffer, or divisor latch LSB if DLAB set */
|
|
|
|
if (BX_SER_THIS s[port].line_cntl.dlab) {
|
|
|
|
val = BX_SER_THIS s[port].divisor_lsb;
|
2001-04-10 05:04:59 +04:00
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].fifo_cntl.enable) {
|
|
|
|
val = BX_SER_THIS s[port].rx_fifo[0];
|
|
|
|
if (BX_SER_THIS s[port].rx_fifo_end > 0) {
|
|
|
|
memcpy(&BX_SER_THIS s[port].rx_fifo[0], &BX_SER_THIS s[port].rx_fifo[1], 15);
|
|
|
|
BX_SER_THIS s[port].rx_fifo_end--;
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].rx_fifo_end == 0) {
|
|
|
|
BX_SER_THIS s[port].line_status.rxdata_ready = 0;
|
|
|
|
BX_SER_THIS s[port].rx_interrupt = 0;
|
|
|
|
BX_SER_THIS s[port].rx_ipending = 0;
|
|
|
|
BX_SER_THIS s[port].fifo_interrupt = 0;
|
|
|
|
BX_SER_THIS s[port].fifo_ipending = 0;
|
|
|
|
lower_interrupt(port);
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
val = BX_SER_THIS s[port].rxbuffer;
|
|
|
|
BX_SER_THIS s[port].line_status.rxdata_ready = 0;
|
|
|
|
BX_SER_THIS s[port].rx_interrupt = 0;
|
|
|
|
BX_SER_THIS s[port].rx_ipending = 0;
|
|
|
|
lower_interrupt(port);
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_IER: /* interrupt enable register, or div. latch MSB */
|
|
|
|
if (BX_SER_THIS s[port].line_cntl.dlab) {
|
|
|
|
val = BX_SER_THIS s[port].divisor_msb;
|
2001-04-10 05:04:59 +04:00
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
val = BX_SER_THIS s[port].int_enable.rxdata_enable |
|
|
|
|
(BX_SER_THIS s[port].int_enable.txhold_enable << 1) |
|
|
|
|
(BX_SER_THIS s[port].int_enable.rxlstat_enable << 2) |
|
|
|
|
(BX_SER_THIS s[port].int_enable.modstat_enable << 3);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_IIR: /* interrupt ID register */
|
2001-04-10 05:04:59 +04:00
|
|
|
/*
|
|
|
|
* Set the interrupt ID based on interrupt source
|
|
|
|
*/
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].ls_interrupt) {
|
|
|
|
BX_SER_THIS s[port].int_ident.int_ID = 0x3;
|
|
|
|
BX_SER_THIS s[port].int_ident.ipending = 0;
|
|
|
|
} else if (BX_SER_THIS s[port].fifo_interrupt) {
|
|
|
|
BX_SER_THIS s[port].int_ident.int_ID = 0x6;
|
|
|
|
BX_SER_THIS s[port].int_ident.ipending = 0;
|
|
|
|
} else if (BX_SER_THIS s[port].rx_interrupt) {
|
|
|
|
BX_SER_THIS s[port].int_ident.int_ID = 0x2;
|
|
|
|
BX_SER_THIS s[port].int_ident.ipending = 0;
|
|
|
|
} else if (BX_SER_THIS s[port].tx_interrupt) {
|
|
|
|
BX_SER_THIS s[port].int_ident.int_ID = 0x1;
|
|
|
|
BX_SER_THIS s[port].int_ident.ipending = 0;
|
|
|
|
} else if (BX_SER_THIS s[port].ms_interrupt) {
|
|
|
|
BX_SER_THIS s[port].int_ident.int_ID = 0x0;
|
|
|
|
BX_SER_THIS s[port].int_ident.ipending = 0;
|
2001-04-10 05:04:59 +04:00
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].int_ident.int_ID = 0x0;
|
|
|
|
BX_SER_THIS s[port].int_ident.ipending = 1;
|
2002-01-20 19:35:32 +03:00
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].tx_interrupt = 0;
|
|
|
|
lower_interrupt(port);
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
val = BX_SER_THIS s[port].int_ident.ipending |
|
|
|
|
(BX_SER_THIS s[port].int_ident.int_ID << 1) |
|
|
|
|
(BX_SER_THIS s[port].fifo_cntl.enable ? 0xc0 : 0x00);
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_LCR: /* Line control register */
|
2004-01-18 14:58:07 +03:00
|
|
|
val = BX_SER_THIS s[port].line_cntl.wordlen_sel |
|
|
|
|
(BX_SER_THIS s[port].line_cntl.stopbits << 2) |
|
|
|
|
(BX_SER_THIS s[port].line_cntl.parity_enable << 3) |
|
|
|
|
(BX_SER_THIS s[port].line_cntl.evenparity_sel << 4) |
|
|
|
|
(BX_SER_THIS s[port].line_cntl.stick_parity << 5) |
|
|
|
|
(BX_SER_THIS s[port].line_cntl.break_cntl << 6) |
|
|
|
|
(BX_SER_THIS s[port].line_cntl.dlab << 7);
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_MCR: /* MODEM control register */
|
|
|
|
val = BX_SER_THIS s[port].modem_cntl.dtr |
|
|
|
|
(BX_SER_THIS s[port].modem_cntl.rts << 1) |
|
|
|
|
(BX_SER_THIS s[port].modem_cntl.out1 << 2) |
|
|
|
|
(BX_SER_THIS s[port].modem_cntl.out2 << 3) |
|
|
|
|
(BX_SER_THIS s[port].modem_cntl.local_loopback << 4);
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_LSR: /* Line status register */
|
2004-01-18 14:58:07 +03:00
|
|
|
val = BX_SER_THIS s[port].line_status.rxdata_ready |
|
|
|
|
(BX_SER_THIS s[port].line_status.overrun_error << 1) |
|
|
|
|
(BX_SER_THIS s[port].line_status.parity_error << 2) |
|
|
|
|
(BX_SER_THIS s[port].line_status.framing_error << 3) |
|
|
|
|
(BX_SER_THIS s[port].line_status.break_int << 4) |
|
|
|
|
(BX_SER_THIS s[port].line_status.thr_empty << 5) |
|
|
|
|
(BX_SER_THIS s[port].line_status.tsr_empty << 6) |
|
|
|
|
(BX_SER_THIS s[port].line_status.fifo_error << 7);
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].line_status.overrun_error = 0;
|
2004-03-10 00:58:37 +03:00
|
|
|
BX_SER_THIS s[port].line_status.framing_error = 0;
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].line_status.break_int = 0;
|
|
|
|
BX_SER_THIS s[port].ls_interrupt = 0;
|
|
|
|
BX_SER_THIS s[port].ls_ipending = 0;
|
|
|
|
lower_interrupt(port);
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_MSR: /* MODEM status register */
|
2004-03-09 00:51:19 +03:00
|
|
|
prev_cts = BX_SER_THIS s[port].modem_status.cts;
|
|
|
|
prev_dsr = BX_SER_THIS s[port].modem_status.dsr;
|
|
|
|
prev_ri = BX_SER_THIS s[port].modem_status.ri;
|
|
|
|
prev_dcd = BX_SER_THIS s[port].modem_status.dcd;
|
2004-07-28 23:36:42 +04:00
|
|
|
if (BX_SER_THIS s[port].io_mode == BX_SER_MODE_RAW) {
|
2004-03-09 00:51:19 +03:00
|
|
|
#if USE_RAW_SERIAL
|
2004-07-28 23:36:42 +04:00
|
|
|
val = BX_SER_THIS s[port].raw->get_modem_status();
|
|
|
|
BX_SER_THIS s[port].modem_status.cts = (val & 0x10) >> 4;
|
|
|
|
BX_SER_THIS s[port].modem_status.dsr = (val & 0x20) >> 5;
|
|
|
|
BX_SER_THIS s[port].modem_status.ri = (val & 0x40) >> 6;
|
|
|
|
BX_SER_THIS s[port].modem_status.dcd = (val & 0x80) >> 7;
|
|
|
|
if (BX_SER_THIS s[port].modem_status.cts != prev_cts) {
|
|
|
|
BX_SER_THIS s[port].modem_status.delta_cts = 1;
|
|
|
|
}
|
|
|
|
if (BX_SER_THIS s[port].modem_status.dsr != prev_dsr) {
|
|
|
|
BX_SER_THIS s[port].modem_status.delta_dsr = 1;
|
|
|
|
}
|
|
|
|
if ((BX_SER_THIS s[port].modem_status.ri == 0) && (prev_ri == 1))
|
|
|
|
BX_SER_THIS s[port].modem_status.ri_trailedge = 1;
|
|
|
|
if (BX_SER_THIS s[port].modem_status.dcd != prev_dcd) {
|
|
|
|
BX_SER_THIS s[port].modem_status.delta_dcd = 1;
|
|
|
|
}
|
2004-03-09 00:51:19 +03:00
|
|
|
#endif
|
2004-07-28 23:36:42 +04:00
|
|
|
}
|
2004-01-18 14:58:07 +03:00
|
|
|
val = BX_SER_THIS s[port].modem_status.delta_cts |
|
|
|
|
(BX_SER_THIS s[port].modem_status.delta_dsr << 1) |
|
|
|
|
(BX_SER_THIS s[port].modem_status.ri_trailedge << 2) |
|
|
|
|
(BX_SER_THIS s[port].modem_status.delta_dcd << 3) |
|
|
|
|
(BX_SER_THIS s[port].modem_status.cts << 4) |
|
|
|
|
(BX_SER_THIS s[port].modem_status.dsr << 5) |
|
|
|
|
(BX_SER_THIS s[port].modem_status.ri << 6) |
|
|
|
|
(BX_SER_THIS s[port].modem_status.dcd << 7);
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].modem_status.delta_cts = 0;
|
|
|
|
BX_SER_THIS s[port].modem_status.delta_dsr = 0;
|
|
|
|
BX_SER_THIS s[port].modem_status.ri_trailedge = 0;
|
|
|
|
BX_SER_THIS s[port].modem_status.delta_dcd = 0;
|
|
|
|
BX_SER_THIS s[port].ms_interrupt = 0;
|
|
|
|
BX_SER_THIS s[port].ms_ipending = 0;
|
|
|
|
lower_interrupt(port);
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_SCR: /* scratch register */
|
|
|
|
val = BX_SER_THIS s[port].scratch;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
val = 0; // keep compiler happy
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_PANIC(("unsupported io read from address=0x%04x!", address));
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2005-01-02 13:42:15 +03:00
|
|
|
BX_DEBUG(("com%d register read from address: 0x%04x = 0x%02x", port+1, address, val));
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
return(val);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// static IO port write callback handler
|
|
|
|
// redirects to non-static class handler to avoid virtual functions
|
|
|
|
|
2001-06-19 21:52:46 +04:00
|
|
|
void
|
2001-04-10 05:04:59 +04:00
|
|
|
bx_serial_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
|
|
|
|
{
|
|
|
|
#if !BX_USE_SER_SMF
|
|
|
|
bx_serial_c *class_ptr = (bx_serial_c *) this_ptr;
|
|
|
|
|
|
|
|
class_ptr->write(address, value, io_len);
|
|
|
|
}
|
|
|
|
|
2001-06-19 21:52:46 +04:00
|
|
|
void
|
2001-04-10 05:04:59 +04:00
|
|
|
bx_serial_c::write(Bit32u address, Bit32u value, unsigned io_len)
|
|
|
|
{
|
|
|
|
#else
|
|
|
|
UNUSED(this_ptr);
|
|
|
|
#endif // !BX_USE_SER_SMF
|
2002-10-25 15:44:41 +04:00
|
|
|
bx_bool prev_cts, prev_dsr, prev_ri, prev_dcd;
|
2004-03-10 00:58:37 +03:00
|
|
|
bx_bool new_b0, new_b1, new_b2, new_b3;
|
|
|
|
bx_bool new_b4, new_b5, new_b6, new_b7;
|
2002-10-25 15:44:41 +04:00
|
|
|
bx_bool gen_int = 0;
|
2004-03-10 00:58:37 +03:00
|
|
|
Bit8u offset, new_wordlen;
|
2004-02-28 16:10:57 +03:00
|
|
|
#if USE_RAW_SERIAL
|
2004-09-06 01:09:46 +04:00
|
|
|
bx_bool mcr_changed = 0;
|
2004-02-28 16:10:57 +03:00
|
|
|
Bit8u p_mode;
|
|
|
|
#endif
|
2004-01-17 18:51:09 +03:00
|
|
|
Bit8u port = 0;
|
2002-01-20 19:35:32 +03:00
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
offset = address & 0x07;
|
|
|
|
switch (address & 0x03f8) {
|
|
|
|
case 0x03f8: port = 0; break;
|
|
|
|
case 0x02f8: port = 1; break;
|
|
|
|
case 0x03e8: port = 2; break;
|
|
|
|
case 0x02e8: port = 3; break;
|
|
|
|
}
|
2005-01-02 13:42:15 +03:00
|
|
|
|
|
|
|
BX_DEBUG(("com%d register write to address: 0x%04x = 0x%02x", port+1, address, value));
|
|
|
|
|
2004-03-10 00:58:37 +03:00
|
|
|
new_b0 = value & 0x01;
|
|
|
|
new_b1 = (value & 0x02) >> 1;
|
|
|
|
new_b2 = (value & 0x04) >> 2;
|
|
|
|
new_b3 = (value & 0x08) >> 3;
|
|
|
|
new_b4 = (value & 0x10) >> 4;
|
|
|
|
new_b5 = (value & 0x20) >> 5;
|
|
|
|
new_b6 = (value & 0x40) >> 6;
|
|
|
|
new_b7 = (value & 0x80) >> 7;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
switch (offset) {
|
|
|
|
case BX_SER_THR: /* transmit buffer, or divisor latch LSB if DLAB set */
|
|
|
|
if (BX_SER_THIS s[port].line_cntl.dlab) {
|
2004-01-18 14:58:07 +03:00
|
|
|
BX_SER_THIS s[port].divisor_lsb = value;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
if ((value != 0) || (BX_SER_THIS s[port].divisor_msb != 0)) {
|
2004-01-18 14:58:07 +03:00
|
|
|
BX_SER_THIS s[port].baudrate = (int) (BX_PC_CLOCK_XTL /
|
|
|
|
(16 * ((BX_SER_THIS s[port].divisor_msb << 8) |
|
|
|
|
BX_SER_THIS s[port].divisor_lsb)));
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
Bit8u bitmask = 0xff >> (3 - BX_SER_THIS s[port].line_cntl.wordlen_sel);
|
|
|
|
if (BX_SER_THIS s[port].line_status.thr_empty) {
|
|
|
|
if (BX_SER_THIS s[port].fifo_cntl.enable) {
|
|
|
|
BX_SER_THIS s[port].tx_fifo[BX_SER_THIS s[port].tx_fifo_end++] = value & bitmask;
|
2003-11-09 03:14:43 +03:00
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].thrbuffer = value & bitmask;
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].line_status.thr_empty = 0;
|
|
|
|
if (BX_SER_THIS s[port].line_status.tsr_empty) {
|
|
|
|
if (BX_SER_THIS s[port].fifo_cntl.enable) {
|
|
|
|
BX_SER_THIS s[port].tsrbuffer = BX_SER_THIS s[port].tx_fifo[0];
|
|
|
|
memcpy(&BX_SER_THIS s[port].tx_fifo[0], &BX_SER_THIS s[port].tx_fifo[1], 15);
|
|
|
|
BX_SER_THIS s[port].line_status.thr_empty = (--BX_SER_THIS s[port].tx_fifo_end == 0);
|
2003-11-09 03:14:43 +03:00
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].tsrbuffer = BX_SER_THIS s[port].thrbuffer;
|
|
|
|
BX_SER_THIS s[port].line_status.thr_empty = 1;
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].line_status.tsr_empty = 0;
|
|
|
|
raise_interrupt(port, BX_SER_INT_TXHOLD);
|
|
|
|
bx_pc_system.activate_timer(BX_SER_THIS s[port].tx_timer_index,
|
|
|
|
(int) (1000000.0 / BX_SER_THIS s[port].baudrate *
|
|
|
|
(BX_SER_THIS s[port].line_cntl.wordlen_sel + 5)),
|
2003-09-15 00:16:25 +04:00
|
|
|
0); /* not continuous */
|
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].tx_interrupt = 0;
|
|
|
|
lower_interrupt(port);
|
2003-09-15 00:16:25 +04:00
|
|
|
}
|
2002-01-20 19:35:32 +03:00
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].fifo_cntl.enable) {
|
|
|
|
if (BX_SER_THIS s[port].tx_fifo_end < 16) {
|
|
|
|
BX_SER_THIS s[port].tx_fifo[BX_SER_THIS s[port].tx_fifo_end++] = value & bitmask;
|
2003-11-09 03:14:43 +03:00
|
|
|
} else {
|
2004-01-25 16:01:29 +03:00
|
|
|
BX_ERROR(("com%d: transmit FIFO overflow", port+1));
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
|
|
|
} else {
|
2004-01-25 16:01:29 +03:00
|
|
|
BX_ERROR(("com%d: write to tx hold register when not empty", port+1));
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
2002-01-20 19:35:32 +03:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_IER: /* interrupt enable register, or div. latch MSB */
|
|
|
|
if (BX_SER_THIS s[port].line_cntl.dlab) {
|
2004-01-18 14:58:07 +03:00
|
|
|
BX_SER_THIS s[port].divisor_msb = value;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
if ((value != 0) || (BX_SER_THIS s[port].divisor_lsb != 0)) {
|
2004-01-18 14:58:07 +03:00
|
|
|
BX_SER_THIS s[port].baudrate = (int) (BX_PC_CLOCK_XTL /
|
|
|
|
(16 * ((BX_SER_THIS s[port].divisor_msb << 8) |
|
|
|
|
BX_SER_THIS s[port].divisor_lsb)));
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
} else {
|
2004-03-10 00:58:37 +03:00
|
|
|
if (new_b3 != BX_SER_THIS s[port].int_enable.modstat_enable) {
|
|
|
|
BX_SER_THIS s[port].int_enable.modstat_enable = new_b3;
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].int_enable.modstat_enable == 1) {
|
|
|
|
if (BX_SER_THIS s[port].ms_ipending == 1) {
|
|
|
|
BX_SER_THIS s[port].ms_interrupt = 1;
|
|
|
|
BX_SER_THIS s[port].ms_ipending = 0;
|
2003-10-30 00:00:04 +03:00
|
|
|
gen_int = 1;
|
|
|
|
}
|
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].ms_interrupt == 1) {
|
|
|
|
BX_SER_THIS s[port].ms_interrupt = 0;
|
|
|
|
BX_SER_THIS s[port].ms_ipending = 1;
|
|
|
|
lower_interrupt(port);
|
2003-10-30 00:00:04 +03:00
|
|
|
}
|
2003-10-28 21:40:00 +03:00
|
|
|
}
|
2002-01-20 19:35:32 +03:00
|
|
|
}
|
2004-03-10 00:58:37 +03:00
|
|
|
if (new_b1 != BX_SER_THIS s[port].int_enable.txhold_enable) {
|
|
|
|
BX_SER_THIS s[port].int_enable.txhold_enable = new_b1;
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].int_enable.txhold_enable == 1) {
|
|
|
|
BX_SER_THIS s[port].tx_interrupt = BX_SER_THIS s[port].line_status.thr_empty;
|
|
|
|
if (BX_SER_THIS s[port].tx_interrupt) gen_int = 1;
|
2003-10-28 21:40:00 +03:00
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].tx_interrupt = 0;
|
|
|
|
lower_interrupt(port);
|
2003-10-28 21:40:00 +03:00
|
|
|
}
|
2002-01-20 19:35:32 +03:00
|
|
|
}
|
2004-03-10 00:58:37 +03:00
|
|
|
if (new_b0 != BX_SER_THIS s[port].int_enable.rxdata_enable) {
|
|
|
|
BX_SER_THIS s[port].int_enable.rxdata_enable = new_b0;
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].int_enable.rxdata_enable == 1) {
|
|
|
|
if (BX_SER_THIS s[port].fifo_ipending == 1) {
|
|
|
|
BX_SER_THIS s[port].fifo_interrupt = 1;
|
|
|
|
BX_SER_THIS s[port].fifo_ipending = 0;
|
2003-11-09 03:14:43 +03:00
|
|
|
gen_int = 1;
|
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].rx_ipending == 1) {
|
|
|
|
BX_SER_THIS s[port].rx_interrupt = 1;
|
|
|
|
BX_SER_THIS s[port].rx_ipending = 0;
|
2003-10-30 00:00:04 +03:00
|
|
|
gen_int = 1;
|
|
|
|
}
|
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].rx_interrupt == 1) {
|
|
|
|
BX_SER_THIS s[port].rx_interrupt = 0;
|
|
|
|
BX_SER_THIS s[port].rx_ipending = 1;
|
|
|
|
lower_interrupt(port);
|
2003-10-30 00:00:04 +03:00
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].fifo_interrupt == 1) {
|
|
|
|
BX_SER_THIS s[port].fifo_interrupt = 0;
|
|
|
|
BX_SER_THIS s[port].fifo_ipending = 1;
|
|
|
|
lower_interrupt(port);
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
2003-10-28 21:40:00 +03:00
|
|
|
}
|
2002-01-20 19:35:32 +03:00
|
|
|
}
|
2004-03-10 00:58:37 +03:00
|
|
|
if (new_b2 != BX_SER_THIS s[port].int_enable.rxlstat_enable) {
|
|
|
|
BX_SER_THIS s[port].int_enable.rxlstat_enable = new_b2;
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].int_enable.rxlstat_enable == 1) {
|
|
|
|
if (BX_SER_THIS s[port].ls_ipending == 1) {
|
|
|
|
BX_SER_THIS s[port].ls_interrupt = 1;
|
|
|
|
BX_SER_THIS s[port].ls_ipending = 0;
|
2003-10-30 00:00:04 +03:00
|
|
|
gen_int = 1;
|
|
|
|
}
|
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].ls_interrupt == 1) {
|
|
|
|
BX_SER_THIS s[port].ls_interrupt = 0;
|
|
|
|
BX_SER_THIS s[port].ls_ipending = 1;
|
|
|
|
lower_interrupt(port);
|
2003-10-30 00:00:04 +03:00
|
|
|
}
|
2003-10-28 21:40:00 +03:00
|
|
|
}
|
2002-01-20 19:35:32 +03:00
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
if (gen_int) raise_interrupt(port, BX_SER_INT_IER);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_FCR: /* FIFO control register */
|
2004-03-10 00:58:37 +03:00
|
|
|
if (new_b0 && !BX_SER_THIS s[port].fifo_cntl.enable) {
|
2004-01-25 16:01:29 +03:00
|
|
|
BX_INFO(("com%d: FIFO enabled", port+1));
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].rx_fifo_end = 0;
|
|
|
|
BX_SER_THIS s[port].tx_fifo_end = 0;
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
2004-03-10 00:58:37 +03:00
|
|
|
BX_SER_THIS s[port].fifo_cntl.enable = new_b0;
|
|
|
|
if (new_b1) {
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].rx_fifo_end = 0;
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
2004-03-10 00:58:37 +03:00
|
|
|
if (new_b2) {
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].tx_fifo_end = 0;
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].fifo_cntl.rxtrigger = (value & 0xc0) >> 6;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_LCR: /* Line control register */
|
2004-02-28 16:10:57 +03:00
|
|
|
new_wordlen = value & 0x03;
|
2004-07-28 23:36:42 +04:00
|
|
|
if (BX_SER_THIS s[port].io_mode == BX_SER_MODE_RAW) {
|
2004-02-28 16:10:57 +03:00
|
|
|
#if USE_RAW_SERIAL
|
2004-07-28 23:36:42 +04:00
|
|
|
if (BX_SER_THIS s[port].line_cntl.wordlen_sel != new_wordlen) {
|
|
|
|
BX_SER_THIS s[port].raw->set_data_bits(new_wordlen + 5);
|
|
|
|
}
|
|
|
|
if (new_b2 != BX_SER_THIS s[port].line_cntl.stopbits) {
|
|
|
|
BX_SER_THIS s[port].raw->set_stop_bits(new_b2 ? 2 : 1);
|
|
|
|
}
|
|
|
|
if ((new_b3 != BX_SER_THIS s[port].line_cntl.parity_enable) ||
|
|
|
|
(new_b4 != BX_SER_THIS s[port].line_cntl.evenparity_sel) ||
|
|
|
|
(new_b5 != BX_SER_THIS s[port].line_cntl.stick_parity)) {
|
|
|
|
if (new_b3 == 0) {
|
|
|
|
p_mode = P_NONE;
|
|
|
|
} else {
|
|
|
|
p_mode = ((value & 0x30) >> 4) + 1;
|
|
|
|
}
|
|
|
|
BX_SER_THIS s[port].raw->set_parity_mode(p_mode);
|
|
|
|
}
|
|
|
|
if ((new_b6 != BX_SER_THIS s[port].line_cntl.break_cntl) &&
|
|
|
|
(!BX_SER_THIS s[port].modem_cntl.local_loopback)) {
|
|
|
|
BX_SER_THIS s[port].raw->set_break(new_b6);
|
2004-02-28 16:10:57 +03:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
#endif // USE_RAW_SERIAL
|
2004-07-28 23:36:42 +04:00
|
|
|
}
|
2004-02-28 16:10:57 +03:00
|
|
|
BX_SER_THIS s[port].line_cntl.wordlen_sel = new_wordlen;
|
2001-04-10 05:04:59 +04:00
|
|
|
/* These are ignored, but set them up so they can be read back */
|
2004-03-10 00:58:37 +03:00
|
|
|
BX_SER_THIS s[port].line_cntl.stopbits = new_b2;
|
|
|
|
BX_SER_THIS s[port].line_cntl.parity_enable = new_b3;
|
|
|
|
BX_SER_THIS s[port].line_cntl.evenparity_sel = new_b4;
|
|
|
|
BX_SER_THIS s[port].line_cntl.stick_parity = new_b5;
|
|
|
|
BX_SER_THIS s[port].line_cntl.break_cntl = new_b6;
|
|
|
|
if (BX_SER_THIS s[port].modem_cntl.local_loopback &&
|
|
|
|
BX_SER_THIS s[port].line_cntl.break_cntl) {
|
|
|
|
BX_SER_THIS s[port].line_status.break_int = 1;
|
|
|
|
BX_SER_THIS s[port].line_status.framing_error = 1;
|
|
|
|
rx_fifo_enq(port, 0x00);
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
/* used when doing future writes */
|
2004-03-10 00:58:37 +03:00
|
|
|
if (!new_b7 && BX_SER_THIS s[port].line_cntl.dlab) {
|
2004-01-18 14:58:07 +03:00
|
|
|
// Start the receive polling process if not already started
|
|
|
|
// and there is a valid baudrate.
|
|
|
|
if (BX_SER_THIS s[port].rx_pollstate == BX_SER_RXIDLE &&
|
|
|
|
BX_SER_THIS s[port].baudrate != 0) {
|
|
|
|
BX_SER_THIS s[port].rx_pollstate = BX_SER_RXPOLL;
|
|
|
|
bx_pc_system.activate_timer(BX_SER_THIS s[port].rx_timer_index,
|
|
|
|
(int) (1000000.0 / BX_SER_THIS s[port].baudrate *
|
|
|
|
(BX_SER_THIS s[port].line_cntl.wordlen_sel + 5)),
|
|
|
|
0); /* not continuous */
|
|
|
|
}
|
2004-07-28 23:36:42 +04:00
|
|
|
if (BX_SER_THIS s[port].io_mode == BX_SER_MODE_RAW) {
|
2004-02-28 16:10:57 +03:00
|
|
|
#if USE_RAW_SERIAL
|
2004-07-28 23:36:42 +04:00
|
|
|
BX_SER_THIS s[port].raw->set_baudrate(BX_SER_THIS s[port].baudrate);
|
2004-02-28 16:10:57 +03:00
|
|
|
#endif // USE_RAW_SERIAL
|
2004-07-28 23:36:42 +04:00
|
|
|
}
|
2004-01-25 16:01:29 +03:00
|
|
|
BX_DEBUG(("com%d: baud rate set - %d", port+1, BX_SER_THIS s[port].baudrate));
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
2004-03-10 00:58:37 +03:00
|
|
|
BX_SER_THIS s[port].line_cntl.dlab = new_b7;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
2002-01-20 19:35:32 +03:00
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_MCR: /* MODEM control register */
|
2004-12-03 00:34:26 +03:00
|
|
|
if ((BX_SER_THIS s[port].io_mode == BX_SER_MODE_MOUSE) &&
|
|
|
|
(BX_SER_THIS s[port].line_cntl.wordlen_sel == 2)) {
|
2004-12-05 23:23:39 +03:00
|
|
|
if (new_b0 && !new_b1) BX_SER_THIS detect_mouse = 1;
|
|
|
|
if (new_b0 && new_b1 && (BX_SER_THIS detect_mouse == 1)) BX_SER_THIS detect_mouse = 2;
|
2004-11-27 13:09:41 +03:00
|
|
|
}
|
2004-07-28 23:36:42 +04:00
|
|
|
if (BX_SER_THIS s[port].io_mode == BX_SER_MODE_RAW) {
|
2004-03-10 00:58:37 +03:00
|
|
|
#if USE_RAW_SERIAL
|
2004-07-28 23:36:42 +04:00
|
|
|
mcr_changed = (BX_SER_THIS s[port].modem_cntl.dtr != new_b0) |
|
|
|
|
(BX_SER_THIS s[port].modem_cntl.rts != new_b1);
|
2004-03-10 00:58:37 +03:00
|
|
|
#endif
|
2004-07-28 23:36:42 +04:00
|
|
|
}
|
2004-03-10 00:58:37 +03:00
|
|
|
BX_SER_THIS s[port].modem_cntl.dtr = new_b0;
|
|
|
|
BX_SER_THIS s[port].modem_cntl.rts = new_b1;
|
|
|
|
BX_SER_THIS s[port].modem_cntl.out1 = new_b2;
|
|
|
|
BX_SER_THIS s[port].modem_cntl.out2 = new_b3;
|
|
|
|
|
2004-03-10 01:17:33 +03:00
|
|
|
if (new_b4 != BX_SER_THIS s[port].modem_cntl.local_loopback) {
|
2004-03-10 00:58:37 +03:00
|
|
|
BX_SER_THIS s[port].modem_cntl.local_loopback = new_b4;
|
|
|
|
if (BX_SER_THIS s[port].modem_cntl.local_loopback) {
|
|
|
|
/* transition to loopback mode */
|
2004-07-28 23:36:42 +04:00
|
|
|
if (BX_SER_THIS s[port].io_mode == BX_SER_MODE_RAW) {
|
2004-03-10 00:58:37 +03:00
|
|
|
#if USE_RAW_SERIAL
|
2004-07-28 23:36:42 +04:00
|
|
|
if (BX_SER_THIS s[port].modem_cntl.dtr ||
|
|
|
|
BX_SER_THIS s[port].modem_cntl.rts) {
|
|
|
|
BX_SER_THIS s[port].raw->set_modem_control(0);
|
|
|
|
}
|
2004-03-10 00:58:37 +03:00
|
|
|
#endif
|
2004-07-28 23:36:42 +04:00
|
|
|
}
|
2004-03-10 00:58:37 +03:00
|
|
|
if (BX_SER_THIS s[port].line_cntl.break_cntl) {
|
2004-07-28 23:36:42 +04:00
|
|
|
if (BX_SER_THIS s[port].io_mode == BX_SER_MODE_RAW) {
|
2004-03-10 00:58:37 +03:00
|
|
|
#if USE_RAW_SERIAL
|
2004-07-28 23:36:42 +04:00
|
|
|
BX_SER_THIS s[port].raw->set_break(0);
|
2004-03-10 00:58:37 +03:00
|
|
|
#endif
|
2004-07-28 23:36:42 +04:00
|
|
|
}
|
2004-03-10 00:58:37 +03:00
|
|
|
BX_SER_THIS s[port].line_status.break_int = 1;
|
|
|
|
BX_SER_THIS s[port].line_status.framing_error = 1;
|
|
|
|
rx_fifo_enq(port, 0x00);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* transition to normal mode */
|
2004-07-28 23:36:42 +04:00
|
|
|
if (BX_SER_THIS s[port].io_mode == BX_SER_MODE_RAW) {
|
2004-03-10 00:58:37 +03:00
|
|
|
#if USE_RAW_SERIAL
|
2004-07-28 23:36:42 +04:00
|
|
|
mcr_changed = 1;
|
|
|
|
if (BX_SER_THIS s[port].line_cntl.break_cntl) {
|
|
|
|
BX_SER_THIS s[port].raw->set_break(0);
|
|
|
|
}
|
2004-03-10 00:58:37 +03:00
|
|
|
#endif
|
2004-07-28 23:36:42 +04:00
|
|
|
}
|
2004-03-10 00:58:37 +03:00
|
|
|
}
|
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
|
|
|
|
if (BX_SER_THIS s[port].modem_cntl.local_loopback) {
|
|
|
|
prev_cts = BX_SER_THIS s[port].modem_status.cts;
|
|
|
|
prev_dsr = BX_SER_THIS s[port].modem_status.dsr;
|
|
|
|
prev_ri = BX_SER_THIS s[port].modem_status.ri;
|
|
|
|
prev_dcd = BX_SER_THIS s[port].modem_status.dcd;
|
|
|
|
BX_SER_THIS s[port].modem_status.cts = BX_SER_THIS s[port].modem_cntl.rts;
|
|
|
|
BX_SER_THIS s[port].modem_status.dsr = BX_SER_THIS s[port].modem_cntl.dtr;
|
|
|
|
BX_SER_THIS s[port].modem_status.ri = BX_SER_THIS s[port].modem_cntl.out1;
|
|
|
|
BX_SER_THIS s[port].modem_status.dcd = BX_SER_THIS s[port].modem_cntl.out2;
|
|
|
|
if (BX_SER_THIS s[port].modem_status.cts != prev_cts) {
|
|
|
|
BX_SER_THIS s[port].modem_status.delta_cts = 1;
|
|
|
|
BX_SER_THIS s[port].ms_ipending = 1;
|
2002-01-20 19:35:32 +03:00
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].modem_status.dsr != prev_dsr) {
|
|
|
|
BX_SER_THIS s[port].modem_status.delta_dsr = 1;
|
|
|
|
BX_SER_THIS s[port].ms_ipending = 1;
|
2002-01-20 19:35:32 +03:00
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].modem_status.ri != prev_ri)
|
|
|
|
BX_SER_THIS s[port].ms_ipending = 1;
|
|
|
|
if ((BX_SER_THIS s[port].modem_status.ri == 0) && (prev_ri == 1))
|
|
|
|
BX_SER_THIS s[port].modem_status.ri_trailedge = 1;
|
|
|
|
if (BX_SER_THIS s[port].modem_status.dcd != prev_dcd) {
|
|
|
|
BX_SER_THIS s[port].modem_status.delta_dcd = 1;
|
|
|
|
BX_SER_THIS s[port].ms_ipending = 1;
|
2002-01-20 19:35:32 +03:00
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
raise_interrupt(port, BX_SER_INT_MODSTAT);
|
2001-04-10 05:04:59 +04:00
|
|
|
} else {
|
2004-11-27 13:09:41 +03:00
|
|
|
if (BX_SER_THIS s[port].io_mode == BX_SER_MODE_MOUSE) {
|
2004-12-05 23:23:39 +03:00
|
|
|
if (BX_SER_THIS detect_mouse == 2) {
|
2004-12-09 21:47:36 +03:00
|
|
|
if (bx_options.Omouse_type->get() == BX_MOUSE_TYPE_SERIAL) {
|
2004-12-08 00:06:35 +03:00
|
|
|
BX_SER_THIS mouse_internal_buffer.head = 0;
|
2004-12-05 23:23:39 +03:00
|
|
|
BX_SER_THIS mouse_internal_buffer.num_elements = 1;
|
|
|
|
BX_SER_THIS mouse_internal_buffer.buffer[0] = 'M';
|
|
|
|
}
|
2004-12-09 21:47:36 +03:00
|
|
|
if (bx_options.Omouse_type->get() == BX_MOUSE_TYPE_SERIAL_WHEEL) {
|
2004-12-08 00:06:35 +03:00
|
|
|
BX_SER_THIS mouse_internal_buffer.head = 0;
|
2004-12-05 23:23:39 +03:00
|
|
|
BX_SER_THIS mouse_internal_buffer.num_elements = 6;
|
|
|
|
BX_SER_THIS mouse_internal_buffer.buffer[0] = 'M';
|
|
|
|
BX_SER_THIS mouse_internal_buffer.buffer[1] = 'Z';
|
|
|
|
BX_SER_THIS mouse_internal_buffer.buffer[2] = '@';
|
|
|
|
BX_SER_THIS mouse_internal_buffer.buffer[3] = '\0';
|
|
|
|
BX_SER_THIS mouse_internal_buffer.buffer[4] = '\0';
|
|
|
|
BX_SER_THIS mouse_internal_buffer.buffer[5] = '\0';
|
|
|
|
}
|
|
|
|
BX_SER_THIS detect_mouse = 0;
|
|
|
|
}
|
2004-11-27 13:09:41 +03:00
|
|
|
}
|
2004-12-05 23:23:39 +03:00
|
|
|
|
2004-07-28 23:36:42 +04:00
|
|
|
if (BX_SER_THIS s[port].io_mode == BX_SER_MODE_RAW) {
|
2004-03-09 00:51:19 +03:00
|
|
|
#if USE_RAW_SERIAL
|
2004-07-28 23:36:42 +04:00
|
|
|
if (mcr_changed) {
|
|
|
|
BX_SER_THIS s[port].raw->set_modem_control(value & 0x03);
|
|
|
|
}
|
2004-03-09 00:51:19 +03:00
|
|
|
#endif
|
2004-07-28 23:36:42 +04:00
|
|
|
} else {
|
|
|
|
/* simulate device connected */
|
|
|
|
BX_SER_THIS s[port].modem_status.cts = 1;
|
|
|
|
BX_SER_THIS s[port].modem_status.dsr = 1;
|
|
|
|
BX_SER_THIS s[port].modem_status.ri = 0;
|
|
|
|
BX_SER_THIS s[port].modem_status.dcd = 0;
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_LSR: /* Line status register */
|
2004-01-25 16:01:29 +03:00
|
|
|
BX_ERROR(("com%d: write to line status register ignored", port+1));
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_MSR: /* MODEM status register */
|
2004-01-25 16:01:29 +03:00
|
|
|
BX_ERROR(("com%d: write to MODEM status register ignored", port+1));
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
case BX_SER_SCR: /* scratch register */
|
|
|
|
BX_SER_THIS s[port].scratch = value;
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2002-08-27 21:24:36 +04:00
|
|
|
BX_PANIC(("unsupported io write to address=0x%04x, value = 0x%02x!",
|
merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
|
|
|
(unsigned) address, (unsigned) value));
|
2001-04-10 05:04:59 +04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2003-11-09 03:14:43 +03:00
|
|
|
|
|
|
|
void
|
|
|
|
bx_serial_c::rx_fifo_enq(Bit8u port, Bit8u data)
|
|
|
|
{
|
|
|
|
bx_bool gen_int = 0;
|
|
|
|
|
|
|
|
if (BX_SER_THIS s[port].fifo_cntl.enable) {
|
|
|
|
if (BX_SER_THIS s[port].rx_fifo_end == 16) {
|
2004-01-25 16:01:29 +03:00
|
|
|
BX_ERROR(("com%d: receive FIFO overflow", port+1));
|
2003-11-09 03:14:43 +03:00
|
|
|
BX_SER_THIS s[port].line_status.overrun_error = 1;
|
|
|
|
raise_interrupt(port, BX_SER_INT_RXLSTAT);
|
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].rx_fifo[BX_SER_THIS s[port].rx_fifo_end++] = data;
|
2003-11-09 03:14:43 +03:00
|
|
|
switch (BX_SER_THIS s[port].fifo_cntl.rxtrigger) {
|
|
|
|
case 1:
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].rx_fifo_end == 4) gen_int = 1;
|
2003-11-09 03:14:43 +03:00
|
|
|
break;
|
|
|
|
case 2:
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].rx_fifo_end == 8) gen_int = 1;
|
2003-11-09 03:14:43 +03:00
|
|
|
break;
|
|
|
|
case 3:
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].rx_fifo_end == 14) gen_int = 1;
|
2003-11-09 03:14:43 +03:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
gen_int = 1;
|
|
|
|
}
|
|
|
|
if (gen_int) {
|
2004-01-17 18:51:09 +03:00
|
|
|
bx_pc_system.deactivate_timer(BX_SER_THIS s[port].fifo_timer_index);
|
2003-11-09 03:14:43 +03:00
|
|
|
BX_SER_THIS s[port].line_status.rxdata_ready = 1;
|
|
|
|
raise_interrupt(port, BX_SER_INT_RXDATA);
|
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
bx_pc_system.activate_timer(BX_SER_THIS s[port].fifo_timer_index,
|
|
|
|
(int) (1000000.0 / BX_SER_THIS s[port].baudrate *
|
|
|
|
(BX_SER_THIS s[port].line_cntl.wordlen_sel + 5) * 16),
|
2003-11-09 03:14:43 +03:00
|
|
|
0); /* not continuous */
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (BX_SER_THIS s[port].line_status.rxdata_ready == 1) {
|
2004-01-25 16:01:29 +03:00
|
|
|
BX_ERROR(("com%d: overrun error", port+1));
|
2003-11-09 03:14:43 +03:00
|
|
|
BX_SER_THIS s[port].line_status.overrun_error = 1;
|
|
|
|
raise_interrupt(port, BX_SER_INT_RXLSTAT);
|
|
|
|
}
|
|
|
|
BX_SER_THIS s[port].rxbuffer = data;
|
|
|
|
BX_SER_THIS s[port].line_status.rxdata_ready = 1;
|
|
|
|
raise_interrupt(port, BX_SER_INT_RXDATA);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2001-04-10 05:04:59 +04:00
|
|
|
void
|
|
|
|
bx_serial_c::tx_timer_handler(void *this_ptr)
|
|
|
|
{
|
|
|
|
bx_serial_c *class_ptr = (bx_serial_c *) this_ptr;
|
|
|
|
|
|
|
|
class_ptr->tx_timer();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
bx_serial_c::tx_timer(void)
|
|
|
|
{
|
2003-11-09 03:14:43 +03:00
|
|
|
bx_bool gen_int = 0;
|
2004-01-17 18:51:09 +03:00
|
|
|
Bit8u port = 0;
|
|
|
|
int timer_id;
|
|
|
|
|
|
|
|
timer_id = bx_pc_system.triggeredTimerID();
|
|
|
|
if (timer_id == BX_SER_THIS s[0].tx_timer_index) {
|
|
|
|
port = 0;
|
|
|
|
} else if (timer_id == BX_SER_THIS s[1].tx_timer_index) {
|
|
|
|
port = 1;
|
|
|
|
} else if (timer_id == BX_SER_THIS s[2].tx_timer_index) {
|
|
|
|
port = 2;
|
|
|
|
} else if (timer_id == BX_SER_THIS s[3].tx_timer_index) {
|
|
|
|
port = 3;
|
|
|
|
}
|
2004-12-05 23:23:39 +03:00
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
if (BX_SER_THIS s[port].modem_cntl.local_loopback) {
|
2004-01-18 03:18:44 +03:00
|
|
|
rx_fifo_enq(port, BX_SER_THIS s[port].tsrbuffer);
|
2001-04-10 05:04:59 +04:00
|
|
|
} else {
|
2004-07-28 23:36:42 +04:00
|
|
|
switch (BX_SER_THIS s[port].io_mode) {
|
|
|
|
case BX_SER_MODE_FILE:
|
|
|
|
fputc(BX_SER_THIS s[port].tsrbuffer, BX_SER_THIS s[port].output);
|
|
|
|
fflush(BX_SER_THIS s[port].output);
|
|
|
|
break;
|
|
|
|
case BX_SER_MODE_TERM:
|
|
|
|
#if defined(SERIAL_ENABLE)
|
|
|
|
BX_DEBUG(("com%d: write: '%c'", port+1, BX_SER_THIS s[port].tsrbuffer));
|
|
|
|
if (BX_SER_THIS s[port].tty_id >= 0) {
|
|
|
|
write(BX_SER_THIS s[port].tty_id, (bx_ptr_t) & BX_SER_THIS s[port].tsrbuffer, 1);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
break;
|
|
|
|
case BX_SER_MODE_RAW:
|
2003-10-12 14:51:58 +04:00
|
|
|
#if USE_RAW_SERIAL
|
2004-07-28 23:36:42 +04:00
|
|
|
if (!BX_SER_THIS s[port].raw->ready_transmit())
|
|
|
|
BX_PANIC(("com%d: not ready to transmit", port+1));
|
|
|
|
BX_SER_THIS s[port].raw->transmit(BX_SER_THIS s[port].tsrbuffer);
|
2001-04-10 05:04:59 +04:00
|
|
|
#endif
|
2004-07-28 23:36:42 +04:00
|
|
|
break;
|
2004-11-27 13:09:41 +03:00
|
|
|
case BX_SER_MODE_MOUSE:
|
|
|
|
BX_INFO(("com%d: write to mouse ignored: 0x%02x", port+1, BX_SER_THIS s[port].tsrbuffer));
|
|
|
|
break;
|
2005-07-10 20:51:09 +04:00
|
|
|
case BX_SER_MODE_SOCKET:
|
|
|
|
if (BX_SER_THIS s[port].socket_id >= 0) {
|
|
|
|
#ifdef WIN32
|
|
|
|
BX_INFO(("attempting to write win32 : %c", BX_SER_THIS s[port].tsrbuffer));
|
|
|
|
::send(BX_SER_THIS s[port].socket_id,
|
|
|
|
(const char*) & BX_SER_THIS s[port].tsrbuffer, 1, 0);
|
|
|
|
#else
|
|
|
|
::write(BX_SER_THIS s[port].socket_id,
|
|
|
|
(bx_ptr_t) & BX_SER_THIS s[port].tsrbuffer, 1);
|
|
|
|
#endif
|
|
|
|
}
|
2004-07-28 23:36:42 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].line_status.tsr_empty = 1;
|
|
|
|
if (BX_SER_THIS s[port].fifo_cntl.enable && (BX_SER_THIS s[port].tx_fifo_end > 0)) {
|
|
|
|
BX_SER_THIS s[port].tsrbuffer = BX_SER_THIS s[port].tx_fifo[0];
|
|
|
|
BX_SER_THIS s[port].line_status.tsr_empty = 0;
|
|
|
|
memcpy(&BX_SER_THIS s[port].tx_fifo[0], &BX_SER_THIS s[port].tx_fifo[1], 15);
|
|
|
|
gen_int = (--BX_SER_THIS s[port].tx_fifo_end == 0);
|
|
|
|
} else if (!BX_SER_THIS s[port].line_status.thr_empty) {
|
|
|
|
BX_SER_THIS s[port].tsrbuffer = BX_SER_THIS s[port].thrbuffer;
|
|
|
|
BX_SER_THIS s[port].line_status.tsr_empty = 0;
|
2003-11-09 03:14:43 +03:00
|
|
|
gen_int = 1;
|
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
if (!BX_SER_THIS s[port].line_status.tsr_empty) {
|
2003-11-09 03:14:43 +03:00
|
|
|
if (gen_int) {
|
2004-01-17 18:51:09 +03:00
|
|
|
BX_SER_THIS s[port].line_status.thr_empty = 1;
|
|
|
|
raise_interrupt(port, BX_SER_INT_TXHOLD);
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
bx_pc_system.activate_timer(BX_SER_THIS s[port].tx_timer_index,
|
|
|
|
(int) (1000000.0 / BX_SER_THIS s[port].baudrate *
|
|
|
|
(BX_SER_THIS s[port].line_cntl.wordlen_sel + 5)),
|
2003-09-15 00:16:25 +04:00
|
|
|
0); /* not continuous */
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
bx_serial_c::rx_timer_handler(void *this_ptr)
|
|
|
|
{
|
|
|
|
bx_serial_c *class_ptr = (bx_serial_c *) this_ptr;
|
|
|
|
|
|
|
|
class_ptr->rx_timer();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
bx_serial_c::rx_timer(void)
|
|
|
|
{
|
2004-03-13 20:17:16 +03:00
|
|
|
#if BX_HAVE_SELECT && defined(SERIAL_ENABLE)
|
2001-06-10 05:35:10 +04:00
|
|
|
struct timeval tval;
|
2001-04-10 05:04:59 +04:00
|
|
|
fd_set fds;
|
|
|
|
#endif
|
2004-01-17 18:51:09 +03:00
|
|
|
Bit8u port = 0;
|
|
|
|
int timer_id;
|
2004-07-28 23:36:42 +04:00
|
|
|
bx_bool data_ready = 0;
|
2004-01-17 18:51:09 +03:00
|
|
|
|
|
|
|
timer_id = bx_pc_system.triggeredTimerID();
|
|
|
|
if (timer_id == BX_SER_THIS s[0].rx_timer_index) {
|
|
|
|
port = 0;
|
|
|
|
} else if (timer_id == BX_SER_THIS s[1].rx_timer_index) {
|
|
|
|
port = 1;
|
|
|
|
} else if (timer_id == BX_SER_THIS s[2].rx_timer_index) {
|
|
|
|
port = 2;
|
|
|
|
} else if (timer_id == BX_SER_THIS s[3].rx_timer_index) {
|
|
|
|
port = 3;
|
|
|
|
}
|
2004-12-05 23:23:39 +03:00
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
int bdrate = BX_SER_THIS s[port].baudrate / (BX_SER_THIS s[port].line_cntl.wordlen_sel + 5);
|
2001-05-23 11:48:11 +04:00
|
|
|
unsigned char chbuf = 0;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-07-28 23:36:42 +04:00
|
|
|
if (BX_SER_THIS s[port].io_mode == BX_SER_MODE_TERM) {
|
2004-03-13 20:17:16 +03:00
|
|
|
#if BX_HAVE_SELECT && defined(SERIAL_ENABLE)
|
2004-07-28 23:36:42 +04:00
|
|
|
tval.tv_sec = 0;
|
|
|
|
tval.tv_usec = 0;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
// MacOS: I'm not sure what to do with this, since I don't know
|
|
|
|
// what an fd_set is or what FD_SET() or select() do. They aren't
|
|
|
|
// declared in the CodeWarrior standard library headers. I'm just
|
|
|
|
// leaving it commented out for the moment.
|
|
|
|
|
2004-07-28 23:36:42 +04:00
|
|
|
FD_ZERO(&fds);
|
|
|
|
if (BX_SER_THIS s[port].tty_id >= 0) FD_SET(BX_SER_THIS s[port].tty_id, &fds);
|
2004-03-13 20:17:16 +03:00
|
|
|
#endif
|
2004-07-28 23:36:42 +04:00
|
|
|
}
|
2004-01-17 18:51:09 +03:00
|
|
|
if ((BX_SER_THIS s[port].line_status.rxdata_ready == 0) ||
|
|
|
|
(BX_SER_THIS s[port].fifo_cntl.enable)) {
|
2004-11-27 13:09:41 +03:00
|
|
|
switch (BX_SER_THIS s[port].io_mode) {
|
2005-07-10 20:51:09 +04:00
|
|
|
case BX_SER_MODE_SOCKET:
|
|
|
|
#if defined(SERIAL_ENABLE)
|
|
|
|
if (BX_SER_THIS s[port].line_status.rxdata_ready == 0) {
|
|
|
|
tval.tv_sec = 0;
|
|
|
|
tval.tv_usec = 0;
|
|
|
|
FD_ZERO(&fds);
|
|
|
|
int socketid = BX_SER_THIS s[port].socket_id;
|
|
|
|
if (socketid >= 0) FD_SET(socketid, &fds);
|
|
|
|
if ((socketid >= 0) && (select(socketid+1, &fds, NULL, NULL, &tval) == 1)) {
|
|
|
|
#ifdef WIN32
|
|
|
|
(void) ::recv(socketid, (char*) &chbuf, 1, 0);
|
|
|
|
#else
|
|
|
|
(void) read(socketid, &chbuf, 1);
|
|
|
|
#endif
|
|
|
|
BX_INFO((" -- COM %d : read byte [%d]", port+1, chbuf));
|
|
|
|
data_ready = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
break;
|
2004-11-27 13:09:41 +03:00
|
|
|
case BX_SER_MODE_RAW:
|
2003-10-12 14:51:58 +04:00
|
|
|
#if USE_RAW_SERIAL
|
2004-11-27 13:09:41 +03:00
|
|
|
int data;
|
|
|
|
if ((data_ready = BX_SER_THIS s[port].raw->ready_receive())) {
|
|
|
|
data = BX_SER_THIS s[port].raw->receive();
|
|
|
|
if (data < 0 ) {
|
|
|
|
data_ready = 0;
|
|
|
|
switch (data) {
|
|
|
|
case RAW_EVENT_BREAK:
|
|
|
|
BX_SER_THIS s[port].line_status.break_int = 1;
|
|
|
|
raise_interrupt(port, BX_SER_INT_RXLSTAT);
|
|
|
|
break;
|
|
|
|
case RAW_EVENT_FRAME:
|
|
|
|
BX_SER_THIS s[port].line_status.framing_error = 1;
|
|
|
|
raise_interrupt(port, BX_SER_INT_RXLSTAT);
|
|
|
|
break;
|
|
|
|
case RAW_EVENT_OVERRUN:
|
|
|
|
BX_SER_THIS s[port].line_status.overrun_error = 1;
|
|
|
|
raise_interrupt(port, BX_SER_INT_RXLSTAT);
|
|
|
|
break;
|
|
|
|
case RAW_EVENT_PARITY:
|
|
|
|
BX_SER_THIS s[port].line_status.parity_error = 1;
|
|
|
|
raise_interrupt(port, BX_SER_INT_RXLSTAT);
|
|
|
|
break;
|
|
|
|
case RAW_EVENT_CTS_ON:
|
|
|
|
case RAW_EVENT_CTS_OFF:
|
|
|
|
case RAW_EVENT_DSR_ON:
|
|
|
|
case RAW_EVENT_DSR_OFF:
|
|
|
|
case RAW_EVENT_RING_ON:
|
|
|
|
case RAW_EVENT_RING_OFF:
|
|
|
|
case RAW_EVENT_RLSD_ON:
|
|
|
|
case RAW_EVENT_RLSD_OFF:
|
|
|
|
raise_interrupt(port, BX_SER_INT_MODSTAT);
|
|
|
|
break;
|
|
|
|
}
|
2004-07-28 23:36:42 +04:00
|
|
|
}
|
2004-03-28 16:41:12 +04:00
|
|
|
}
|
2004-11-27 13:09:41 +03:00
|
|
|
if (data_ready) {
|
|
|
|
chbuf = data;
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
#endif
|
2004-11-27 13:09:41 +03:00
|
|
|
break;
|
|
|
|
case BX_SER_MODE_TERM:
|
2004-07-28 23:36:42 +04:00
|
|
|
#if BX_HAVE_SELECT && defined(SERIAL_ENABLE)
|
2004-11-27 13:09:41 +03:00
|
|
|
if ((BX_SER_THIS s[port].tty_id >= 0) && (select(BX_SER_THIS s[port].tty_id + 1, &fds, NULL, NULL, &tval) == 1)) {
|
|
|
|
(void) read(BX_SER_THIS s[port].tty_id, &chbuf, 1);
|
|
|
|
BX_DEBUG(("com%d: read: '%c'", port+1, chbuf));
|
|
|
|
data_ready = 1;
|
|
|
|
}
|
2004-07-28 23:36:42 +04:00
|
|
|
#endif
|
2004-11-27 13:09:41 +03:00
|
|
|
break;
|
|
|
|
case BX_SER_MODE_MOUSE:
|
2004-12-03 00:34:26 +03:00
|
|
|
if (BX_SER_THIS mouse_internal_buffer.num_elements > 0) {
|
|
|
|
chbuf = BX_SER_THIS mouse_internal_buffer.buffer[BX_SER_THIS mouse_internal_buffer.head];
|
|
|
|
BX_SER_THIS mouse_internal_buffer.head = (BX_SER_THIS mouse_internal_buffer.head + 1) %
|
|
|
|
BX_MOUSE_BUFF_SIZE;
|
|
|
|
BX_SER_THIS mouse_internal_buffer.num_elements--;
|
|
|
|
data_ready = 1;
|
|
|
|
}
|
2004-11-27 13:09:41 +03:00
|
|
|
break;
|
2004-07-28 23:36:42 +04:00
|
|
|
}
|
|
|
|
if (data_ready) {
|
2004-01-17 18:51:09 +03:00
|
|
|
if (!BX_SER_THIS s[port].modem_cntl.local_loopback) {
|
2004-01-18 03:18:44 +03:00
|
|
|
rx_fifo_enq(port, chbuf);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
} else {
|
2004-01-17 18:51:09 +03:00
|
|
|
if (!BX_SER_THIS s[port].fifo_cntl.enable) {
|
2003-11-09 03:14:43 +03:00
|
|
|
bdrate = (int) (1000000.0 / 100000); // Poll frequency is 100ms
|
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// Poll at 4x baud rate to see if the next-char can
|
|
|
|
// be read
|
2002-01-20 19:35:32 +03:00
|
|
|
bdrate *= 4;
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2004-01-17 18:51:09 +03:00
|
|
|
bx_pc_system.activate_timer(BX_SER_THIS s[port].rx_timer_index,
|
2004-01-18 14:58:07 +03:00
|
|
|
(int) (1000000.0 / bdrate),
|
|
|
|
0); /* not continuous */
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
2003-11-09 03:14:43 +03:00
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
bx_serial_c::fifo_timer_handler(void *this_ptr)
|
|
|
|
{
|
|
|
|
bx_serial_c *class_ptr = (bx_serial_c *) this_ptr;
|
|
|
|
|
|
|
|
class_ptr->fifo_timer();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
bx_serial_c::fifo_timer(void)
|
|
|
|
{
|
2004-01-17 18:51:09 +03:00
|
|
|
Bit8u port = 0;
|
|
|
|
int timer_id;
|
|
|
|
|
|
|
|
timer_id = bx_pc_system.triggeredTimerID();
|
|
|
|
if (timer_id == BX_SER_THIS s[0].fifo_timer_index) {
|
|
|
|
port = 0;
|
|
|
|
} else if (timer_id == BX_SER_THIS s[1].fifo_timer_index) {
|
|
|
|
port = 1;
|
|
|
|
} else if (timer_id == BX_SER_THIS s[2].fifo_timer_index) {
|
|
|
|
port = 2;
|
|
|
|
} else if (timer_id == BX_SER_THIS s[3].fifo_timer_index) {
|
|
|
|
port = 3;
|
|
|
|
}
|
|
|
|
BX_SER_THIS s[port].line_status.rxdata_ready = 1;
|
|
|
|
raise_interrupt(port, BX_SER_INT_FIFO);
|
2003-11-09 03:14:43 +03:00
|
|
|
}
|
2004-12-03 00:34:26 +03:00
|
|
|
|
|
|
|
|
|
|
|
void
|
2004-12-05 23:23:39 +03:00
|
|
|
bx_serial_c::serial_mouse_enq(int delta_x, int delta_y, int delta_z, unsigned button_state)
|
2004-12-03 00:34:26 +03:00
|
|
|
{
|
2004-12-05 23:23:39 +03:00
|
|
|
Bit8u b1, b2, b3, mouse_data[4];
|
2004-12-03 00:34:26 +03:00
|
|
|
int tail;
|
|
|
|
|
|
|
|
if (BX_SER_THIS mouse_port == -1) {
|
|
|
|
BX_ERROR(("mouse not connected to a serial port"));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2004-12-08 00:06:35 +03:00
|
|
|
// if the DTR and RTS lines aren't up, the mouse doesn't have any power to send packets.
|
|
|
|
if (!BX_SER_THIS s[BX_SER_THIS mouse_port].modem_cntl.dtr || !BX_SER_THIS s[BX_SER_THIS mouse_port].modem_cntl.rts)
|
|
|
|
return;
|
|
|
|
|
2004-12-03 00:34:26 +03:00
|
|
|
// scale down the motion
|
|
|
|
if ( (delta_x < -1) || (delta_x > 1) )
|
|
|
|
delta_x /= 2;
|
|
|
|
if ( (delta_y < -1) || (delta_y > 1) )
|
|
|
|
delta_y /= 2;
|
|
|
|
|
|
|
|
if(delta_x>127) delta_x=127;
|
|
|
|
if(delta_y>127) delta_y=127;
|
|
|
|
if(delta_x<-128) delta_x=-128;
|
|
|
|
if(delta_y<-128) delta_y=-128;
|
|
|
|
|
|
|
|
BX_SER_THIS mouse_delayed_dx+=delta_x;
|
|
|
|
BX_SER_THIS mouse_delayed_dy-=delta_y;
|
2004-12-08 00:06:35 +03:00
|
|
|
BX_SER_THIS mouse_delayed_dz =delta_z;
|
2004-12-03 00:34:26 +03:00
|
|
|
|
2004-12-08 00:06:35 +03:00
|
|
|
if ((BX_SER_THIS mouse_internal_buffer.num_elements + 4) >= BX_MOUSE_BUFF_SIZE) {
|
2004-12-03 00:34:26 +03:00
|
|
|
return; /* buffer doesn't have the space */
|
|
|
|
}
|
|
|
|
|
|
|
|
if (BX_SER_THIS mouse_delayed_dx > 127) {
|
|
|
|
delta_x = 127;
|
|
|
|
BX_SER_THIS mouse_delayed_dx -= 127;
|
|
|
|
} else if (BX_SER_THIS mouse_delayed_dx < -128) {
|
|
|
|
delta_x = -128;
|
|
|
|
BX_SER_THIS mouse_delayed_dx += 128;
|
|
|
|
} else {
|
|
|
|
delta_x = BX_SER_THIS mouse_delayed_dx;
|
|
|
|
BX_SER_THIS mouse_delayed_dx = 0;
|
|
|
|
}
|
|
|
|
if (BX_SER_THIS mouse_delayed_dy > 127) {
|
|
|
|
delta_y = 127;
|
|
|
|
BX_SER_THIS mouse_delayed_dy -= 127;
|
|
|
|
} else if (BX_SER_THIS mouse_delayed_dy < -128) {
|
|
|
|
delta_y = -128;
|
|
|
|
BX_SER_THIS mouse_delayed_dy += 128;
|
|
|
|
} else {
|
|
|
|
delta_y = BX_SER_THIS mouse_delayed_dy;
|
|
|
|
BX_SER_THIS mouse_delayed_dy = 0;
|
|
|
|
}
|
|
|
|
|
2004-12-08 00:06:35 +03:00
|
|
|
b1 = (Bit8u) delta_x;
|
|
|
|
b2 = (Bit8u) delta_y;
|
|
|
|
b3 = (Bit8u) -((Bit8s) delta_z);
|
|
|
|
|
2004-12-03 00:34:26 +03:00
|
|
|
mouse_data[0] = 0x40 | ((b1 & 0xc0) >> 6) | ((b2 & 0xc0) >> 4);
|
|
|
|
mouse_data[0] |= ((button_state & 0x01) << 5) | ((button_state & 0x02) << 3);
|
|
|
|
mouse_data[1] = b1 & 0x3f;
|
|
|
|
mouse_data[2] = b2 & 0x3f;
|
2004-12-05 23:23:39 +03:00
|
|
|
mouse_data[3] = b3 & 0x0f;
|
|
|
|
mouse_data[3] |= ((button_state & 0x04) << 2);
|
2004-12-03 00:34:26 +03:00
|
|
|
|
|
|
|
/* enqueue mouse data in multibyte internal mouse buffer */
|
2004-12-05 23:23:39 +03:00
|
|
|
int bytes = 3;
|
2004-12-09 21:47:36 +03:00
|
|
|
if (bx_options.Omouse_type->get() == BX_MOUSE_TYPE_SERIAL_WHEEL) bytes = 4;
|
2004-12-05 23:23:39 +03:00
|
|
|
for (int i = 0; i < bytes; i++) {
|
2004-12-03 00:34:26 +03:00
|
|
|
tail = (BX_SER_THIS mouse_internal_buffer.head + BX_SER_THIS mouse_internal_buffer.num_elements) %
|
|
|
|
BX_MOUSE_BUFF_SIZE;
|
|
|
|
BX_SER_THIS mouse_internal_buffer.buffer[tail] = mouse_data[i];
|
|
|
|
BX_SER_THIS mouse_internal_buffer.num_elements++;
|
|
|
|
}
|
|
|
|
}
|