2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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2006-03-26 23:39:37 +04:00
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// $Id: io.cc,v 1.30 2006-03-26 19:39:37 sshwarts Exp $
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2001-10-03 17:10:38 +04:00
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/////////////////////////////////////////////////////////////////////////
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//
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2001-04-10 06:20:02 +04:00
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// Copyright (C) 2001 MandrakeSoft S.A.
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2001-04-10 05:04:59 +04:00
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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2001-05-24 22:46:34 +04:00
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#define NEED_CPU_REG_SHORTCUTS 1
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2001-04-10 05:04:59 +04:00
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#include "bochs.h"
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2006-03-07 01:03:16 +03:00
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#include "cpu.h"
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merge in BRANCH-io-cleanup.
To see the commit logs for this use either cvsweb or
cvs update -r BRANCH-io-cleanup and then 'cvs log' the various files.
In general this provides a generic interface for logging.
logfunctions:: is a class that is inherited by some classes, and also
. allocated as a standalone global called 'genlog'. All logging uses
. one of the ::info(), ::error(), ::ldebug(), ::panic() methods of this
. class through 'BX_INFO(), BX_ERROR(), BX_DEBUG(), BX_PANIC()' macros
. respectively.
.
. An example usage:
. BX_INFO(("Hello, World!\n"));
iofunctions:: is a class that is allocated once by default, and assigned
as the iofunction of each logfunctions instance. It is this class that
maintains the file descriptor and other output related code, at this
point using vfprintf(). At some future point, someone may choose to
write a gui 'console' for bochs to which messages would be redirected
simply by assigning a different iofunction class to the various logfunctions
objects.
More cleanup is coming, but this works for now. If you want to see alot
of debugging output, in main.cc, change onoff[LOGLEV_DEBUG]=0 to =1.
Comments, bugs, flames, to me: todd@fries.net
2001-05-15 18:49:57 +04:00
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#define LOG_THIS BX_CPU_THIS_PTR
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2001-04-10 05:04:59 +04:00
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2006-03-07 01:03:16 +03:00
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#include "iodev/iodev.h"
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2001-04-10 05:04:59 +04:00
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2002-09-15 06:55:34 +04:00
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#if BX_SUPPORT_X86_64==0
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// Make life easier for merging cpu64 and cpu32 code.
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#define RDI EDI
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#define RSI ESI
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#define RAX EAX
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#endif
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2001-04-10 05:04:59 +04:00
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2002-09-09 20:56:56 +04:00
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2005-05-21 00:06:50 +04:00
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void BX_CPU_C::INSB_YbDX(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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{
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Bit8u value8=0;
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2002-09-12 22:10:46 +04:00
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if (BX_CPU_THIS_PTR cr0.pe && (BX_CPU_THIS_PTR get_VM () || (CPL>BX_CPU_THIS_PTR get_IOPL ()))) {
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2001-04-10 05:04:59 +04:00
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if ( !BX_CPU_THIS_PTR allow_io(DX, 1) ) {
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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2005-05-21 00:06:50 +04:00
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}
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2001-04-10 05:04:59 +04:00
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2004-03-02 23:48:48 +03:00
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#if BX_SUPPORT_X86_64
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2002-09-18 09:36:48 +04:00
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if (i->as64L()) {
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2002-09-15 06:55:34 +04:00
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// Write a zero to memory, to trigger any segment or page
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// faults before reading from IO port.
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write_virtual_byte(BX_SEG_REG_ES, RDI, &value8);
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value8 = BX_INP(DX, 1);
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/* no seg override possible */
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write_virtual_byte(BX_SEG_REG_ES, RDI, &value8);
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2004-03-02 23:48:48 +03:00
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if (BX_CPU_THIS_PTR get_DF ())
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RDI--;
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else
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RDI++;
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2005-05-21 00:06:50 +04:00
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}
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2004-03-02 23:48:48 +03:00
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else
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#endif
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if (i->as32L()) {
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2001-04-10 05:04:59 +04:00
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// Write a zero to memory, to trigger any segment or page
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// faults before reading from IO port.
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write_virtual_byte(BX_SEG_REG_ES, EDI, &value8);
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value8 = BX_INP(DX, 1);
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/* no seg override possible */
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write_virtual_byte(BX_SEG_REG_ES, EDI, &value8);
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2002-09-12 22:10:46 +04:00
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if (BX_CPU_THIS_PTR get_DF ()) {
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2002-09-15 06:55:34 +04:00
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RDI = EDI - 1;
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2005-05-21 00:06:50 +04:00
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}
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2001-04-10 05:04:59 +04:00
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else {
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2002-09-15 06:55:34 +04:00
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RDI = EDI + 1;
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2001-04-10 05:04:59 +04:00
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}
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2005-05-21 00:06:50 +04:00
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}
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2001-04-10 05:04:59 +04:00
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else {
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// Write a zero to memory, to trigger any segment or page
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// faults before reading from IO port.
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write_virtual_byte(BX_SEG_REG_ES, DI, &value8);
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value8 = BX_INP(DX, 1);
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/* no seg override possible */
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write_virtual_byte(BX_SEG_REG_ES, DI, &value8);
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2004-03-02 23:48:48 +03:00
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if (BX_CPU_THIS_PTR get_DF ())
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DI--;
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else
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DI++;
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}
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2001-04-10 05:04:59 +04:00
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}
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2005-05-21 00:06:50 +04:00
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void BX_CPU_C::INSW_YvDX(bxInstruction_c *i)
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2001-04-10 05:04:59 +04:00
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// input word/doubleword from port to string
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{
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2002-09-15 06:55:34 +04:00
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bx_address edi;
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2001-04-10 05:04:59 +04:00
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unsigned int incr;
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2004-03-02 23:48:48 +03:00
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#if BX_SUPPORT_X86_64
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2002-09-18 09:36:48 +04:00
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if (i->as64L()) // This was coded as if (i->as_64) ???
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2002-09-15 06:55:34 +04:00
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edi = RDI;
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2004-03-02 23:48:48 +03:00
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else
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#endif
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if (i->as32L())
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2001-04-10 05:04:59 +04:00
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edi = EDI;
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else
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edi = DI;
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2002-09-18 09:36:48 +04:00
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if (i->os32L()) {
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2001-04-10 05:04:59 +04:00
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Bit32u value32=0;
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2002-09-12 22:10:46 +04:00
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if (BX_CPU_THIS_PTR cr0.pe && (BX_CPU_THIS_PTR get_VM () || (CPL>BX_CPU_THIS_PTR get_IOPL ()))) {
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2001-04-10 05:04:59 +04:00
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if ( !BX_CPU_THIS_PTR allow_io(DX, 4) ) {
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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2005-05-21 00:06:50 +04:00
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}
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2001-04-10 05:04:59 +04:00
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// Write a zero to memory, to trigger any segment or page
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// faults before reading from IO port.
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write_virtual_dword(BX_SEG_REG_ES, edi, &value32);
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value32 = BX_INP(DX, 4);
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/* no seg override allowed */
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write_virtual_dword(BX_SEG_REG_ES, edi, &value32);
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incr = 4;
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2005-05-21 00:06:50 +04:00
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}
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2001-04-10 05:04:59 +04:00
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else {
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Bit16u value16=0;
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2002-09-12 22:10:46 +04:00
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if (BX_CPU_THIS_PTR cr0.pe && (BX_CPU_THIS_PTR get_VM () || (CPL>BX_CPU_THIS_PTR get_IOPL ()))) {
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2004-03-02 23:48:48 +03:00
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if ( !BX_CPU_THIS_PTR allow_io(DX, 2) )
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2001-04-10 05:04:59 +04:00
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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2002-09-02 22:44:35 +04:00
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#if BX_SupportRepeatSpeedups
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Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
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#if (BX_DEBUGGER == 0)
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#if (defined(__i386__) && __i386__)
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/* If conditions are right, we can transfer IO to physical memory
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* in a batch, rather than one instruction at a time.
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*/
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2002-09-18 12:00:43 +04:00
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if (i->repUsedL() && !BX_CPU_THIS_PTR async_event) {
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Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
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Bit32u wordCount;
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2002-09-24 08:43:59 +04:00
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#if BX_SUPPORT_X86_64
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if (i->as64L())
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wordCount = RCX; // Truncated to 32bits. (we're only doing 1 page)
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else
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#endif
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2002-09-18 09:36:48 +04:00
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if (i->as32L())
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Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
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wordCount = ECX;
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else
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wordCount = CX;
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2002-09-03 23:38:27 +04:00
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Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
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if (wordCount) {
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2002-09-24 08:43:59 +04:00
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bx_address laddrDst;
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Bit32u paddrDst, wordsFitDst;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
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Bit8u *hostAddrDst;
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2002-09-03 23:38:27 +04:00
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bx_segment_reg_t *dstSegPtr;
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2002-09-09 20:56:56 +04:00
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int pointerDelta;
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2002-09-03 23:38:27 +04:00
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2002-10-17 02:10:07 +04:00
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dstSegPtr = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES];
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2002-09-03 23:38:27 +04:00
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// Do segment checks for the 1st word. We do not want to
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// trip an exception beyond this, because the address would
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// be incorrect. After we know how many bytes we will directly
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// transfer, we can do the full segment limit check ourselves
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// without generating an exception.
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write_virtual_checks(dstSegPtr, edi, 2);
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2005-02-28 21:56:05 +03:00
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laddrDst = BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_ES) + edi;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
if (BX_CPU_THIS_PTR cr0.pg)
|
2002-09-03 23:38:27 +04:00
|
|
|
paddrDst = dtranslate_linear(laddrDst, CPL==3, BX_WRITE);
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
else
|
2002-09-03 23:38:27 +04:00
|
|
|
paddrDst = laddrDst;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
// If we want to write directly into the physical memory array,
|
|
|
|
// we need the A20 address.
|
2002-09-03 23:38:27 +04:00
|
|
|
paddrDst = A20ADDR(paddrDst);
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
|
2002-09-19 23:17:20 +04:00
|
|
|
hostAddrDst = BX_CPU_THIS_PTR mem->getHostMemAddr(BX_CPU_THIS,
|
2006-03-26 23:39:37 +04:00
|
|
|
paddrDst, BX_WRITE, DATA_ACCESS);
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
|
|
|
|
// Check that native host access was not vetoed for that page, and
|
|
|
|
// that the address is word aligned.
|
2002-09-03 23:38:27 +04:00
|
|
|
if ( hostAddrDst && ! (paddrDst & 1) ) {
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
// See how many words can fit in the rest of this page.
|
2002-09-12 22:10:46 +04:00
|
|
|
if (BX_CPU_THIS_PTR get_DF ()) {
|
2002-09-03 23:38:27 +04:00
|
|
|
// Counting downward.
|
|
|
|
// Note: 1st word must not cross page boundary.
|
|
|
|
if ( (paddrDst & 0xfff) > 0xffe )
|
|
|
|
goto noAcceleration;
|
|
|
|
wordsFitDst = (2 + (paddrDst & 0xfff)) >> 1;
|
2002-09-09 20:56:56 +04:00
|
|
|
pointerDelta = -2;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-03 23:38:27 +04:00
|
|
|
else {
|
|
|
|
// Counting upward.
|
|
|
|
wordsFitDst = (0x1000 - (paddrDst & 0xfff)) >> 1;
|
|
|
|
pointerDelta = 2;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-03 23:38:27 +04:00
|
|
|
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
// Restrict word count to the number that will fit in this page.
|
2002-09-03 23:38:27 +04:00
|
|
|
if (wordCount > wordsFitDst)
|
|
|
|
wordCount = wordsFitDst;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
|
|
|
|
// If after all the restrictions, there is anything left to do...
|
|
|
|
if (wordCount) {
|
|
|
|
unsigned j;
|
2002-09-03 23:38:27 +04:00
|
|
|
Bit32u dstSegLimit;
|
|
|
|
|
|
|
|
dstSegLimit = dstSegPtr->cache.u.segment.limit_scaled;
|
|
|
|
// For 16-bit addressing mode, clamp the segment limits to 16bits
|
|
|
|
// so we don't have to worry about computations using si/di
|
|
|
|
// rolling over 16-bit boundaries.
|
2002-09-18 09:36:48 +04:00
|
|
|
if (!i->as32L()) {
|
2002-09-03 23:38:27 +04:00
|
|
|
if (dstSegLimit > 0xffff)
|
|
|
|
dstSegLimit = 0xffff;
|
|
|
|
}
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
|
|
|
|
// Before we copy memory, we need to make sure that the segments
|
|
|
|
// allow the accesses up to the given source and dest offset. If
|
|
|
|
// the cache.valid bits have SegAccessWOK and ROK, we know that
|
|
|
|
// the cache is valid for those operations, and that the segments
|
|
|
|
// are non-expand down (thus we can make a simple limit check).
|
|
|
|
if ( !(dstSegPtr->cache.valid & SegAccessWOK) ) {
|
|
|
|
goto noAcceleration;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2005-08-02 01:40:17 +04:00
|
|
|
if (BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64) {
|
2002-09-24 08:43:59 +04:00
|
|
|
// Now make sure transfer will fit within the constraints of the
|
|
|
|
// segment boundaries, 0..limit for non expand-down. We know
|
|
|
|
// wordCount >= 1 here.
|
|
|
|
if (BX_CPU_THIS_PTR get_DF ()) {
|
|
|
|
// Counting downward.
|
|
|
|
Bit32u minOffset = (wordCount-1) << 1;
|
|
|
|
if ( edi < minOffset )
|
|
|
|
goto noAcceleration;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-24 08:43:59 +04:00
|
|
|
else {
|
|
|
|
// Counting upward.
|
|
|
|
Bit32u dstMaxOffset = (dstSegLimit - (wordCount<<1)) + 1;
|
|
|
|
if ( edi > dstMaxOffset )
|
|
|
|
goto noAcceleration;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
|
|
|
|
for (j=0; j<wordCount; ) {
|
|
|
|
Bit16u temp16;
|
2002-09-09 20:56:56 +04:00
|
|
|
bx_devices.bulkIOQuantumsTransferred = 0;
|
2002-09-12 22:10:46 +04:00
|
|
|
if ( BX_CPU_THIS_PTR get_DF ()==0 ) { // Only do accel for DF=0
|
2005-04-02 15:30:08 +04:00
|
|
|
bx_devices.bulkIOHostAddr = hostAddrDst;
|
2002-09-09 20:56:56 +04:00
|
|
|
bx_devices.bulkIOQuantumsRequested = (wordCount - j);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-09 20:56:56 +04:00
|
|
|
else
|
|
|
|
bx_devices.bulkIOQuantumsRequested = 0;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
temp16 = BX_INP(DX, 2);
|
2002-09-09 20:56:56 +04:00
|
|
|
if ( bx_devices.bulkIOQuantumsTransferred ) {
|
2005-04-02 15:30:08 +04:00
|
|
|
hostAddrDst = bx_devices.bulkIOHostAddr;
|
2002-09-09 20:56:56 +04:00
|
|
|
j += bx_devices.bulkIOQuantumsTransferred;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-09 20:56:56 +04:00
|
|
|
else {
|
|
|
|
* (Bit16u *) hostAddrDst = temp16;
|
|
|
|
hostAddrDst += pointerDelta;
|
|
|
|
j++;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-03 23:38:27 +04:00
|
|
|
// Terminate early if there was an event.
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
if ( BX_CPU_THIS_PTR async_event )
|
|
|
|
break;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-09 20:56:56 +04:00
|
|
|
// Reset for next non-bulk IO.
|
|
|
|
bx_devices.bulkIOQuantumsRequested = 0;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
wordCount = j;
|
|
|
|
// Decrement eCX. Note, the main loop will decrement 1 also, so
|
|
|
|
// decrement by one less than expected, like the case above.
|
2002-09-09 20:56:56 +04:00
|
|
|
BX_TICKN(j-1); // Main cpu loop also decrements one more.
|
2002-09-24 08:43:59 +04:00
|
|
|
#if BX_SUPPORT_X86_64
|
|
|
|
if (i->as64L())
|
|
|
|
RCX -= (wordCount-1);
|
|
|
|
else
|
|
|
|
#endif
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->as32L())
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
ECX -= (wordCount-1);
|
|
|
|
else
|
|
|
|
CX -= (wordCount-1);
|
|
|
|
incr = wordCount << 1; // count * 2.
|
|
|
|
goto doIncr;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
|
|
|
|
noAcceleration:
|
|
|
|
|
2002-09-03 23:38:27 +04:00
|
|
|
#endif // __i386__
|
|
|
|
#endif // (BX_DEBUGGER == 0)
|
|
|
|
#endif // #if BX_SupportRepeatSpeedups
|
|
|
|
|
2001-04-10 05:04:59 +04:00
|
|
|
// Write a zero to memory, to trigger any segment or page
|
|
|
|
// faults before reading from IO port.
|
|
|
|
write_virtual_word(BX_SEG_REG_ES, edi, &value16);
|
|
|
|
|
|
|
|
value16 = BX_INP(DX, 2);
|
|
|
|
|
|
|
|
/* no seg override allowed */
|
|
|
|
write_virtual_word(BX_SEG_REG_ES, edi, &value16);
|
|
|
|
incr = 2;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2002-09-03 23:38:27 +04:00
|
|
|
#if BX_SupportRepeatSpeedups
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
#if (BX_DEBUGGER == 0)
|
2002-09-03 23:38:27 +04:00
|
|
|
#if (defined(__i386__) && __i386__)
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
doIncr:
|
2002-09-03 23:38:27 +04:00
|
|
|
#endif
|
|
|
|
#endif
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
#endif
|
|
|
|
|
2004-03-02 23:48:48 +03:00
|
|
|
#if BX_SUPPORT_X86_64
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->as64L()) {
|
2002-09-15 06:55:34 +04:00
|
|
|
if (BX_CPU_THIS_PTR get_DF ())
|
|
|
|
RDI = RDI - incr;
|
|
|
|
else
|
|
|
|
RDI = RDI + incr;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-15 06:55:34 +04:00
|
|
|
else
|
2004-03-02 23:48:48 +03:00
|
|
|
#endif
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->as32L()) {
|
2002-09-12 22:10:46 +04:00
|
|
|
if (BX_CPU_THIS_PTR get_DF ())
|
2002-09-15 06:55:34 +04:00
|
|
|
RDI = EDI - incr;
|
2001-04-10 05:04:59 +04:00
|
|
|
else
|
2002-09-15 06:55:34 +04:00
|
|
|
RDI = EDI + incr;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else {
|
2002-09-12 22:10:46 +04:00
|
|
|
if (BX_CPU_THIS_PTR get_DF ())
|
2001-04-10 05:04:59 +04:00
|
|
|
DI = DI - incr;
|
|
|
|
else
|
|
|
|
DI = DI + incr;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2005-05-21 00:06:50 +04:00
|
|
|
void BX_CPU_C::OUTSB_DXXb(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
unsigned seg;
|
|
|
|
Bit8u value8;
|
2002-09-15 06:55:34 +04:00
|
|
|
bx_address esi;
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2002-09-12 22:10:46 +04:00
|
|
|
if (BX_CPU_THIS_PTR cr0.pe && (BX_CPU_THIS_PTR get_VM () || (CPL>BX_CPU_THIS_PTR get_IOPL ()))) {
|
2001-04-10 05:04:59 +04:00
|
|
|
if ( !BX_CPU_THIS_PTR allow_io(DX, 1) ) {
|
|
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2002-09-18 09:36:48 +04:00
|
|
|
if (!BX_NULL_SEG_REG(i->seg())) {
|
|
|
|
seg = i->seg();
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else {
|
|
|
|
seg = BX_SEG_REG_DS;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-03-02 23:48:48 +03:00
|
|
|
#if BX_SUPPORT_X86_64
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->as64L())
|
2002-09-15 06:55:34 +04:00
|
|
|
esi = RSI;
|
2004-03-02 23:48:48 +03:00
|
|
|
else
|
|
|
|
#endif
|
|
|
|
if (i->as32L())
|
2001-04-10 05:04:59 +04:00
|
|
|
esi = ESI;
|
|
|
|
else
|
|
|
|
esi = SI;
|
|
|
|
|
|
|
|
read_virtual_byte(seg, esi, &value8);
|
|
|
|
|
|
|
|
BX_OUTP(DX, value8, 1);
|
|
|
|
|
2004-03-02 23:48:48 +03:00
|
|
|
#if BX_SUPPORT_X86_64
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->as64L()) {
|
2002-09-17 00:23:38 +04:00
|
|
|
if (BX_CPU_THIS_PTR get_DF ())
|
2004-03-02 23:48:48 +03:00
|
|
|
RSI--;
|
2002-09-17 00:23:38 +04:00
|
|
|
else
|
2004-03-02 23:48:48 +03:00
|
|
|
RSI++;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2004-03-02 23:48:48 +03:00
|
|
|
else
|
|
|
|
#endif
|
|
|
|
if (i->as32L()) {
|
2002-09-12 22:10:46 +04:00
|
|
|
if (BX_CPU_THIS_PTR get_DF ())
|
2004-03-02 23:48:48 +03:00
|
|
|
RSI--;
|
2001-04-10 05:04:59 +04:00
|
|
|
else
|
2004-03-02 23:48:48 +03:00
|
|
|
RSI++;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else {
|
2002-09-12 22:10:46 +04:00
|
|
|
if (BX_CPU_THIS_PTR get_DF ())
|
2004-03-02 23:48:48 +03:00
|
|
|
SI--;
|
2001-04-10 05:04:59 +04:00
|
|
|
else
|
2004-03-02 23:48:48 +03:00
|
|
|
SI++;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2005-05-21 00:06:50 +04:00
|
|
|
// output word/doubleword string to port
|
|
|
|
void BX_CPU_C::OUTSW_DXXv(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
unsigned seg;
|
2002-09-24 08:43:59 +04:00
|
|
|
bx_address esi;
|
2001-04-10 05:04:59 +04:00
|
|
|
unsigned int incr;
|
|
|
|
|
2002-09-18 09:36:48 +04:00
|
|
|
if (!BX_NULL_SEG_REG(i->seg())) {
|
|
|
|
seg = i->seg();
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else {
|
|
|
|
seg = BX_SEG_REG_DS;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2004-03-02 23:48:48 +03:00
|
|
|
#if BX_SUPPORT_X86_64
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->as64L())
|
2002-09-15 06:55:34 +04:00
|
|
|
esi = RSI;
|
2004-03-02 23:48:48 +03:00
|
|
|
else
|
|
|
|
#endif
|
|
|
|
if (i->as32L())
|
2001-04-10 05:04:59 +04:00
|
|
|
esi = ESI;
|
|
|
|
else
|
|
|
|
esi = SI;
|
|
|
|
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->os32L()) {
|
2001-04-10 05:04:59 +04:00
|
|
|
Bit32u value32;
|
|
|
|
|
2002-09-12 22:10:46 +04:00
|
|
|
if (BX_CPU_THIS_PTR cr0.pe && (BX_CPU_THIS_PTR get_VM () || (CPL>BX_CPU_THIS_PTR get_IOPL ()))) {
|
2001-04-10 05:04:59 +04:00
|
|
|
if ( !BX_CPU_THIS_PTR allow_io(DX, 4) ) {
|
|
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
|
|
|
read_virtual_dword(seg, esi, &value32);
|
|
|
|
|
|
|
|
BX_OUTP(DX, value32, 4);
|
|
|
|
incr = 4;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else {
|
|
|
|
Bit16u value16;
|
|
|
|
|
2002-09-12 22:10:46 +04:00
|
|
|
if (BX_CPU_THIS_PTR cr0.pe && (BX_CPU_THIS_PTR get_VM () || (CPL>BX_CPU_THIS_PTR get_IOPL ()))) {
|
2001-04-10 05:04:59 +04:00
|
|
|
if ( !BX_CPU_THIS_PTR allow_io(DX, 2) ) {
|
|
|
|
exception(BX_GP_EXCEPTION, 0, 0);
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2002-09-02 22:44:35 +04:00
|
|
|
#if BX_SupportRepeatSpeedups
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
#if (BX_DEBUGGER == 0)
|
|
|
|
#if (defined(__i386__) && __i386__)
|
|
|
|
/* If conditions are right, we can transfer IO to physical memory
|
|
|
|
* in a batch, rather than one instruction at a time.
|
|
|
|
*/
|
2002-09-18 12:00:43 +04:00
|
|
|
if (i->repUsedL() && !BX_CPU_THIS_PTR async_event) {
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
Bit32u wordCount;
|
|
|
|
|
2002-09-24 08:43:59 +04:00
|
|
|
#if BX_SUPPORT_X86_64
|
|
|
|
if (i->as64L())
|
|
|
|
wordCount = RCX; // Truncated to 32bits. (we're only doing 1 page)
|
|
|
|
else
|
|
|
|
#endif
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->as32L())
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
wordCount = ECX;
|
|
|
|
else
|
|
|
|
wordCount = CX;
|
2002-09-03 23:38:27 +04:00
|
|
|
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
if (wordCount) {
|
2002-09-24 08:43:59 +04:00
|
|
|
bx_address laddrSrc;
|
|
|
|
Bit32u paddrSrc, wordsFitSrc;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
Bit8u *hostAddrSrc;
|
2002-09-03 23:38:27 +04:00
|
|
|
bx_segment_reg_t *srcSegPtr;
|
|
|
|
unsigned pointerDelta;
|
|
|
|
|
|
|
|
srcSegPtr = &BX_CPU_THIS_PTR sregs[seg];
|
|
|
|
|
|
|
|
// Do segment checks for the 1st word. We do not want to
|
|
|
|
// trip an exception beyond this, because the address would
|
|
|
|
// be incorrect. After we know how many bytes we will directly
|
|
|
|
// transfer, we can do the full segment limit check ourselves
|
|
|
|
// without generating an exception.
|
|
|
|
read_virtual_checks(srcSegPtr, esi, 2);
|
2005-02-28 21:56:05 +03:00
|
|
|
laddrSrc = BX_CPU_THIS_PTR get_segment_base(seg) + esi;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
if (BX_CPU_THIS_PTR cr0.pg)
|
2002-09-03 23:38:27 +04:00
|
|
|
paddrSrc = dtranslate_linear(laddrSrc, CPL==3, BX_READ);
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
else
|
2002-09-03 23:38:27 +04:00
|
|
|
paddrSrc = laddrSrc;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
// If we want to write directly into the physical memory array,
|
|
|
|
// we need the A20 address.
|
2002-09-03 23:38:27 +04:00
|
|
|
paddrSrc = A20ADDR(paddrSrc);
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
|
2002-09-19 23:17:20 +04:00
|
|
|
hostAddrSrc = BX_CPU_THIS_PTR mem->getHostMemAddr(BX_CPU_THIS,
|
2006-03-26 23:39:37 +04:00
|
|
|
paddrSrc, BX_READ, DATA_ACCESS);
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
|
|
|
|
// Check that native host access was not vetoed for that page, and
|
|
|
|
// that the address is word aligned.
|
2002-09-03 23:38:27 +04:00
|
|
|
if ( hostAddrSrc && ! (paddrSrc & 1) ) {
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
// See how many words can fit in the rest of this page.
|
2002-09-12 22:10:46 +04:00
|
|
|
if (BX_CPU_THIS_PTR get_DF ()) {
|
2002-09-03 23:38:27 +04:00
|
|
|
// Counting downward.
|
|
|
|
// Note: 1st word must not cross page boundary.
|
|
|
|
if ( (paddrSrc & 0xfff) > 0xffe )
|
|
|
|
goto noAcceleration;
|
|
|
|
wordsFitSrc = (2 + (paddrSrc & 0xfff)) >> 1;
|
|
|
|
pointerDelta = (unsigned) -2;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-03 23:38:27 +04:00
|
|
|
else {
|
|
|
|
// Counting upward.
|
|
|
|
wordsFitSrc = (0x1000 - (paddrSrc & 0xfff)) >> 1;
|
|
|
|
pointerDelta = 2;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-03 23:38:27 +04:00
|
|
|
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
// Restrict word count to the number that will fit in this page.
|
2002-09-03 23:38:27 +04:00
|
|
|
if (wordCount > wordsFitSrc)
|
|
|
|
wordCount = wordsFitSrc;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
|
|
|
|
// If after all the restrictions, there is anything left to do...
|
|
|
|
if (wordCount) {
|
|
|
|
unsigned j;
|
2002-09-03 23:38:27 +04:00
|
|
|
Bit32u srcSegLimit;
|
|
|
|
|
|
|
|
srcSegLimit = srcSegPtr->cache.u.segment.limit_scaled;
|
|
|
|
// For 16-bit addressing mode, clamp the segment limits to 16bits
|
|
|
|
// so we don't have to worry about computations using si/di
|
|
|
|
// rolling over 16-bit boundaries.
|
2002-09-18 09:36:48 +04:00
|
|
|
if (!i->as32L()) {
|
2002-09-03 23:38:27 +04:00
|
|
|
if (srcSegLimit > 0xffff)
|
|
|
|
srcSegLimit = 0xffff;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
|
|
|
|
// Before we copy memory, we need to make sure that the segments
|
|
|
|
// allow the accesses up to the given source and dest offset. If
|
|
|
|
// the cache.valid bits have SegAccessWOK and ROK, we know that
|
|
|
|
// the cache is valid for those operations, and that the segments
|
|
|
|
// are non-expand down (thus we can make a simple limit check).
|
|
|
|
if ( !(srcSegPtr->cache.valid & SegAccessROK) ) {
|
|
|
|
goto noAcceleration;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2005-08-02 01:40:17 +04:00
|
|
|
if (BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64) {
|
2002-09-24 08:43:59 +04:00
|
|
|
// Now make sure transfer will fit within the constraints of the
|
|
|
|
// segment boundaries, 0..limit for non expand-down. We know
|
|
|
|
// wordCount >= 1 here.
|
|
|
|
if (BX_CPU_THIS_PTR get_DF ()) {
|
|
|
|
// Counting downward.
|
|
|
|
Bit32u minOffset = (wordCount-1) << 1;
|
|
|
|
if ( esi < minOffset )
|
|
|
|
goto noAcceleration;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-24 08:43:59 +04:00
|
|
|
else {
|
|
|
|
// Counting upward.
|
|
|
|
Bit32u srcMaxOffset = (srcSegLimit - (wordCount<<1)) + 1;
|
|
|
|
if ( esi > srcMaxOffset )
|
|
|
|
goto noAcceleration;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
|
|
|
|
for (j=0; j<wordCount; ) {
|
|
|
|
Bit16u temp16;
|
2002-09-09 20:56:56 +04:00
|
|
|
bx_devices.bulkIOQuantumsTransferred = 0;
|
2002-09-12 22:10:46 +04:00
|
|
|
if ( BX_CPU_THIS_PTR get_DF ()==0 ) { // Only do accel for DF=0
|
2005-04-02 15:30:08 +04:00
|
|
|
bx_devices.bulkIOHostAddr = hostAddrSrc;
|
2002-09-09 20:56:56 +04:00
|
|
|
bx_devices.bulkIOQuantumsRequested = (wordCount - j);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-09 20:56:56 +04:00
|
|
|
else
|
|
|
|
bx_devices.bulkIOQuantumsRequested = 0;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
temp16 = * (Bit16u *) hostAddrSrc;
|
|
|
|
BX_OUTP(DX, temp16, 2);
|
2002-09-09 20:56:56 +04:00
|
|
|
if ( bx_devices.bulkIOQuantumsTransferred ) {
|
2005-04-02 15:30:08 +04:00
|
|
|
hostAddrSrc = bx_devices.bulkIOHostAddr;
|
2002-09-09 20:56:56 +04:00
|
|
|
j += bx_devices.bulkIOQuantumsTransferred;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-09 20:56:56 +04:00
|
|
|
else {
|
|
|
|
hostAddrSrc += pointerDelta;
|
|
|
|
j++;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-03 23:38:27 +04:00
|
|
|
// Terminate early if there was an event.
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
if ( BX_CPU_THIS_PTR async_event )
|
|
|
|
break;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2002-09-09 20:56:56 +04:00
|
|
|
// Reset for next non-bulk IO.
|
|
|
|
bx_devices.bulkIOQuantumsRequested = 0;
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
wordCount = j;
|
|
|
|
// Decrement eCX. Note, the main loop will decrement 1 also, so
|
|
|
|
// decrement by one less than expected, like the case above.
|
2002-09-09 20:56:56 +04:00
|
|
|
BX_TICKN(j-1); // Main cpu loop also decrements one more.
|
2002-09-24 08:43:59 +04:00
|
|
|
#if BX_SUPPORT_X86_64
|
|
|
|
if (i->as64L())
|
|
|
|
RCX -= (wordCount-1);
|
|
|
|
else
|
|
|
|
#endif
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->as32L())
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
ECX -= (wordCount-1);
|
|
|
|
else
|
|
|
|
CX -= (wordCount-1);
|
|
|
|
incr = wordCount << 1; // count * 2.
|
|
|
|
goto doIncr;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
|
|
|
|
noAcceleration:
|
|
|
|
|
2002-09-03 23:38:27 +04:00
|
|
|
#endif // __i386__
|
|
|
|
#endif // (BX_DEBUGGER == 0)
|
|
|
|
#endif // #if BX_SupportRepeatSpeedups
|
|
|
|
|
2001-04-10 05:04:59 +04:00
|
|
|
read_virtual_word(seg, esi, &value16);
|
|
|
|
|
|
|
|
BX_OUTP(DX, value16, 2);
|
|
|
|
incr = 2;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
|
2002-09-03 23:38:27 +04:00
|
|
|
#if BX_SupportRepeatSpeedups
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
#if (BX_DEBUGGER == 0)
|
2002-09-03 23:38:27 +04:00
|
|
|
#if (defined(__i386__) && __i386__)
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
doIncr:
|
2002-09-03 23:38:27 +04:00
|
|
|
#endif
|
|
|
|
#endif
|
Integrated patches for:
- Paging code rehash. You must now use --enable-4meg-pages to
use 4Meg pages, with the default of disabled, since we don't well
support 4Meg pages yet. Paging table walks model a real CPU
more closely now, and I fixed some bugs in the old logic.
- Segment check redundancy elimination. After a segment is loaded,
reads and writes are marked when a segment type check succeeds, and
they are skipped thereafter, when possible.
- Repeated IO and memory string copy acceleration. Only some variants
of instructions are available on all platforms, word and dword
variants only on x86 for the moment due to alignment and endian issues.
This is compiled in currently with no option - I should add a configure
option.
- Added a guest linear address to host TLB. Actually, I just stick
the host address (mem.vector[addr] address) in the upper 29 bits
of the field 'combined_access' since they are unused. Convenient
for now. I'm only storing page frame addresses. This was the
simplest for of such a TLB. We can likely enhance this. Also,
I only accelerated the normal read/write routines in access.cc.
Could also modify the read-modify-write versions too. You must
use --enable-guest2host-tlb, to try this out. Currently speeds
up Win95 boot time by about 3.5% for me. More ground to cover...
- Minor mods to CPUI/MOV_CdRd for CMOV.
- Integrated enhancements from Volker to getHostMemAddr() for PCI
being enabled.
2002-09-02 00:12:09 +04:00
|
|
|
#endif
|
|
|
|
|
2004-03-02 23:48:48 +03:00
|
|
|
#if BX_SUPPORT_X86_64
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->as64L()) {
|
2002-09-15 06:55:34 +04:00
|
|
|
if (BX_CPU_THIS_PTR get_DF ())
|
|
|
|
RSI = RSI - incr;
|
|
|
|
else
|
|
|
|
RSI = RSI + incr;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2004-03-02 23:48:48 +03:00
|
|
|
else
|
|
|
|
#endif
|
|
|
|
if (i->as32L()) {
|
2002-09-12 22:10:46 +04:00
|
|
|
if (BX_CPU_THIS_PTR get_DF ())
|
2002-09-15 06:55:34 +04:00
|
|
|
RSI = ESI - incr;
|
2001-04-10 05:04:59 +04:00
|
|
|
else
|
2002-09-15 06:55:34 +04:00
|
|
|
RSI = ESI + incr;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else {
|
2002-09-12 22:10:46 +04:00
|
|
|
if (BX_CPU_THIS_PTR get_DF ())
|
2001-04-10 05:04:59 +04:00
|
|
|
SI = SI - incr;
|
|
|
|
else
|
|
|
|
SI = SI + incr;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2005-05-21 00:06:50 +04:00
|
|
|
void BX_CPU_C::IN_ALIb(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2004-03-02 23:48:48 +03:00
|
|
|
AL = BX_CPU_THIS_PTR inp8(i->Ib());
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2005-05-21 00:06:50 +04:00
|
|
|
void BX_CPU_C::IN_eAXIb(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
#if BX_CPU_LEVEL > 2
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->os32L()) {
|
2004-03-02 23:48:48 +03:00
|
|
|
Bit32u eax = BX_CPU_THIS_PTR inp32(i->Ib());
|
2002-09-15 06:55:34 +04:00
|
|
|
RAX = eax;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else
|
|
|
|
#endif /* BX_CPU_LEVEL > 2 */
|
2005-05-21 00:06:50 +04:00
|
|
|
{
|
2004-03-02 23:48:48 +03:00
|
|
|
AX = BX_CPU_THIS_PTR inp16(i->Ib());
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2005-05-21 00:06:50 +04:00
|
|
|
void BX_CPU_C::OUT_IbAL(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2004-03-02 23:48:48 +03:00
|
|
|
BX_CPU_THIS_PTR outp8(i->Ib(), AL);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2005-05-21 00:06:50 +04:00
|
|
|
void BX_CPU_C::OUT_IbeAX(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
#if BX_CPU_LEVEL > 2
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->os32L()) {
|
2004-03-02 23:48:48 +03:00
|
|
|
BX_CPU_THIS_PTR outp32(i->Ib(), EAX);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else
|
|
|
|
#endif /* BX_CPU_LEVEL > 2 */
|
2005-05-21 00:06:50 +04:00
|
|
|
{
|
2004-03-02 23:48:48 +03:00
|
|
|
BX_CPU_THIS_PTR outp16(i->Ib(), AX);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2005-05-21 00:06:50 +04:00
|
|
|
void BX_CPU_C::IN_ALDX(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2004-03-02 23:48:48 +03:00
|
|
|
AL = BX_CPU_THIS_PTR inp8(DX);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2005-05-21 00:06:50 +04:00
|
|
|
void BX_CPU_C::IN_eAXDX(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
#if BX_CPU_LEVEL > 2
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->os32L()) {
|
2004-03-02 23:48:48 +03:00
|
|
|
Bit32u eax = BX_CPU_THIS_PTR inp32(DX);
|
2002-09-15 06:55:34 +04:00
|
|
|
RAX = eax;
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else
|
|
|
|
#endif /* BX_CPU_LEVEL > 2 */
|
2005-05-21 00:06:50 +04:00
|
|
|
{
|
2004-03-02 23:48:48 +03:00
|
|
|
AX = BX_CPU_THIS_PTR inp16(DX);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2005-05-21 00:06:50 +04:00
|
|
|
void BX_CPU_C::OUT_DXAL(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
2004-03-02 23:48:48 +03:00
|
|
|
BX_CPU_THIS_PTR outp8(DX, AL);
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|
|
|
|
|
2005-05-21 00:06:50 +04:00
|
|
|
void BX_CPU_C::OUT_DXeAX(bxInstruction_c *i)
|
2001-04-10 05:04:59 +04:00
|
|
|
{
|
|
|
|
#if BX_CPU_LEVEL > 2
|
2002-09-18 09:36:48 +04:00
|
|
|
if (i->os32L()) {
|
2004-03-02 23:48:48 +03:00
|
|
|
BX_CPU_THIS_PTR outp32(DX, EAX);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
else
|
|
|
|
#endif /* BX_CPU_LEVEL > 2 */
|
2005-05-21 00:06:50 +04:00
|
|
|
{
|
2004-03-02 23:48:48 +03:00
|
|
|
BX_CPU_THIS_PTR outp16(DX, AX);
|
2005-05-21 00:06:50 +04:00
|
|
|
}
|
2001-04-10 05:04:59 +04:00
|
|
|
}
|