diff --git a/apps/msk.c b/apps/msk.c index 8bd4f3ee..5aa6f0ce 100644 --- a/apps/msk.c +++ b/apps/msk.c @@ -174,6 +174,11 @@ static int update_stores(int argc, char * argv[]) { return usage(argc,argv); } + const char * manifest_prefix = ""; +#ifdef __aarch64__ + manifest_prefix = "aarch64."; +#endif + needs_lock(); read_config(); @@ -207,7 +212,7 @@ static int update_stores(int argc, char * argv[]) { } } else { char cmd[512]; - sprintf(cmd, "fetch -vo /tmp/.msk_remote_%s %s/manifest", remote_name, remote_path); + sprintf(cmd, "fetch -vo /tmp/.msk_remote_%s %s/%smanifest", remote_name, remote_path, manifest_prefix); fprintf(stderr, "Downloading remote manifest '%s'...\n", remote_name); if (system(cmd)) { fprintf(stderr, "Skipping unavailable remote manifest '%s' (%s).\n", remote_name, remote_path); diff --git a/build/aarch64.mk b/build/aarch64.mk index 33c01166..2a4e8943 100644 --- a/build/aarch64.mk +++ b/build/aarch64.mk @@ -44,7 +44,10 @@ EMU_ARGS += -serial mon:stdio EMU_ARGS += -device bochs-display EMU_ARGS += -device virtio-tablet-pci # Mouse with absolute positioning EMU_ARGS += -device virtio-keyboard-pci # Keyboard +EMU_ARGS += -device AC97 EMU_ARGS += -d guest_errors +EMU_ARGS += -net user +EMU_ARGS += -netdev hubport,id=u1,hubid=0, -device e1000e,netdev=u1 EMU_RAMDISK = -fw_cfg name=opt/org.toaruos.initrd,file=ramdisk.igz EMU_KERNEL = -fw_cfg name=opt/org.toaruos.kernel,file=misaka-kernel diff --git a/kernel/arch/aarch64/ac97_tmp.c b/kernel/arch/aarch64/ac97_tmp.c new file mode 100644 index 00000000..774ae970 --- /dev/null +++ b/kernel/arch/aarch64/ac97_tmp.c @@ -0,0 +1,406 @@ +/** + * @file kernel/audio/ac97.c + * @brief Driver for the Intel AC'97. + * @package x86_64 + * + * Simple PCM interface for the AC'97 codec when used with the + * ICH hardware interface. There are other hardware interfaces + * that use this codec and this driver could probably be ported + * to them. + * + * Note that the audio subsystem is intended to be non-blocking + * so that buffer filling can be done directly in interrupt handlers. + * + * @see http://www.intel.com/design/chipsets/manuals/29802801.pdf + * + * @copyright + * This file is part of ToaruOS and is released under the terms + * of the NCSA / University of Illinois License - see LICENSE.md + * Copyright (C) 2015 Michael Gerow + * Copyright (C) 2015-2021 K. Lange + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Utility macros */ +#define N_ELEMENTS(arr) (sizeof(arr) / sizeof((arr)[0])) + +/* BARs! */ +#define AC97_NAMBAR 0x10 /* Native Audio Mixer Base Address Register */ +#define AC97_NABMBAR 0x14 /* Native Audio Bus Mastering Base Address Register */ + +/* Bus mastering IO port offsets */ +#define AC97_PO_BDBAR 0x10 /* PCM out buffer descriptor BAR */ +#define AC97_PO_CIV 0x14 /* PCM out current index value */ +#define AC97_PO_LVI 0x15 /* PCM out last valid index */ +#define AC97_PO_SR 0x16 /* PCM out status register */ +#define AC97_PO_PICB 0x18 /* PCM out position in current buffer register */ +#define AC97_PO_CR 0x1B /* PCM out control register */ + +/* Bus mastering misc */ +/* Buffer descriptor list constants */ +#define AC97_BDL_LEN 32 /* Buffer descriptor list length */ +#define AC97_BDL_BUFFER_LEN 0x1000 /* Length of buffer in BDL */ +#define AC97_CL_GET_LENGTH(cl) ((cl) & 0xFFFF) /* Decode length from cl */ +#define AC97_CL_SET_LENGTH(cl, v) ((cl) = (v) & 0xFFFF) /* Encode length to cl */ +#define AC97_CL_BUP ((uint32_t)1 << 30) /* Buffer underrun policy in cl */ +#define AC97_CL_IOC ((uint32_t)1 << 31) /* Interrupt on completion flag in cl */ + +/* PCM out control register flags */ +#define AC97_X_CR_RPBM (1 << 0) /* Run/pause bus master */ +#define AC97_X_CR_RR (1 << 1) /* Reset registers */ +#define AC97_X_CR_LVBIE (1 << 2) /* Last valid buffer interrupt enable */ +#define AC97_X_CR_FEIE (1 << 3) /* FIFO error interrupt enable */ +#define AC97_X_CR_IOCE (1 << 4) /* Interrupt on completion enable */ + +/* Status register flags */ +#define AC97_X_SR_DCH (1 << 0) /* DMA controller halted */ +#define AC97_X_SR_CELV (1 << 1) /* Current equals last valid */ +#define AC97_X_SR_LVBCI (1 << 2) /* Last valid buffer completion interrupt */ +#define AC97_X_SR_BCIS (1 << 3) /* Buffer completion interrupt status */ +#define AC97_X_SR_FIFOE (1 << 4) /* FIFO error */ + +/* Mixer IO port offsets */ +#define AC97_RESET 0x00 +#define AC97_MASTER_VOLUME 0x02 +#define AC97_AUX_OUT_VOLUME 0x04 +#define AC97_MONO_VOLUME 0x06 +#define AC97_PCM_OUT_VOLUME 0x18 + +/* snd values */ +#define AC97_SND_NAME "Intel AC'97" +#define AC97_PLAYBACK_SPEED 48000 +#define AC97_PLAYBACK_FORMAT SND_FORMAT_L16SLE + +/* An entry in a buffer dscriptor list */ +typedef struct { + uint32_t pointer; /* Pointer to buffer */ + uint32_t cl; /* Control values and buffer length */ +} __attribute__((packed)) ac97_bdl_entry_t; + +typedef struct { + uint32_t pci_device; + uint16_t nabmbar; /* Native audio bus mastring BAR */ + uint16_t nambar; /* Native audio mixing BAR */ + size_t irq; /* This ac97's irq */ + uint8_t lvi; /* The currently set last valid index */ + uint8_t bits; /* How many bits of volume are supported (5 or 6) */ + ac97_bdl_entry_t * bdl; /* Buffer descriptor list */ + uint16_t * bufs[AC97_BDL_LEN]; /* Virtual addresses for buffers in BDL */ + uint32_t bdl_p; + uint32_t mask; + volatile char * _iobase; + spin_lock_t lock; +} ac97_device_t; + +static ac97_device_t _device; + +#define AC97_KNOB_PCM_OUT (SND_KNOB_VENDOR + 0) + +static snd_knob_t _knobs[] = { + { + "Master", + SND_KNOB_MASTER + }, + { + "PCM Out", + SND_KNOB_VENDOR + 0 + } +}; + +static int ac97_mixer_read(uint32_t knob_id, uint32_t *val); +static int ac97_mixer_write(uint32_t knob_id, uint32_t val); + +static snd_device_t _snd = { + .name = AC97_SND_NAME, + .device = &_device, + .playback_speed = AC97_PLAYBACK_SPEED, + .playback_format = AC97_PLAYBACK_FORMAT, + + .knobs = _knobs, + .num_knobs = N_ELEMENTS(_knobs), + + .mixer_read = ac97_mixer_read, + .mixer_write = ac97_mixer_write, +}; + +/* + * This could be unnecessary if we instead allocate just two buffers and make + * the ac97 think there are more. + */ + +static void find_ac97(uint32_t device, uint16_t vendorid, uint16_t deviceid, void * extra) { + + ac97_device_t * ac97 = extra; + + if ((vendorid == 0x8086) && (deviceid == 0x2415)) { + ac97->pci_device = device; + } + +} + +static uint8_t inportb(size_t port) { + volatile uint8_t * _port = (volatile uint8_t*)(_device._iobase + port); + return *_port; +} + +static uint16_t inports(size_t port) { + volatile uint16_t * _port = (volatile uint16_t*)(_device._iobase + port); + return *_port; +} + +static uint32_t inportl(size_t port) { + volatile uint32_t * _port = (volatile uint32_t*)(_device._iobase + port); + return *_port; +} + +static void outportb(size_t port, uint8_t val) { + volatile uint8_t * _port = (volatile uint8_t*)(_device._iobase + port); + *_port = val; +} + +static void outports(size_t port, uint16_t val) { + volatile uint16_t * _port = (volatile uint16_t*)(_device._iobase + port); + *_port = val; +} + +static void outportl(size_t port, uint32_t val) { + volatile uint32_t * _port = (volatile uint32_t*)(_device._iobase + port); + *_port = val; +} + +#define DIVISION 0x1000 +#if 0 +static int ac97_irq_handler(struct regs * regs) { + uint16_t sr = inports(_device.nabmbar + AC97_PO_SR); + if (sr & AC97_X_SR_BCIS) { + uint16_t current_buffer = inportb(_device.nabmbar + AC97_PO_CIV); + uint16_t last_valid = ((current_buffer+2) & (AC97_BDL_LEN-1)); + snd_request_buf(&_snd, 0x1000, (uint8_t *)_device.bufs[last_valid]); + outportb(_device.nabmbar + AC97_PO_LVI, last_valid); + snd_request_buf(&_snd, 0x1000, (uint8_t *)_device.bufs[last_valid]+0x1000); + outports(_device.nabmbar + AC97_PO_SR, AC97_X_SR_BCIS); + } else if (sr & AC97_X_SR_LVBCI) { + outports(_device.nabmbar + AC97_PO_SR, AC97_X_SR_LVBCI); + } else if (sr & AC97_X_SR_FIFOE) { + outports(_device.nabmbar + AC97_PO_SR, AC97_X_SR_FIFOE); + } else { + return 0; + } + irq_ack(_device.irq); + return 1; +} +#endif + +int ac97_irq_handler(process_t * this, int irq, void * data) { + spin_lock(_device.lock); + uint16_t sr = inports(_device.nabmbar + AC97_PO_SR); + if (sr & AC97_X_SR_BCIS) { + outports(_device.nabmbar + AC97_PO_SR, AC97_X_SR_BCIS); + spin_unlock(_device.lock); + uint16_t current_buffer = inportb(_device.nabmbar + AC97_PO_CIV); + uint16_t last_valid = ((current_buffer+2) & (AC97_BDL_LEN-1)); + snd_request_buf(&_snd, 0x1000, (uint8_t *)_device.bufs[last_valid]); + outportb(_device.nabmbar + AC97_PO_LVI, last_valid); + snd_request_buf(&_snd, 0x1000, (uint8_t *)_device.bufs[last_valid]+0x1000); + } else if (sr & AC97_X_SR_LVBCI) { + outports(_device.nabmbar + AC97_PO_SR, AC97_X_SR_LVBCI); + spin_unlock(_device.lock); + } else if (sr & AC97_X_SR_FIFOE) { + outports(_device.nabmbar + AC97_PO_SR, AC97_X_SR_FIFOE); + spin_unlock(_device.lock); + } else { + /* Spurious */ + spin_unlock(_device.lock); + return 0; + } + return 1; +} + +/* Currently we just assume right and left are the same */ +static int ac97_mixer_read(uint32_t knob_id, uint32_t *val) { + uint16_t tmp; + switch (knob_id) { + case SND_KNOB_MASTER: + tmp = inports(_device.nambar + AC97_MASTER_VOLUME); + if (tmp == 0x8000) { + *val = 0; + } else { + /* 6 bit value */ + *val = (tmp & _device.mask) << (sizeof(*val) * 8 - _device.bits); + *val = ~*val; + *val &= (uint32_t)_device.mask << (sizeof(*val) * 8 - _device.bits); + } + break; + case AC97_KNOB_PCM_OUT: + tmp = inports(_device.nambar + AC97_PCM_OUT_VOLUME); + if (tmp == 0x8000) { + *val = 0; + } else { + /* 5 bit value */ + *val = (tmp & 0x1f) << (sizeof(*val) * 8 - 5); + *val = ~*val; + *val &= 0x1f << (sizeof(*val) * 8 - 5); + } + break; + + default: + return -1; + } + + return 0; +} + +static int ac97_mixer_write(uint32_t knob_id, uint32_t val) { + switch (knob_id) { + case SND_KNOB_MASTER: { + uint16_t encoded; + if (val == 0x0) { + encoded = 0x8000; + } else { + /* 0 is the highest volume */ + val = ~val; + /* 6 bit value */ + val >>= (sizeof(val) * 8 - _device.bits); + encoded = (val & 0xFF) | (val << 8); + } + outports(_device.nambar + AC97_MASTER_VOLUME, encoded); + break; + } + + case AC97_KNOB_PCM_OUT: { + uint16_t encoded; + if (val == 0x0) { + encoded = 0x8000; + } else { + /* 0 is the highest volume */ + val = ~val; + /* 5 bit value */ + val >>= (sizeof(val) * 8 - 5); + encoded = (val & 0xFF) | (val << 8); + } + outports(_device.nambar + AC97_PCM_OUT_VOLUME, encoded); + break; + } + + default: + return -1; + } + + return 0; +} + +int ac97_install(int argc, char * argv[]) { + //debug_print(NOTICE, "Initializing AC97"); + + pci_scan(&find_ac97, -1, &_device); + if (!_device.pci_device) { + return -ENODEV; + } + dprintf("ac97: device located...\n"); + + pci_write_field(_device.pci_device, PCI_COMMAND, 2, 0x5); + + pci_write_field(_device.pci_device, AC97_NABMBAR, 2, 0x1001); + pci_write_field(_device.pci_device, PCI_BAR0, 4, 0x2001); + + _device._iobase = (volatile char *)mmu_map_mmio_region(0x3eff0000, 0x3000); + + asm volatile ("isb" ::: "memory"); + + _device.nabmbar = pci_read_field(_device.pci_device, AC97_NABMBAR, 2) & ((uint32_t) -1) << 1; + _device.nambar = pci_read_field(_device.pci_device, PCI_BAR0, 4) & ((uint32_t) -1) << 1; + + dprintf("nabmbar = %#x\n", _device.nabmbar); + dprintf("nambar = %#x\n", _device.nambar); + + int irq; + gic_map_pci_interrupt("ac97",_device.pci_device,&irq,ac97_irq_handler,&_device); + _device.irq = irq; + + + dprintf("global control = %#x\n", inportl(_device.nabmbar + 0x2C)); + + //pci_get_interrupt(_device.pci_device); + //printf("device wants irq %zd\n", _device.irq); + //irq_install_handler(_device.irq, ac97_irq_handler, "ac97"); + /* Enable all matter of interrupts */ + outportb(_device.nabmbar + AC97_PO_CR, AC97_X_CR_FEIE | AC97_X_CR_IOCE); + + /* Enable bus mastering and disable memory mapped space */ + pci_write_field(_device.pci_device, PCI_COMMAND, 2, 0x5); + /* Default the PCM output to full volume. */ + outports(_device.nambar + AC97_PCM_OUT_VOLUME, 0x0000); + + /* Allocate our BDL and our buffers */ + _device.bdl_p = mmu_allocate_a_frame() << 12; + _device.bdl = mmu_map_from_physical(_device.bdl_p); + memset(_device.bdl, 0, AC97_BDL_LEN * sizeof(*_device.bdl)); + + for (int i = 0; i < AC97_BDL_LEN; i++) { + _device.bdl[i].pointer = mmu_allocate_n_frames(2) << 12; + _device.bufs[i] = mmu_map_from_physical(_device.bdl[i].pointer); + memset(_device.bufs[i], 0, AC97_BDL_BUFFER_LEN * sizeof(*_device.bufs[0])); + AC97_CL_SET_LENGTH(_device.bdl[i].cl, AC97_BDL_BUFFER_LEN); + /* Set all buffers to interrupt */ + _device.bdl[i].cl |= AC97_CL_IOC; + + } + /* Tell the ac97 where our BDL is */ + outportl(_device.nabmbar + AC97_PO_BDBAR, _device.bdl_p); + /* Set the LVI to be the last index */ + _device.lvi = 2; + outportb(_device.nabmbar + AC97_PO_LVI, _device.lvi); + + /* detect whether device supports MSB */ + outports(_device.nambar + AC97_MASTER_VOLUME, 0x2020); + uint16_t t = inports(_device.nambar + AC97_MASTER_VOLUME) & 0x1f; + if (t == 0x1f) { + //debug_print(WARNING, "This device only supports 5 bits of audio volume."); + _device.bits = 5; + _device.mask = 0x1f; + } else { + _device.bits = 6; + _device.mask = 0x3f; + } + outports(_device.nambar + AC97_MASTER_VOLUME, 0x2f2f); + + snd_register(&_snd); + + /* Start things playing */ + outportb(_device.nabmbar + AC97_PO_CR, inportb(_device.nabmbar + AC97_PO_CR) | AC97_X_CR_RPBM); + + //debug_print(NOTICE, "AC97 initialized successfully"); + + return 0; +} + +#if 0 +static int fini(void) { + snd_unregister(&_snd); + + free(_device.bdl); + for (int i = 0; i < AC97_BDL_LEN; i++) { + free(_device.bufs[i]); + } + return 0; +} + +struct Module metadata = { + .name = "ac97", + .init = ac97_install, + .fini = fini, +}; + +#endif diff --git a/kernel/arch/aarch64/e1000_tmp.c b/kernel/arch/aarch64/e1000_tmp.c new file mode 100644 index 00000000..abc4800f --- /dev/null +++ b/kernel/arch/aarch64/e1000_tmp.c @@ -0,0 +1,623 @@ +/** + * @file kernel/net/e1000.c + * @brief Intel Gigabit Ethernet device driver + * @package x86_64 + * + * @copyright + * This file is part of ToaruOS and is released under the terms + * of the NCSA / University of Illinois License - see LICENSE.md + * Copyright (C) 2017-2021 K. Lange + * + * @ref https://www.intel.com/content/dam/www/public/us/en/documents/manuals/pcie-gbe-controllers-open-source-manual.pdf + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define INTS (ICR_LSC | ICR_RXO | ICR_RXT0 | ICR_TXQE | ICR_TXDW | ICR_ACK | ICR_RXDMT0 | ICR_SRPD) + +struct e1000_nic { + struct EthernetDevice eth; + uint32_t pci_device; + uint16_t deviceid; + uintptr_t mmio_addr; + int irq_number; + + int has_eeprom; + int rx_index; + int tx_index; + int link_status; + + spin_lock_t tx_lock; + + uint8_t * rx_virt[E1000_NUM_RX_DESC]; + uint8_t * tx_virt[E1000_NUM_TX_DESC]; + volatile struct e1000_rx_desc * rx; + volatile struct e1000_tx_desc * tx; + uintptr_t rx_phys; + uintptr_t tx_phys; + + int configured; + process_t * queuer; + + netif_counters_t counts; +}; + +static int device_count = 0; +static struct e1000_nic * devices[32] = {NULL}; + +static uint32_t mmio_read32(uintptr_t addr) { + asm volatile ("dc ivac, %0\ndsb sy\nisb\n" :: "r"(addr) : "memory"); + uint32_t res = *((volatile uint32_t*)(addr)); + asm volatile ("dmb ish" ::: "memory"); + return res; +} +static void mmio_write32(uintptr_t addr, uint32_t val) { + (*((volatile uint32_t*)(addr))) = val; + asm volatile ("dsb ishst\nisb\ndc cvac, %0\n" :: "r"(addr) : "memory"); +} + +static void write_command(struct e1000_nic * device, uint16_t addr, uint32_t val) { + mmio_write32(device->mmio_addr + addr, val); +} + +static uint32_t read_command(struct e1000_nic * device, uint16_t addr) { + return mmio_read32(device->mmio_addr + addr); +} + +static void delay_yield(size_t subticks) { + asm volatile ("isb" ::: "memory"); + unsigned long s, ss; + relative_time(0, subticks, &s, &ss); + sleep_until((process_t *)this_core->current_process, s, ss); + switch_task(0); +} + +static int eeprom_detect(struct e1000_nic * device) { + + /* Definitely not */ + if (device->deviceid == 0x10d3) return 0; + + write_command(device, E1000_REG_EEPROM, 1); + + for (int i = 0; i < 10000 && !device->has_eeprom; ++i) { + uint32_t val = read_command(device, E1000_REG_EEPROM); + if (val & 0x10) device->has_eeprom = 1; + } + + return 0; +} + +static uint16_t eeprom_read(struct e1000_nic * device, uint8_t addr) { + uint32_t temp = 0; + write_command(device, E1000_REG_EEPROM, 1 | ((uint32_t)(addr) << 8)); + while (!((temp = read_command(device, E1000_REG_EEPROM)) & (1 << 4))); + return (uint16_t)((temp >> 16) & 0xFFFF); +} + +static void write_mac(struct e1000_nic * device) { + uint32_t low, high; + memcpy(&low, &device->eth.mac[0], 4); + memcpy(&high,&device->eth.mac[4], 2); + memset((uint8_t *)&high + 2, 0, 2); + high |= 0x80000000; + write_command(device, E1000_REG_RXADDR + 0, low); + write_command(device, E1000_REG_RXADDR + 4, high); +} + +static void read_mac(struct e1000_nic * device) { + if (device->has_eeprom) { + uint32_t t; + t = eeprom_read(device, 0); + device->eth.mac[0] = t & 0xFF; + device->eth.mac[1] = t >> 8; + t = eeprom_read(device, 1); + device->eth.mac[2] = t & 0xFF; + device->eth.mac[3] = t >> 8; + t = eeprom_read(device, 2); + device->eth.mac[4] = t & 0xFF; + device->eth.mac[5] = t >> 8; + } else { + uint32_t mac_addr_low = *(uint32_t *)(device->mmio_addr + E1000_REG_RXADDR); + uint32_t mac_addr_high = *(uint32_t *)(device->mmio_addr + E1000_REG_RXADDR + 4); + device->eth.mac[0] = (mac_addr_low >> 0 ) & 0xFF; + device->eth.mac[1] = (mac_addr_low >> 8 ) & 0xFF; + device->eth.mac[2] = (mac_addr_low >> 16) & 0xFF; + device->eth.mac[3] = (mac_addr_low >> 24) & 0xFF; + device->eth.mac[4] = (mac_addr_high>> 0 ) & 0xFF; + device->eth.mac[5] = (mac_addr_high>> 8 ) & 0xFF; + } +} + +static void e1000_handle(struct e1000_nic * nic, uint32_t status) { + write_command(nic, E1000_REG_ICR, status); + + if (!nic->configured) { + return; + } + + if (status & ICR_LSC) { + nic->link_status= (read_command(nic, E1000_REG_STATUS) & (1 << 1)); + } + + make_process_ready(nic->queuer); +} + +static void cache_invalidate(void *addr) { + uintptr_t a = addr; + for (uintptr_t x = 0; x < 4096; x += 64) { + asm volatile ("dc ivac, %0\n" :: "r"(a + x) : "memory"); + } + asm volatile ("dsb sy\nisb":::"memory"); +} + +static void cache_clean(void *addr) { + uintptr_t a = addr; + asm volatile ("dmb ish" ::: "memory"); + for (uintptr_t x = 0; x < 4096; x += 64) { + asm volatile ("dc cvac, %0" :: "r"(a + x) : "memory"); + } + asm volatile ("dsb sy\nisb":::"memory"); +} + +void e1000_queuer(void * data) { + struct e1000_nic * nic = data; + + int head = read_command(nic, E1000_REG_RXDESCHEAD); + int budget = 8; + + while (1) { + int processed = 0; + if (head == nic->rx_index) { + head = read_command(nic, E1000_REG_RXDESCHEAD); + } + if (head != nic->rx_index) { + __sync_synchronize(); + while ((nic->rx[nic->rx_index].status & 0x01) && (processed < budget)) { + int i = nic->rx_index; + if (!(nic->rx[i].errors & (0x97))) { + //dprintf("%s: \033[1;33mrx id=%d len=%u\033[0m\n", nic->eth.if_name, i, nic->rx[i].length); + nic->counts.rx_count++; + nic->counts.rx_bytes += nic->rx[i].length; + cache_invalidate(nic->rx_virt[i]); + net_eth_handle((void*)nic->rx_virt[i], nic->eth.device_node, nic->rx[i].length); + } else { + dprintf("%s: error bits set in packet: %x\n", nic->eth.if_name, nic->rx[i].errors); + } + processed++; + __sync_synchronize(); + nic->rx[i].status = 0; + if (++nic->rx_index == E1000_NUM_RX_DESC) { + nic->rx_index = 0; + } + if (nic->rx_index == head) { + head = read_command(nic, E1000_REG_RXDESCHEAD); + if (nic->rx_index == head) break; + } + write_command(nic, E1000_REG_RXDESCTAIL, nic->rx_index); + read_command(nic, E1000_REG_STATUS); + __sync_synchronize(); + } + } + if (processed == 0) { + delay_yield(100000); + } else { + if (this_core->cpu_id == 0) switch_task(1); + } + } +} + +#if 0 +static int irq_handler(struct regs *r) { + int irq = r->int_no - 32; +#else +int e1000_irq_handler(process_t * this, int irq, void * data) { +#endif + int handled = 0; + + for (int i = 0; i < device_count; ++i) { + if (devices[i]->irq_number == irq) { + uint32_t status = read_command(devices[i], E1000_REG_ICR); + if (status) { + e1000_handle(devices[i], status); + if (!handled) { + handled = 1; + #if 0 + irq_ack(irq); + #endif + } + } + } + } + + return handled; +} + +static int tx_full(struct e1000_nic * device, int tx_tail, int tx_head) { + if (tx_tail == tx_head) return 0; + if (device->tx_index == tx_head) return 1; + if (((device->tx_index + 1) & E1000_NUM_TX_DESC) == tx_head) return 1; + return 0; +} + +static void send_packet(struct e1000_nic * device, uint8_t* payload, size_t payload_size) { + spin_lock(device->tx_lock); + int tx_tail = read_command(device, E1000_REG_TXDESCTAIL); + int tx_head = read_command(device, E1000_REG_TXDESCHEAD); + + if (tx_full(device, tx_tail, tx_head)) { + int timeout = 1000; + do { + spin_unlock(device->tx_lock); + delay_yield(10000); + timeout--; + if (timeout == 0) { + printf("e1000: wait for tx timed out, giving up\n"); + return; + } + spin_lock(device->tx_lock); + tx_tail = read_command(device, E1000_REG_TXDESCTAIL); + tx_head = read_command(device, E1000_REG_TXDESCHEAD); + } while (tx_full(device, tx_tail, tx_head)); + } + + //dprintf("%s: \033[1;31mtx id=%d len=%zu\033[0m\n", device->eth.if_name, device->tx_index, payload_size); + + int sent = device->tx_index; + memcpy(device->tx_virt[device->tx_index], payload, payload_size); + asm volatile ("dmb ish\nisb" ::: "memory"); + cache_clean(device->tx_virt[device->tx_index]); + + device->tx[device->tx_index].length = payload_size; + device->tx[device->tx_index].cmd = CMD_EOP | CMD_IFCS | CMD_RS | CMD_RPS; + device->tx[device->tx_index].status = 0; + asm volatile ("dmb ish\nisb" ::: "memory"); + + device->counts.tx_count++; + device->counts.tx_bytes += payload_size; + + if (++device->tx_index == E1000_NUM_TX_DESC) { + device->tx_index = 0; + } + + //dprintf("%s: write tx index %d\n", device->eth.if_name, device->tx_index); + //dprintf("tail goes from %d to %d while head was %d\n", tx_tail, device->tx_index, tx_head); + write_command(device, E1000_REG_TXDESCTAIL, device->tx_index); + int st = read_command(device, E1000_REG_STATUS); + //dprintf("%s: read status %#x\n", device->eth.if_name, st); + + #if 0 + while (read_command(device, E1000_REG_TXDESCHEAD) != device->tx_index) { + dprintf("%s: wait...\n", device->eth.if_name); + delay_yield(10000); + } + #endif + + asm volatile ("dc ivac, %0\ndsb sy\n" :: "r"(&device->tx[sent]) : "memory"); + //dprintf("%s: set %d status=%d\n", + // device->eth.if_name, + // sent, device->tx[sent].status); + + spin_unlock(device->tx_lock); +} + +static void init_rx(struct e1000_nic * device) { + write_command(device, E1000_REG_RXDESCLO, device->rx_phys); + write_command(device, E1000_REG_RXDESCHI, 0); + write_command(device, E1000_REG_RXDESCLEN, E1000_NUM_RX_DESC * sizeof(struct e1000_rx_desc)); + write_command(device, E1000_REG_RXDESCHEAD, 0); + write_command(device, E1000_REG_RXDESCTAIL, E1000_NUM_RX_DESC - 1); + + device->rx_index = 0; + + write_command(device, E1000_REG_RCTRL, + RCTL_EN | + (1 << 2) | /* store bad packets */ + (1 << 4) | /* multicast promiscuous */ + (1 << 15) | /* broadcast accept */ + (1 << 25) | /* Extended size... */ + (3 << 16) | /* 4096 */ + (1 << 26) /* strip CRC */ + ); +} + +static void init_tx(struct e1000_nic * device) { + write_command(device, E1000_REG_TXDESCLO, device->tx_phys); + write_command(device, E1000_REG_TXDESCHI, 0); + write_command(device, E1000_REG_TXDESCLEN, E1000_NUM_TX_DESC * sizeof(struct e1000_tx_desc)); + write_command(device, E1000_REG_TXDESCHEAD, 0); + write_command(device, E1000_REG_TXDESCTAIL, 0); + + device->tx_index = 0; + + uint32_t tctl = read_command(device, E1000_REG_TCTRL); + + /* Collision threshold */ + tctl &= ~(0xFF << 4); + tctl |= (15 << 4); + + /* Turn it on */ + tctl |= TCTL_EN; + tctl |= TCTL_PSP; + tctl |= (1 << 24); /* retransmit on late collision */ + + write_command(device, E1000_REG_TCTRL, tctl); +} + +static int ioctl_e1000(fs_node_t * node, unsigned long request, void * argp) { + struct e1000_nic * nic = node->device; + + switch (request) { + case SIOCGIFHWADDR: + /* fill argp with mac */ + memcpy(argp, nic->eth.mac, 6); + return 0; + + case SIOCGIFADDR: + if (nic->eth.ipv4_addr == 0) return -ENOENT; + memcpy(argp, &nic->eth.ipv4_addr, sizeof(nic->eth.ipv4_addr)); + return 0; + case SIOCSIFADDR: + memcpy(&nic->eth.ipv4_addr, argp, sizeof(nic->eth.ipv4_addr)); + return 0; + case SIOCGIFNETMASK: + if (nic->eth.ipv4_subnet == 0) return -ENOENT; + memcpy(argp, &nic->eth.ipv4_subnet, sizeof(nic->eth.ipv4_subnet)); + return 0; + case SIOCSIFNETMASK: + memcpy(&nic->eth.ipv4_subnet, argp, sizeof(nic->eth.ipv4_subnet)); + return 0; + case SIOCGIFGATEWAY: + if (nic->eth.ipv4_subnet == 0) return -ENOENT; + memcpy(argp, &nic->eth.ipv4_gateway, sizeof(nic->eth.ipv4_gateway)); + return 0; + case SIOCSIFGATEWAY: + memcpy(&nic->eth.ipv4_gateway, argp, sizeof(nic->eth.ipv4_gateway)); + net_arp_ask(nic->eth.ipv4_gateway, node); + return 0; + + case SIOCGIFADDR6: + return -ENOENT; + case SIOCSIFADDR6: + memcpy(&nic->eth.ipv6_addr, argp, sizeof(nic->eth.ipv6_addr)); + return 0; + + case SIOCGIFFLAGS: { + uint32_t * flags = argp; + *flags = IFF_RUNNING; + if (nic->link_status) *flags |= IFF_UP; + /* We turn these on in our init_tx */ + *flags |= IFF_BROADCAST; + *flags |= IFF_MULTICAST; + return 0; + } + + case SIOCGIFMTU: { + uint32_t * mtu = argp; + *mtu = nic->eth.mtu; + return 0; + } + + case SIOCGIFCOUNTS: { + memcpy(argp, &nic->counts, sizeof(netif_counters_t)); + return 0; + } + + default: + return -EINVAL; + } +} + +static ssize_t write_e1000(fs_node_t *node, off_t offset, size_t size, uint8_t *buffer) { + struct e1000_nic * nic = node->device; + /* write packet */ + send_packet(nic, buffer, size); + return size; +} + +static void ints_off(struct e1000_nic * nic) { + write_command(nic, E1000_REG_IMC, 0xFFFFFFFF); + write_command(nic, E1000_REG_ICR, 0xFFFFFFFF); + read_command(nic, E1000_REG_STATUS); +} + +void e1000_init(struct e1000_nic * nic) { + while (this_core->cpu_id != 0) switch_task(1); + uint32_t e1000_device_pci = nic->pci_device; + + nic->rx_phys = mmu_allocate_n_frames(2) << 12; + nic->rx = mmu_map_mmio_region(nic->rx_phys, 8192); + + nic->tx_phys = mmu_allocate_n_frames(2) << 12; + nic->tx = mmu_map_mmio_region(nic->tx_phys, 8192); + + memset(nic->rx, 0, sizeof(struct e1000_rx_desc) * E1000_NUM_RX_DESC); + memset(nic->tx, 0, sizeof(struct e1000_tx_desc) * E1000_NUM_TX_DESC); + + /* Allocate buffers */ + for (int i = 0; i < E1000_NUM_RX_DESC; ++i) { + nic->rx[i].addr = mmu_allocate_a_frame() << 12; + nic->rx_virt[i] = mmu_map_mmio_region(nic->rx[i].addr, 4096); + mmu_frame_map_address(mmu_get_page((uintptr_t)nic->rx_virt[i],0),MMU_FLAG_KERNEL|MMU_FLAG_WRITABLE,nic->rx[i].addr); + nic->rx[i].status = 0; + } + + for (int i = 0; i < E1000_NUM_TX_DESC; ++i) { + nic->tx[i].addr = mmu_allocate_a_frame() << 12; + nic->tx_virt[i] = mmu_map_mmio_region(nic->tx[i].addr, 4096); + mmu_frame_allocate(mmu_get_page((uintptr_t)nic->tx_virt[i],0),MMU_FLAG_KERNEL|MMU_FLAG_WRITABLE); + memset(nic->tx_virt[i], 0, 4096); + nic->tx[i].status = 0; + nic->tx[i].cmd = (1 << 0); + } + + uint16_t command_reg = pci_read_field(e1000_device_pci, PCI_COMMAND, 2); + command_reg = (1 << 1) | (1 << 2); + pci_write_field(e1000_device_pci, PCI_COMMAND, 2, command_reg); + dprintf("command_reg = %#x\n", command_reg); + + pci_write_field(e1000_device_pci, PCI_BAR0, 4, 0x12200000); + asm volatile ("isb" ::: "memory"); + + delay_yield(10000); + while (this_core->cpu_id != 0) switch_task(1); + + /* Is this size enough? */ + uint32_t initial_bar = pci_read_field(e1000_device_pci, PCI_BAR0, 4); + dprintf("initial_bar = %#x\n", initial_bar); + nic->mmio_addr = (uintptr_t)mmu_map_mmio_region(initial_bar, 0x20000); + asm volatile ("isb" ::: "memory"); + + eeprom_detect(nic); + read_mac(nic); + write_mac(nic); + + nic->queuer = (process_t*)this_core->current_process; + + #define CTRL_PHY_RST (1UL << 31UL) + #define CTRL_RST (1UL << 26UL) + #define CTRL_SLU (1UL << 6UL) + #define CTRL_LRST (1UL << 3UL) + + #if 0 + nic->irq_number = pci_get_interrupt(e1000_device_pci); + irq_install_handler(nic->irq_number, irq_handler, nic->eth.if_name); + #else + + int irq; + gic_map_pci_interrupt(nic->eth.if_name,e1000_device_pci,&irq,e1000_irq_handler,nic); + nic->irq_number = irq; + #endif + + /* Disable interrupts */ + ints_off(nic); + + /* Turn off receive + transmit */ + write_command(nic, E1000_REG_RCTRL, 0); + write_command(nic, E1000_REG_TCTRL, TCTL_PSP); + read_command(nic, E1000_REG_STATUS); + delay_yield(10000); + + /* Reset everything */ + uint32_t ctrl = read_command(nic, E1000_REG_CTRL); + ctrl |= CTRL_RST; + write_command(nic, E1000_REG_CTRL, ctrl); + delay_yield(20000); + + /* Turn off interrupts _again_ */ + ints_off(nic); + + /* Recommended flow control settings? */ + write_command(nic, 0x0028, 0x002C8001); + write_command(nic, 0x002c, 0x0100); + write_command(nic, 0x0030, 0x8808); + write_command(nic, 0x0170, 0xFFFF); + + /* Link up */ + uint32_t status = read_command(nic, E1000_REG_CTRL); + status |= CTRL_SLU; + status |= (2 << 8); /* Speed to gigabit... */ + status &= ~CTRL_LRST; + status &= ~CTRL_PHY_RST; + write_command(nic, E1000_REG_CTRL, status); + + /* Clear statistical counters */ + #if 0 + /* Why does this get mad at us? */ + for (int i = 0; i < 128; ++i) { + write_command(nic, 0x5200 + i * 4, 0); + } + + for (int i = 0; i < 64; ++i) { + read_command(nic, 0x4000 + i * 4); + } + #endif + + init_rx(nic); + init_tx(nic); + + write_command(nic, E1000_REG_RDTR, 0); + write_command(nic, E1000_REG_ITR, 500); + read_command(nic, E1000_REG_STATUS); + + nic->link_status = (read_command(nic, E1000_REG_STATUS) & (1 << 1)); + + nic->eth.device_node = calloc(sizeof(fs_node_t),1); + snprintf(nic->eth.device_node->name, 100, "%s", nic->eth.if_name); + nic->eth.device_node->flags = FS_BLOCKDEVICE; /* NETDEVICE? */ + nic->eth.device_node->mask = 0666; /* temporary; shouldn't be doing this with these device files */ + nic->eth.device_node->ioctl = ioctl_e1000; + nic->eth.device_node->write = write_e1000; + nic->eth.device_node->device = nic; + + nic->eth.mtu = 1500; /* guess */ + + net_add_interface(nic->eth.if_name, nic->eth.device_node); + + nic->configured = 1; + + /* Twiddle interrupts */ + write_command(nic, E1000_REG_IMS, INTS); + delay_yield(10000); + + e1000_queuer(nic); + + while (1) { + switch_task(0); + } +} + +static void find_e1000(uint32_t device, uint16_t vendorid, uint16_t deviceid, void * found) { + if ((vendorid == 0x8086) && (deviceid == 0x100e || deviceid == 0x1004 || deviceid == 0x100f || deviceid == 0x10ea || deviceid == 0x10d3)) { + dprintf("e1000: device found\n"); + /* Allocate a device */ + struct e1000_nic * nic = calloc(1,sizeof(struct e1000_nic)); + nic->pci_device = device; + nic->deviceid = deviceid; + devices[device_count++] = nic; + + snprintf(nic->eth.if_name, 31, + "enp%ds%d", + (int)pci_extract_bus(device), + (int)pci_extract_slot(device)); + + char worker_name[34]; + snprintf(worker_name, 33, "[%s]", nic->eth.if_name); + + spawn_worker_thread(e1000_init, worker_name, nic); + + *(int*)found = 1; + } +} + +int e1000_install(int argc, char * argv[]) { + uint32_t found = 0; + pci_scan(&find_e1000, -1, &found); + + if (!found) { + /* TODO: Clean up? Remove ourselves? */ + return -ENODEV; + } + + return 0; +} + diff --git a/kernel/arch/aarch64/main.c b/kernel/arch/aarch64/main.c index b072bfe3..1e9a59f9 100644 --- a/kernel/arch/aarch64/main.c +++ b/kernel/arch/aarch64/main.c @@ -633,18 +633,22 @@ int kmain(uintptr_t dtb_base, uintptr_t phys_base, uintptr_t rpi_tag) { /* Start other cores here */ if (!rpi_tag ){ aarch64_smp_start(); - } else { - extern void rpi_smp_init(void); - rpi_smp_init(); - } - if (!rpi_tag) { /* Install drivers that may need to sleep here */ virtio_input(); /* Set up serial input */ extern void pl011_start(void); pl011_start(); + + extern int ac97_install(int argc, char * argv[]); + ac97_install(0,NULL); + + extern int e1000_install(int argc, char * argv[]); + e1000_install(0,NULL); + } else { + extern void rpi_smp_init(void); + rpi_smp_init(); } generic_main();