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aarch64: smp: reorder barriers before enabling MMU

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This commit is contained in:
K. Lange 2022-02-03 17:48:51 +09:00
parent ff42fea697
commit 92ae583c5b
1 changed files with 11 additions and 3 deletions
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14
kernel/arch/aarch64/smp.c
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@ -92,6 +92,10 @@ void smp_bootstrap(void) {
/* Set up TTBR0 with our temporary directory */
"ldr x0, aarch64_ttbr0\n"
"msr TTBR0_EL1, x0\n"
"dsb ishst\n"
"tlbi vmalle1is\n"
"dsb ish\n"
"isb\n"
/* Load VBAR from first core */
"ldr x0, aarch64_vbar\n"
"msr VBAR_EL1, x0\n"
@ -105,9 +109,6 @@ void smp_bootstrap(void) {
"ldr x0, aarch64_sctlr\n"
"ldr x1, aarch64_jmp_target\n"
"msr SCTLR_EL1, x0\n"
"dsb ishst\n"
"tlbi vmalle1is\n"
"dsb ish\n"
"isb\n"
/* Restore core ID as argument */
"mov x0, x3\n"
@ -188,5 +189,12 @@ void aarch64_smp_start(void) {
aarch64_ttbr0 = mmu_map_to_physical(NULL, (uintptr_t)&startup_ttbr0[0]);
aarch64_ttbr1 = mmu_map_to_physical(NULL, (uintptr_t)mmu_get_kernel_directory());
asm volatile (
"dsb ishst\n"
"tlbi vmalle1is\n"
"dsb ish\n"
"isb\n"
);
dtb_callback_direct_children(cpus, start_cpu);
}