xhci: Basic initialization
This commit is contained in:
K. Lange
parent
e8dd8aa7cb
commit
7129db86dd
443
modules/xhci.c
443
modules/xhci.c
@ -10,6 +10,7 @@
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* of the NCSA / University of Illinois License - see LICENSE.md
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* Copyright (C) 2021 K. Lange
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*/
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#include <errno.h>
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#include <kernel/module.h>
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#include <kernel/printf.h>
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#include <kernel/types.h>
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@ -20,6 +21,20 @@
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#include <kernel/procfs.h>
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#include <kernel/syscall.h>
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static void delay_yield(size_t subticks) {
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#ifdef __aarch64__
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asm volatile ("dsb sy\nisb" ::: "memory");
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#endif
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unsigned long s, ss;
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relative_time(0, subticks, &s, &ss);
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sleep_until((process_t *)this_core->current_process, s, ss);
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switch_task(0);
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#ifdef __aarch64__
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asm volatile ("dmb sy\n" ::: "memory");
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#endif
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}
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struct xhci_cap_regs {
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volatile uint32_t cap_caplen_version;
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volatile uint32_t cap_hcsparams1;
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@ -31,61 +46,358 @@ struct xhci_cap_regs {
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volatile uint32_t cap_hccparams2;
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} __attribute__((packed));
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struct xhci_port_regs {
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volatile uint32_t port_status;
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volatile uint32_t port_pm_status;
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volatile uint32_t port_link_info;
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volatile uint32_t port_lpm_control;
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} __attribute__((packed));
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struct xhci_op_regs {
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volatile uint32_t op_usbcmd;
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volatile uint32_t op_usbsts;
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volatile uint32_t op_pagesize;
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volatile uint32_t op__pad1[2];
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volatile uint32_t op_dnctrl;
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volatile uint32_t op_crcr;
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volatile uint32_t op__pad2[5];
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volatile uint32_t op_dcbaap_lo;
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volatile uint32_t op_dcbaap_hi;
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volatile uint32_t op_config;
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volatile uint32_t op_usbcmd; /* 0 */
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volatile uint32_t op_usbsts; // 4
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volatile uint32_t op_pagesize; // 8h
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volatile uint32_t op__pad1[2]; // ch 10h
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volatile uint32_t op_dnctrl; // 14h
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volatile uint32_t op_crcr[2]; // 18h 1ch
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volatile uint32_t op__pad2[4]; // 20h 24h 28h 2ch
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volatile uint32_t op_dcbaap[2]; // 30h 34h
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volatile uint32_t op_config; // 38h
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volatile uint8_t op_more_padding[964]; // 3ch-400h
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struct xhci_port_regs op_portregs[256];
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} __attribute__((packed));
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struct xhci_trb {
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uint32_t trb_thing_a;
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uint32_t trb_thing_b;
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uint32_t trb_status;
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uint32_t trb_control;
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} __attribute__((packed));
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struct XHCIControllerData {
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uintptr_t mmio;
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uint32_t device;
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uint64_t pcie_offset;
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struct xhci_cap_regs * cregs;
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struct xhci_op_regs * oregs;
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process_t * thread;
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volatile struct xhci_trb * cr_trbs;
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volatile struct xhci_trb * er_trbs;
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spin_lock_t command_queue;
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uint32_t command_queue_cycle;
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int command_queue_enq;
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volatile uint32_t * doorbells;
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};
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static int _counter = 0;
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static uint64_t pci_addr_map(struct XHCIControllerData * controller, uint64_t addr) {
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return addr + controller->pcie_offset;
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}
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static ssize_t xhci_procfs_callback(fs_node_t * node, off_t offset, size_t size, uint8_t * buffer) {
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static uintptr_t pci_to_cpu(struct XHCIControllerData * controller, uint64_t addr) {
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return addr - controller->pcie_offset;
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}
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static uintptr_t allocate_page(uint64_t * phys_out) {
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uint64_t phys = mmu_allocate_a_frame() << 12;
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uintptr_t virt = (uintptr_t)mmu_map_mmio_region(phys, 4096);
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memset((void*)virt,0,4096);
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*phys_out = phys;
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return virt;
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}
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static int xhci_command(struct XHCIControllerData * controller, uint32_t p1, uint32_t p2, uint32_t status, uint32_t control) {
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spin_lock(controller->command_queue);
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control &= ~1;
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control |= controller->command_queue_cycle;
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controller->cr_trbs[controller->command_queue_enq].trb_thing_a = p1;
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controller->cr_trbs[controller->command_queue_enq].trb_thing_b = p2;
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controller->cr_trbs[controller->command_queue_enq].trb_status = status;
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controller->cr_trbs[controller->command_queue_enq].trb_control = control;
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controller->command_queue_enq++;
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if (controller->command_queue_enq == 63) {
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controller->cr_trbs[controller->command_queue_enq].trb_control ^= 1;
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if (controller->cr_trbs[controller->command_queue_enq].trb_control & (1 << 1)) {
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controller->command_queue_cycle ^= 1;
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}
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controller->command_queue_enq = 0;
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}
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/* ring doorbell */
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controller->doorbells[0] = 0;
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spin_unlock(controller->command_queue);
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return 0;
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}
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static ssize_t xhci_write(fs_node_t * node, off_t offset, size_t size, uint8_t * buffer) {
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struct XHCIControllerData * controller = node->device;
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char buf[2048];
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size_t _bsize = snprintf(buf, 2000,
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"%08x\n"
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"0x%016zx\n"
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"CAPLENGTH 0x%08x\n"
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"HCSPARAMS1 0x%08x\n"
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"HCSPARAMS2 0x%08x\n"
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"HCSPARAMS3 0x%08x\n"
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"HCCPARAMS1 0x%08x\n"
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"DBOFF 0x%08x\n"
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"RTSOFF 0x%08x\n"
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"HCCPARAMS2 0x%08x\n"
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,
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controller->device,
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(uintptr_t)controller->mmio,
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controller->cregs->cap_caplen_version,
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controller->cregs->cap_hcsparams1,
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controller->cregs->cap_hcsparams2,
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controller->cregs->cap_hcsparams3,
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controller->cregs->cap_hccparams1,
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controller->cregs->cap_dboff,
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controller->cregs->cap_rtsoff,
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controller->cregs->cap_hccparams2
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);
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if (size != sizeof(struct xhci_trb)) return -EINVAL;
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if ((size_t)offset > _bsize) return 0;
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if (size > _bsize - offset) size = _bsize - offset;
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struct xhci_trb * data = (void*)buffer;
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memcpy(buffer, buf + offset, size);
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return size;
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xhci_command(controller, data->trb_thing_a, data->trb_thing_b, data->trb_status, data->trb_control);
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return sizeof(struct xhci_trb);
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}
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static struct XHCIControllerData * _irq_owner = NULL;
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#include <kernel/arch/x86_64/irq.h>
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static int irq_handler(struct regs *r) {
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int irq = r->int_no - 32;
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if (_irq_owner) {
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/* Is it ours? */
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uint32_t status = _irq_owner->oregs->op_usbsts;
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if (status & (1 << 3)) {
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_irq_owner->oregs->op_usbsts = (1 << 3);
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dprintf("xhci: irq\n");
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uintptr_t rts = (uintptr_t)_irq_owner->cregs + _irq_owner->cregs->cap_rtsoff;
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volatile uint32_t * irs0_32 = (uint32_t*)(rts + 0x20);
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irs0_32[0] |= 1;
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make_process_ready(_irq_owner->thread);
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irq_ack(irq);
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return 1;
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}
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}
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return 0;
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}
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void xhci_thread(void * arg) {
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struct XHCIControllerData * controller = arg;
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controller->thread = (process_t*)this_core->current_process;
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spin_init(controller->command_queue);
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/* Begin generic XHCi */
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dprintf("xhci: available slots: %d\n", controller->cregs->cap_hcsparams1 & 0xFF);
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dprintf("xhci: available ports: %d\n", controller->cregs->cap_hcsparams1 >> 24);
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dprintf("xhci: resetting controller\n");
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dprintf("xhci: waiting for controller to stop...\n");
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uint32_t cmd = controller->oregs->op_usbcmd;
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cmd &= ~(1);
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controller->oregs->op_usbcmd = cmd;
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while (!(controller->oregs->op_usbsts & (1 << 0)));
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dprintf("xhci: restarting controller...\n");
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cmd = controller->oregs->op_usbcmd;
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cmd |= (1 << 1);
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controller->oregs->op_usbcmd = cmd;
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while ((controller->oregs->op_usbcmd & (1 << 1)));
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while ((controller->oregs->op_usbsts & (1 << 11)));
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dprintf("xhci: controller is ready: %#x\n", controller->oregs->op_usbsts);
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dprintf("xhci: slot config %#x -> %#x\n",
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controller->oregs->op_config, controller->cregs->cap_hcsparams1 & 0xFF);
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controller->oregs->op_config = controller->cregs->cap_hcsparams1 & 0xFF;
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/* TODO We may need to clear interrupts here by writing status back */
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uint32_t sts = controller->oregs->op_usbsts;
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(void)sts;
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dprintf("xhci: context size is %d\n",
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(controller->cregs->cap_hccparams1 & (1 << 2)) ? 64 : 32);
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uintptr_t ext_off = (controller->cregs->cap_hccparams1 >> 16) << 2;
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volatile uint32_t * ext_caps = (void*)((uintptr_t)controller->cregs + ext_off);
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/**
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* Verify port configurations;
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* should be port 1 is usb 2.0
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* port 2, 3, 4, 5 are 3.0
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* port 1 has a hub with 4 ports?
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*/
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while (1) {
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uint32_t cap_val = *ext_caps;
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dprintf("xhci: ecap = %#x\n", cap_val);
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/* Bottom byte is type */
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if ((cap_val & 0xFF) == 2) {
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uint8_t rev_minor = ext_caps[0] >> 16;
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uint8_t rev_major = ext_caps[0] >> 24;
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//uint32_t name_str = ext_caps[1];
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uint8_t port_offset = ext_caps[2];
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uint8_t port_count = ext_caps[2] >> 8;
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uint8_t psic = ext_caps[2] >> 28;
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dprintf("xhci: protocol %d.%d %d port%s starting from port %d has %d speed%s\n",
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rev_major, rev_minor,
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port_count, &"s"[port_count==1],
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port_offset,
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psic, &"s"[psic==1]);
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}
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if (cap_val == 0xFFFFffff) break;
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if ((cap_val & 0xFF00) == 0) break;
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ext_caps = (void*)((uintptr_t)ext_caps + ((cap_val & 0xFF00) >> 6));
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}
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/* Device Context Base Address Array */
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uint64_t dcbaap;
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uint64_t * baseCtx = (void*)allocate_page(&dcbaap);
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dprintf("xhci: DCBAAP at %#zx (phys=%#zx)\n", (uintptr_t)baseCtx, dcbaap);
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controller->oregs->op_dcbaap[0] = pci_addr_map(controller, dcbaap);
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controller->oregs->op_dcbaap[1] = pci_addr_map(controller, dcbaap) >> 32;
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/* Enable slots */
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uint32_t cfg = controller->oregs->op_config;
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cfg &= ~0xFF;
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cfg |= 32;
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dprintf("xhci: set cfg = %#x\n", cfg);
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controller->oregs->op_config = cfg;
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/* trbs for event ring */
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uint64_t er_trbs_phys;
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void * er_trbs_virt = (void*)allocate_page(&er_trbs_phys);
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dprintf("xhci: er trbs = %#zx (phys=%#zx)\n",
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(uintptr_t)er_trbs_virt, er_trbs_phys);
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/* erst */
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uint64_t er_erst_phys;
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void * er_erst_virt = (void*)allocate_page(&er_erst_phys);
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dprintf("xhci: er erst = %#zx (phys=%#zx)\n",
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(uintptr_t)er_erst_virt, er_erst_phys);
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((volatile uint64_t*)er_erst_virt)[0] = pci_addr_map(controller, er_trbs_phys);
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((volatile uint64_t*)er_erst_virt)[1] = 64;
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dprintf("xhci: rtsoff = %#x\n", controller->cregs->cap_rtsoff);
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uintptr_t rts = (uintptr_t)controller->cregs + controller->cregs->cap_rtsoff;
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/* Interrupter points to event ring */
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volatile uint32_t * irs0_32 = (uint32_t*)(rts + 0x20);
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irs0_32[2] = 1; /* Size = 1 */
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irs0_32[6] = pci_addr_map(controller, er_trbs_phys) | (1 << 3);
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irs0_32[7] = (pci_addr_map(controller, er_trbs_phys) | (1 << 3)) >> 32;
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irs0_32[1] = 500; /* IMOD */
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irs0_32[0] = 2; /* enable interrupts */
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irs0_32[4] = pci_addr_map(controller, er_erst_phys);
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irs0_32[5] = pci_addr_map(controller, er_erst_phys) >> 32;
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/* trbs for control ring */
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uint64_t cr_trbs_phys;
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void * cr_trbs_virt = (void*)allocate_page(&cr_trbs_phys);
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((volatile uint64_t*)cr_trbs_virt)[63*2] = pci_addr_map(controller, cr_trbs_phys);
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((volatile uint64_t*)cr_trbs_virt)[63*2+1] = ((0x2UL | (6UL << 10)) << 32);
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controller->oregs->op_crcr[0] = (pci_addr_map(controller, cr_trbs_phys) | 1);
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controller->oregs->op_crcr[1] = (pci_addr_map(controller, cr_trbs_phys) | 1) >> 32;
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/* Scratchpad buffers, if needed */
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uint32_t hcs2 = controller->cregs->cap_hcsparams2;
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uint32_t sb_hi = (hcs2 >> 21) & 0x1f;
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uint32_t sb_lo = (hcs2 >> 27) & 0x1f;
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uint32_t sb_max = (sb_hi << 5) | sb_lo;
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/* should be 31 */
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if (sb_max) {
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dprintf("num scratchpad buffers = %u\n", sb_max);
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/* Allocate buffer for array */
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uint64_t scratch_phys;
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uint64_t *scratch_virt = (uint64_t*)allocate_page(&scratch_phys);
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dprintf("xhci: scratch at %#zx (phys=%#zx)\n", (uintptr_t)scratch_virt, scratch_phys);
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/* Our DMA mapping should be 1:1, so, uh, yolo */
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for (unsigned int i = 0; i < sb_max; ++i) {
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uint64_t sb_phys;
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allocate_page(&sb_phys);
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scratch_virt[i] = pci_addr_map(controller, sb_phys);
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}
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baseCtx[0] = pci_addr_map(controller, scratch_phys);
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dprintf("xhci: assigned scratchpad buffer array\n");
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}
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/* TODO This irq API sucks */
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int irq_number = pci_get_interrupt(controller->device);
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irq_install_handler(irq_number, irq_handler, "xhci");
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_irq_owner = controller;
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dprintf("xhci: Starting command ring...\n");
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{
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uint32_t cmd = controller->oregs->op_usbcmd;
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dprintf("cmd before = %#x\n", cmd);
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cmd |= (1 << 0) | (1 << 2);
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controller->oregs->op_usbcmd = cmd;
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}
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dprintf("xhci: status = %#x\n", controller->oregs->op_usbsts);
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delay_yield(50000);
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dprintf("xhci: status = %#x\n", controller->oregs->op_usbsts);
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if (controller->oregs->op_usbsts & (1 << 2)) goto _bail;
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dprintf("xhci: doorbells at %#x\n", controller->cregs->cap_dboff);
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controller->doorbells = (void*)((uintptr_t)controller->cregs + controller->cregs->cap_dboff);
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/* Just want to enable the hub for now, see if we can id it */
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controller->cr_trbs = cr_trbs_virt;
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controller->er_trbs = er_trbs_virt;
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controller->command_queue_cycle = 1;
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controller->command_queue_enq = 0;
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dprintf("xhci: status before ring = %#x\n", controller->oregs->op_usbsts);
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xhci_command(controller, 0, 0, 0, (23 << 10));
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char devName[20] = "/dev/xhciN";
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snprintf(devName, 19, "/dev/xhci%d", 0);
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fs_node_t * fnode = calloc(sizeof(fs_node_t), 1);
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snprintf(fnode->name, 100, "xhci%d", 0);
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fnode->flags = FS_BLOCKDEVICE;
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fnode->mask = 0660; /* Only accessible to root user/group */
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fnode->read = NULL;
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fnode->write = xhci_write;
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fnode->device = controller;
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vfs_mount(devName, fnode);
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int event_deq = 0;
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uint32_t event_cycle_state = 1;
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while (1) {
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while ((controller->er_trbs[event_deq].trb_control & 1) != event_cycle_state) {
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switch_task(0);
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}
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uint32_t thing_a = controller->er_trbs[event_deq].trb_thing_a;
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uint32_t thing_b = controller->er_trbs[event_deq].trb_thing_a;
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uint32_t status = controller->er_trbs[event_deq].trb_status;
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uint32_t control = controller->er_trbs[event_deq].trb_control;
|
||||
|
||||
dprintf("xhci: event %d [%#x %#x %#x %#x]\n",
|
||||
event_deq, thing_a, thing_b, status, control);
|
||||
|
||||
event_deq++;
|
||||
if (event_deq == 64) {
|
||||
event_deq = 0;
|
||||
event_cycle_state = !event_cycle_state;
|
||||
}
|
||||
|
||||
/* Write new event dequeue pointer */
|
||||
uint64_t new_deq_phys = pci_addr_map(controller, er_trbs_phys + sizeof(struct xhci_trb) * event_deq) | (1 << 3);
|
||||
irs0_32[6] = new_deq_phys;
|
||||
irs0_32[7] = new_deq_phys >> 32;
|
||||
}
|
||||
|
||||
_bail:
|
||||
task_exit(1);
|
||||
__builtin_unreachable();
|
||||
}
|
||||
|
||||
static void find_xhci(uint32_t device, uint16_t v, uint16_t d, void * extra) {
|
||||
@ -124,56 +436,9 @@ static void find_xhci(uint32_t device, uint16_t v, uint16_t d, void * extra) {
|
||||
controller->mmio = mmio_addr;
|
||||
controller->cregs = (struct xhci_cap_regs*)xhci_regs;
|
||||
controller->oregs = (struct xhci_op_regs*)(xhci_regs + (controller->cregs->cap_caplen_version & 0xFF));
|
||||
controller->pcie_offset = 0;
|
||||
|
||||
fprintf(stderr, "xhci: available slots: %d\n", controller->cregs->cap_hcsparams1 & 0xFF);
|
||||
fprintf(stderr, "xhci: available ports: %d\n", controller->cregs->cap_hcsparams1 >> 24);
|
||||
fprintf(stderr, "xhci: resetting controller\n");
|
||||
fprintf(stderr, "xhci: waiting for controller to stop...\n");
|
||||
controller->oregs->op_usbcmd = 0;
|
||||
while (!(controller->oregs->op_usbsts & (1 << 0)));
|
||||
|
||||
fprintf(stderr, "xhci: restarting controller...\n");
|
||||
controller->oregs->op_usbcmd = (1 << 1);
|
||||
while ((controller->oregs->op_usbcmd & (1 << 1)));
|
||||
while ((controller->oregs->op_usbsts & (1 << 11)));
|
||||
fprintf(stderr, "xhci: controller is ready.\n");
|
||||
|
||||
fprintf(stderr, "xhci: slot config %#x -> %#x\n",
|
||||
controller->oregs->op_config, controller->cregs->cap_hcsparams1 & 0xFF);
|
||||
controller->oregs->op_config = controller->cregs->cap_hcsparams1 & 0xFF;
|
||||
|
||||
fprintf(stderr, "xhci: clearing interrupts?\n");
|
||||
uint32_t sts = controller->oregs->op_usbsts;
|
||||
controller->oregs->op_usbsts = sts;
|
||||
controller->oregs->op_dnctrl = 0;
|
||||
|
||||
fprintf(stderr, "xhci: context size is %d\n",
|
||||
(controller->cregs->cap_hccparams1 & (1 << 1)) ? 64 : 32);
|
||||
|
||||
uintptr_t dcbaap = mmu_allocate_n_frames(1) << 12;
|
||||
|
||||
char * baseCtx = mmu_map_mmio_region(dcbaap, 0x1000);
|
||||
memset(baseCtx, 0, 0x1000);
|
||||
|
||||
controller->oregs->op_dcbaap_lo = dcbaap & 0xFFFFFFFF;
|
||||
controller->oregs->op_dcbaap_hi = dcbaap >> 32UL;
|
||||
controller->oregs->op_dcbaap_lo = dcbaap & 0xFFFFFFFF;
|
||||
controller->oregs->op_dcbaap_hi = dcbaap >> 32UL;
|
||||
|
||||
|
||||
|
||||
|
||||
char devName[20] = "/dev/xhciN";
|
||||
snprintf(devName, 19, "/dev/xhci%d", _counter);
|
||||
fs_node_t * fnode = calloc(sizeof(fs_node_t), 1);
|
||||
snprintf(fnode->name, 100, "xhci%d", _counter);
|
||||
fnode->flags = FS_BLOCKDEVICE;
|
||||
fnode->mask = 0660; /* Only accessible to root user/group */
|
||||
fnode->read = xhci_procfs_callback;
|
||||
fnode->device = controller;
|
||||
vfs_mount(devName, fnode);
|
||||
|
||||
_counter++;
|
||||
spawn_worker_thread(xhci_thread, "[xhci]", controller);
|
||||
}
|
||||
|
||||
static int init(int argc, char * argv[]) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user