i965: Send mode change signal?
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@ -22,5 +22,6 @@ extern uint16_t lfb_resolution_y;
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extern uint16_t lfb_resolution_b;
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extern uint16_t lfb_resolution_b;
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extern uint8_t * lfb_vid_memory;
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extern uint8_t * lfb_vid_memory;
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extern const char * lfb_driver_name;
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extern const char * lfb_driver_name;
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extern void (*lfb_resolution_impl)(uint16_t,uint16_t);
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extern int framebuffer_initialize(void);
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extern int framebuffer_initialize(void);
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#endif
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#endif
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@ -49,7 +49,7 @@ static int lfb_init(const char * c);
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static pid_t display_change_recipient = 0;
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static pid_t display_change_recipient = 0;
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/* Driver-specific modesetting function */
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/* Driver-specific modesetting function */
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static void (*lfb_resolution_impl)(uint16_t,uint16_t) = NULL;
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void (*lfb_resolution_impl)(uint16_t,uint16_t) = NULL;
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/* Called by ioctl on /dev/fb0 */
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/* Called by ioctl on /dev/fb0 */
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void lfb_set_resolution(uint16_t x, uint16_t y) {
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void lfb_set_resolution(uint16_t x, uint16_t y) {
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@ -42,6 +42,34 @@ static void split(uint32_t val, uint32_t * a, uint32_t * b) {
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*b = (val >> 16) + 1;
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*b = (val >> 16) + 1;
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}
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}
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static void i965_modeset(uint16_t x, uint16_t y) {
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/* Disable pipe A while we update source size */
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uint32_t pipe = i965_mmio_read(REG_PIPEACONF);
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i965_mmio_write(REG_PIPEACONF, pipe & ~PIPEACONF_ENABLE);
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while (i965_mmio_read(REG_PIPEACONF) & PIPEACONF_STATE);
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/* Set source size */
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i965_mmio_write(REG_PIPEASRC, ((x - 1) << 16) | (y - 1));
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/* Re-enable pipe */
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pipe = i965_mmio_read(REG_PIPEACONF);
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i965_mmio_write(REG_PIPEACONF, pipe | PIPEACONF_ENABLE);
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while (!(i965_mmio_read(REG_PIPEACONF) & PIPEACONF_STATE));
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/* Keep the plane enabled while we update stride value */
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i965_mmio_write(REG_DSPALINOFF, 0); /* offset to default of 0 */
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i965_mmio_write(REG_DSPASTRIDE, x * 4); /* stride to 4 x width */
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i965_mmio_write(REG_DSPASURF, 0); /* write to surface address triggers change; use default of 0 */
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/* Update the values we expose to userspace. */
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lfb_resolution_x = x;
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lfb_resolution_y = y;
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lfb_resolution_b = 32;
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lfb_resolution_s = i965_mmio_read(REG_DSPASTRIDE);
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lfb_device->length = lfb_resolution_s * lfb_resolution_y;
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}
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static void setup_framebuffer(uint32_t pcidev) {
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static void setup_framebuffer(uint32_t pcidev) {
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/* Map BAR space for the control registers */
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/* Map BAR space for the control registers */
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uint32_t ctrl_space = pci_read_field(pcidev, PCI_BAR0, 4);
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uint32_t ctrl_space = pci_read_field(pcidev, PCI_BAR0, 4);
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@ -52,30 +80,8 @@ static void setup_framebuffer(uint32_t pcidev) {
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ctrl_space &= 0xFFFFFF00;
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ctrl_space &= 0xFFFFFF00;
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ctrl_regs = (uintptr_t)mmu_map_mmio_region(ctrl_space, ctrl_size);
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ctrl_regs = (uintptr_t)mmu_map_mmio_region(ctrl_space, ctrl_size);
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/* Disable pipe A while we update source size */
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lfb_resolution_impl = i965_modeset;
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uint32_t pipe = i965_mmio_read(REG_PIPEACONF);
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lfb_set_resolution(1440,900);
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i965_mmio_write(REG_PIPEACONF, pipe & ~PIPEACONF_ENABLE);
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while (i965_mmio_read(REG_PIPEACONF) & PIPEACONF_STATE);
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/* Set source size */
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i965_mmio_write(REG_PIPEASRC, ((1440 - 1) << 16) | (900 - 1));
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/* Re-enable pipe */
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pipe = i965_mmio_read(REG_PIPEACONF);
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i965_mmio_write(REG_PIPEACONF, pipe | PIPEACONF_ENABLE);
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while (!(i965_mmio_read(REG_PIPEACONF) & PIPEACONF_STATE));
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/* Keep the plane enabled while we update stride value */
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i965_mmio_write(REG_DSPALINOFF, 0); /* offset to default of 0 */
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i965_mmio_write(REG_DSPASTRIDE, 1440 * 4); /* stride to 4 x width */
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i965_mmio_write(REG_DSPASURF, 0); /* write to surface address triggers change; use default of 0 */
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/* Update the values we expose to userspace. */
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lfb_resolution_x = 1440;
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lfb_resolution_y = 900;
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lfb_resolution_b = 32;
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lfb_resolution_s = i965_mmio_read(REG_DSPASTRIDE);
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lfb_device->length = lfb_resolution_s * lfb_resolution_y;
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}
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}
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static void find_intel(uint32_t device, uint16_t v, uint16_t d, void * extra) {
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static void find_intel(uint32_t device, uint16_t v, uint16_t d, void * extra) {
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