aarch64: Fixup cpuinfo, improve cpu-name

This commit is contained in:
K. Lange 2022-02-02 13:22:20 +09:00
parent 79bd90e44c
commit 10010578bf
2 changed files with 24 additions and 2 deletions

View File

@ -22,4 +22,25 @@ for line in lines:
if cpus and 'Model name' in cpus[0]: if cpus and 'Model name' in cpus[0]:
print(cpus[0]['Model name']) print(cpus[0]['Model name'])
else if cpus and 'PartNum' in cpus[0]: else if cpus and 'PartNum' in cpus[0]:
print('(ARM64)', cpus[0]['PartNum']) # ARM
let manuf = {
0x41: 'ARM',
0x61: 'Apple',
}
let parts = {
0xD02: 'Cortex-A34',
0xD03: 'Cortex-A53',
0xD04: 'Cortex-A35',
0xD05: 'Cortex-A55',
0xD07: 'Cortex-A57',
0xD08: 'Cortex-A72',
0xD09: 'Cortex-A73',
# Apple stuff
0x022: 'M1', # Icestorm core
0x023: 'M1', # Firestorm core
}
print(
manuf.get(int(cpus[0]['Implementer']),cpus[0]['Implementer']),
parts.get(int(cpus[0]['PartNum']),cpus[0]['PartNum'])
)

View File

@ -286,6 +286,7 @@ static ssize_t cpuinfo_func(fs_node_t *node, off_t offset, size_t size, uint8_t
} }
#elif defined(__aarch64__) #elif defined(__aarch64__)
/* TODO store MIDR per-cpu, so we can show different cores. */
uint64_t midr; uint64_t midr;
asm volatile ("mrs %0, MIDR_EL1" : "=r"(midr)); asm volatile ("mrs %0, MIDR_EL1" : "=r"(midr));
@ -299,7 +300,7 @@ static ssize_t cpuinfo_func(fs_node_t *node, off_t offset, size_t size, uint8_t
(unsigned int)(midr >> 24) & 0xFF, (unsigned int)(midr >> 24) & 0xFF,
(unsigned int)(midr >> 20) & 0xF, (unsigned int)(midr >> 20) & 0xF,
(unsigned int)(midr >> 16) & 0xF, (unsigned int)(midr >> 16) & 0xF,
(unsigned int)(midr >> 4) & 0xFFFF, (unsigned int)(midr >> 4) & 0xFFF,
(unsigned int)(midr >> 0) & 0xF (unsigned int)(midr >> 0) & 0xF
); );
#endif #endif