2021-05-31 04:47:02 +03:00
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.section .text
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.align 8
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.macro IRQ index byte
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.global _irq\index
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.type _irq\index, @function
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_irq\index:
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pushq $0x00
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pushq $\byte
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jmp isr_common
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.endm
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.macro ISR_NOERR index
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.global _isr\index
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.type _isr\index, @function
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_isr\index:
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pushq $0x00
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pushq $\index
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jmp isr_common
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.endm
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.macro ISR_ERR index
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.global _isr\index
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.type _isr\index, @function
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_isr\index:
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pushq $\index
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jmp isr_common
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.endm
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/* Interrupt Requests */
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ISR_NOERR 0
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ISR_NOERR 1
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//ISR_NOERR 2
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ISR_NOERR 3
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ISR_NOERR 4
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ISR_NOERR 5
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ISR_NOERR 6
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ISR_NOERR 7
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ISR_ERR 8
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ISR_NOERR 9
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ISR_ERR 10
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ISR_ERR 11
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ISR_ERR 12
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ISR_ERR 13
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ISR_ERR 14
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ISR_NOERR 15
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ISR_NOERR 16
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ISR_NOERR 17
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ISR_NOERR 18
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ISR_NOERR 19
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ISR_NOERR 20
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ISR_NOERR 21
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ISR_NOERR 22
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ISR_NOERR 23
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ISR_NOERR 24
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ISR_NOERR 25
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ISR_NOERR 26
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ISR_NOERR 27
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ISR_NOERR 28
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ISR_NOERR 29
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ISR_NOERR 30
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ISR_NOERR 31
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IRQ 0, 32
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IRQ 1, 33
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IRQ 2, 34
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IRQ 3, 35
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IRQ 4, 36
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IRQ 5, 37
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IRQ 6, 38
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IRQ 7, 39
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IRQ 8, 40
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IRQ 9, 41
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IRQ 10, 42
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IRQ 11, 43
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IRQ 12, 44
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IRQ 13, 45
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IRQ 14, 46
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IRQ 15, 47
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/* syscall entry point */
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ISR_NOERR 127
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2021-06-01 16:37:54 +03:00
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.global _isr124
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.type _isr124, @function
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_isr124:
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pushq %r12
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mov %cr3, %r12
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mov %r12, %cr3
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mov (lapic_final), %r12
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add $0xb0, %r12
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movl $0, (%r12)
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popq %r12
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iretq
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2021-05-31 04:47:02 +03:00
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/* No op, used to signal sleeping processor to wake and check the queue. */
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.extern lapic_final
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.global _isr126
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.type _isr126, @function
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_isr126:
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pushq %r12
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mov (lapic_final), %r12
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2021-06-01 13:36:46 +03:00
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add $0xb0, %r12
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movl $0, (%r12)
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2021-05-31 04:47:02 +03:00
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popq %r12
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iretq
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/* Fatal signal, stop everything. */
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.global _isr125
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.type _isr125, @function
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_isr125:
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cli
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1:
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hlt
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jmp 1b
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/* Fatal signal, stop everything. */
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.global _isr2
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.type _isr2, @function
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_isr2:
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cli
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1:
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hlt
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jmp 1b
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.macro _swapgs
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cmpq $8, 24(%rsp)
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je 1f
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swapgs
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1:
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.endm
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.extern isr_handler
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.type isr_handler, @function
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isr_common:
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/* Save all registers */
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_swapgs
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push %rax
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push %rbx
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push %rcx
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push %rdx
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push %rsi
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push %rdi
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push %rbp
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push %r8
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push %r9
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push %r10
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push %r11
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push %r12
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push %r13
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push %r14
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push %r15
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cld
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/* Call interrupt handler */
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mov %rsp, %rdi
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call isr_handler
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mov %rax, %rsp
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/* Restore all registers */
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pop %r15
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pop %r14
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pop %r13
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pop %r12
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pop %r11
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pop %r10
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pop %r9
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pop %r8
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pop %rbp
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pop %rdi
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pop %rsi
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pop %rdx
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pop %rcx
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pop %rbx
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pop %rax
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_swapgs
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/* Cleanup error code and interrupt # */
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add $16, %rsp
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/* Return from interrupt */
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iretq
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.global arch_save_context
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.type arch_save_context, @function
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arch_save_context:
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leaq 8(%rsp), %rax
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movq %rax, 0(%rdi)
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movq %rbp, 8(%rdi)
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movq (%rsp), %rax
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movq %rax, 16(%rdi)
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movq $0xc0000100, %rcx
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rdmsr
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movl %eax, 24(%rdi)
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movl %edx, 28(%rdi)
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movq %rbx, 32(%rdi)
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movq %r12, 40(%rdi)
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movq %r13, 48(%rdi)
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movq %r14, 56(%rdi)
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movq %r15, 64(%rdi)
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xor %rax, %rax
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retq
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.global arch_restore_context
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.type arch_restore_context, @function
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arch_restore_context:
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mov %gs:0x10,%rax
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cmp %gs:0x0,%rax
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je 1f
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lock andl $0xFFFFfff7,0x14(%rax)
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1:
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movq 0(%rdi), %rsp
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movq 8(%rdi), %rbp
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movl 24(%rdi), %eax
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movl 28(%rdi), %edx
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movq $0xc0000100, %rcx
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wrmsr
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movq 32(%rdi), %rbx
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movq 40(%rdi), %r12
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movq 48(%rdi), %r13
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movq 56(%rdi), %r14
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movq 64(%rdi), %r15
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movq $1, %rax
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jmpq *16(%rdi)
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.global arch_enter_tasklet
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.type arch_enter_tasklet, @function
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arch_enter_tasklet:
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popq %rdi
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popq %rsi
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jmpq *%rsi
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