79 lines
2.2 KiB
C
79 lines
2.2 KiB
C
#include <stdint.h>
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#include <stddef.h>
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#include <mm/vmm.h>
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#include <mm/pmm.h>
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#include <lib/blib.h>
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#include <sys/cpu.h>
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#define PT_SIZE ((uint64_t)0x1000)
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typedef uint64_t pt_entry_t;
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void vmm_assert_nx(void) {
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uint32_t a, b, c, d;
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if (!cpuid(0x80000001, 0, &a, &b, &c, &d) || !(d & (1 << 20))) {
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panic("vmm: NX functionality not available on this CPU.");
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}
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}
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static pt_entry_t *get_next_level(pt_entry_t *current_level, size_t entry) {
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pt_entry_t *ret;
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if (current_level[entry] & 0x1) {
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// Present flag set
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ret = (pt_entry_t *)(size_t)(current_level[entry] & ~((pt_entry_t)0xfff));
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} else {
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// Allocate a table for the next level
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ret = ext_mem_alloc(PT_SIZE);
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// Present + writable + user (0b111)
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current_level[entry] = (pt_entry_t)(size_t)ret | 0b111;
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}
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return ret;
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}
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pagemap_t new_pagemap(int lv) {
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pagemap_t pagemap;
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pagemap.levels = lv;
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pagemap.top_level = ext_mem_alloc(PT_SIZE);
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return pagemap;
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}
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void map_page(pagemap_t pagemap, uint64_t virt_addr, uint64_t phys_addr, uint64_t flags, bool hugepages) {
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// Calculate the indices in the various tables using the virtual address
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size_t pml5_entry = (virt_addr & ((uint64_t)0x1ff << 48)) >> 48;
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size_t pml4_entry = (virt_addr & ((uint64_t)0x1ff << 39)) >> 39;
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size_t pml3_entry = (virt_addr & ((uint64_t)0x1ff << 30)) >> 30;
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size_t pml2_entry = (virt_addr & ((uint64_t)0x1ff << 21)) >> 21;
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size_t pml1_entry = (virt_addr & ((uint64_t)0x1ff << 12)) >> 12;
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pt_entry_t *pml5, *pml4, *pml3, *pml2, *pml1;
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// Paging levels
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switch (pagemap.levels) {
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case 5:
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pml5 = pagemap.top_level;
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goto level5;
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case 4:
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pml4 = pagemap.top_level;
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goto level4;
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default:
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panic("");
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}
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level5:
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pml4 = get_next_level(pml5, pml5_entry);
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level4:
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pml3 = get_next_level(pml4, pml4_entry);
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pml2 = get_next_level(pml3, pml3_entry);
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if (hugepages) {
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pml2[pml2_entry] = (pt_entry_t)(phys_addr | flags | (1 << 7));
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return;
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}
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pml1 = get_next_level(pml2, pml2_entry);
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pml1[pml1_entry] = (pt_entry_t)(phys_addr | flags);
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}
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