100 lines
1.8 KiB
Plaintext
100 lines
1.8 KiB
Plaintext
#include <lib/macros.aarch64_asm.h>
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.set tpl_booted_flag, -56
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.set tpl_ttbr0, -48
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.set tpl_ttbr1, -40
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.set tpl_mair, -32
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.set tpl_tcr, -24
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.set tpl_sctlr, -16
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.set tpl_info_struct, -8
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.global smp_trampoline_start
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smp_trampoline_start:
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bl .L_entry
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.L_entry:
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// Mask IRQs
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msr daifset, #0b1111
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// Address to next page (since our offsets into the boot data are negative)
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add x1, x30, #0xFFC
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ldr x0, [x1, tpl_info_struct]
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ldr x2, [x1, tpl_sctlr]
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ldr x3, [x1, tpl_mair]
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ldr x4, [x1, tpl_tcr]
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ldr x5, [x1, tpl_ttbr0]
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ldr x6, [x1, tpl_ttbr1]
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// Configure EL1 state
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msr mair_el1, x3
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msr tcr_el1, x4
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msr ttbr0_el1, x5
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msr ttbr1_el1, x6
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msr sctlr_el1, x2
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dsb sy
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isb
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PICK_EL x8, 1f, 0f
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0:
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// Configure EL2-specific state for EL1
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// Don't trap counters to EL2
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mrs x8, cnthctl_el2
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orr x8, x8, #3
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msr cnthctl_el2, x8
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msr cntvoff_el2, xzr
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// Enable AArch64 in EL1
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mov x8, xzr
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orr x8, x8, #(1 << 31)
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orr x8, x8, #(1 << 1)
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msr hcr_el2, x8
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// Don't trap FP/SIMD to EL2
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mov x8, #0x33FF
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msr cptr_el2, x8
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msr hstr_el2, xzr
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// Run rest of trampoline in EL1
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mov x8, #0x3c4
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msr spsr_el2, x8
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adr x8, 1f
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msr elr_el2, x8
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eret
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1:
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// Notify BSP we are alive
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mov x8, #1
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add x9, x1, tpl_booted_flag
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stlr x8, [x9]
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// Wait for BSP to tell us where to go
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add x9, x0, #24
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2:
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ldar x8, [x9]
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cbnz x8, 3f
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yield
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b 2b
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3:
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msr elr_el1, x8
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msr spsel, #0
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ldr x8, [x0, #16]
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mov sp, x8
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// Enter kernel
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mov x8, #0x3c4
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msr spsr_el1, x8
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ZERO_REGS_EXCEPT_X0
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eret
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smp_trampoline_end:
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.global smp_trampoline_size
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smp_trampoline_size:
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.quad smp_trampoline_end - smp_trampoline_start
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