328 lines
6.9 KiB
C
328 lines
6.9 KiB
C
#ifndef __SYS__CPU_H__
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#define __SYS__CPU_H__
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#if defined(__x86_64__) || defined(__i386__)
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inline bool cpuid(uint32_t leaf, uint32_t subleaf,
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uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) {
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uint32_t cpuid_max;
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asm volatile ("cpuid"
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: "=a" (cpuid_max)
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: "a" (leaf & 0x80000000)
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: "ebx", "ecx", "edx");
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if (leaf > cpuid_max)
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return false;
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asm volatile ("cpuid"
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: "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
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: "a" (leaf), "c" (subleaf));
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return true;
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}
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inline void outb(uint16_t port, uint8_t value) {
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asm volatile ("outb %%al, %1" : : "a" (value), "Nd" (port) : "memory");
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}
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inline void outw(uint16_t port, uint16_t value) {
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asm volatile ("outw %%ax, %1" : : "a" (value), "Nd" (port) : "memory");
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}
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inline void outd(uint16_t port, uint32_t value) {
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asm volatile ("outl %%eax, %1" : : "a" (value), "Nd" (port) : "memory");
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}
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inline uint8_t inb(uint16_t port) {
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uint8_t value;
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asm volatile ("inb %1, %%al" : "=a" (value) : "Nd" (port) : "memory");
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return value;
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}
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inline uint16_t inw(uint16_t port) {
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uint16_t value;
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asm volatile ("inw %1, %%ax" : "=a" (value) : "Nd" (port) : "memory");
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return value;
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}
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inline uint32_t ind(uint16_t port) {
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uint32_t value;
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asm volatile ("inl %1, %%eax" : "=a" (value) : "Nd" (port) : "memory");
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return value;
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}
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inline void mmoutb(uintptr_t addr, uint8_t value) {
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asm volatile (
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"movb %1, (%0)"
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:
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: "r" (addr), "ir" (value)
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: "memory"
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);
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}
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inline void mmoutw(uintptr_t addr, uint16_t value) {
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asm volatile (
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"movw %1, (%0)"
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:
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: "r" (addr), "ir" (value)
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: "memory"
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);
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}
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inline void mmoutd(uintptr_t addr, uint32_t value) {
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asm volatile (
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"movl %1, (%0)"
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:
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: "r" (addr), "ir" (value)
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: "memory"
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);
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}
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#if defined (__x86_64__)
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inline void mmoutq(uintptr_t addr, uint64_t value) {
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asm volatile (
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"movq %1, (%0)"
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:
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: "r" (addr), "r" (value)
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: "memory"
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);
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}
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#endif
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inline uint8_t mminb(uintptr_t addr) {
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uint8_t ret;
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asm volatile (
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"movb (%1), %0"
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: "=r" (ret)
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: "r" (addr)
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: "memory"
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);
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return ret;
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}
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inline uint16_t mminw(uintptr_t addr) {
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uint16_t ret;
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asm volatile (
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"movw (%1), %0"
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: "=r" (ret)
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: "r" (addr)
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: "memory"
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);
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return ret;
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}
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inline uint32_t mmind(uintptr_t addr) {
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uint32_t ret;
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asm volatile (
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"movl (%1), %0"
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: "=r" (ret)
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: "r" (addr)
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: "memory"
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);
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return ret;
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}
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#if defined (__x86_64__)
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inline uint64_t mminq(uintptr_t addr) {
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uint64_t ret;
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asm volatile (
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"movq (%1), %0"
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: "=r" (ret)
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: "r" (addr)
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: "memory"
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);
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return ret;
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}
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#endif
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inline uint64_t rdmsr(uint32_t msr) {
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uint32_t edx, eax;
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asm volatile ("rdmsr"
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: "=a" (eax), "=d" (edx)
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: "c" (msr)
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: "memory");
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return ((uint64_t)edx << 32) | eax;
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}
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inline void wrmsr(uint32_t msr, uint64_t value) {
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uint32_t edx = value >> 32;
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uint32_t eax = (uint32_t)value;
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asm volatile ("wrmsr"
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:
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: "a" (eax), "d" (edx), "c" (msr)
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: "memory");
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}
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inline uint64_t rdtsc(void) {
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uint32_t edx, eax;
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asm volatile ("rdtsc" : "=a" (eax), "=d" (edx));
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return ((uint64_t)edx << 32) | eax;
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}
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inline void delay(uint64_t cycles) {
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uint64_t next_stop = rdtsc() + cycles;
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while (rdtsc() < next_stop);
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}
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#define rdrand(type) ({ \
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type rdrand__ret; \
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asm volatile ( \
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"1: " \
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"rdrand %0;" \
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"jnc 1b;" \
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: "=r" (rdrand__ret) \
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); \
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rdrand__ret; \
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})
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#define rdseed(type) ({ \
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type rdseed__ret; \
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asm volatile ( \
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"1: " \
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"rdseed %0;" \
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"jnc 1b;" \
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: "=r" (rdseed__ret) \
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); \
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rdseed__ret; \
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})
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#define write_cr(reg, val) do { \
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asm volatile ("mov %0, %%cr" reg :: "r" (val) : "memory"); \
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} while (0)
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#define read_cr(reg) ({ \
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size_t read_cr__cr; \
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asm volatile ("mov %%cr" reg ", %0" : "=r" (read_cr__cr) :: "memory"); \
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read_cr__cr; \
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})
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#define locked_read(var) ({ \
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typeof(*var) locked_read__ret = 0; \
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asm volatile ( \
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"lock xadd %0, %1" \
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: "+r" (locked_read__ret) \
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: "m" (*(var)) \
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: "memory" \
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); \
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locked_read__ret; \
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})
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#define locked_write(var, val) do { \
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__auto_type locked_write__ret = val; \
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asm volatile ( \
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"lock xchg %0, %1" \
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: "+r" ((locked_write__ret)) \
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: "m" (*(var)) \
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: "memory" \
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); \
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} while (0)
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#elif defined (__aarch64__)
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inline uint64_t rdtsc(void) {
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uint64_t v;
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asm volatile ("mrs %0, cntpct_el0" : "=r" (v));
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return v;
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}
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#define locked_read(var) ({ \
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typeof(*var) locked_read__ret = 0; \
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asm volatile ( \
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"ldar %0, %1" \
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: "=r" (locked_read__ret) \
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: "m" (*(var)) \
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: "memory" \
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); \
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locked_read__ret; \
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})
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inline size_t icache_line_size(void) {
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uint64_t ctr;
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asm volatile ("mrs %0, ctr_el0" : "=r"(ctr));
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return (ctr & 0b1111) << 4;
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}
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inline size_t dcache_line_size(void) {
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uint64_t ctr;
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asm volatile ("mrs %0, ctr_el0" : "=r"(ctr));
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return ((ctr >> 16) & 0b1111) << 4;
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}
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// Clean and invalidate D-Cache to Point of Coherency
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inline void clean_inval_dcache_poc(uintptr_t start, uintptr_t end) {
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size_t dsz = dcache_line_size();
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uintptr_t addr = start & ~(dsz - 1);
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while (addr < end) {
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asm volatile ("dc civac, %0" :: "r"(addr) : "memory");
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addr += dsz;
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}
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asm volatile ("dsb sy\n\tisb");
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}
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// Invalidate I-Cache to Point of Unification
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inline void inval_icache_pou(uintptr_t start, uintptr_t end) {
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size_t isz = icache_line_size();
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uintptr_t addr = start & ~(isz - 1);
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while (addr < end) {
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asm volatile ("ic ivau, %0" :: "r"(addr) : "memory");
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addr += isz;
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}
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asm volatile ("dsb sy\n\tisb");
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}
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inline int current_el(void) {
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uint64_t v;
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asm volatile ("mrs %0, currentel" : "=r"(v));
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v = (v >> 2) & 0b11;
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return v;
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}
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#elif defined (__riscv64)
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inline uint64_t rdtsc(void) {
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uint64_t v;
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asm ("rdtime %0" : "=r"(v));
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return v;
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}
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#define csr_read(csr) ({\
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size_t v;\
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asm volatile ("csrr %0, " csr : "=r"(v));\
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v;\
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})
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#define csr_write(csr, v) ({\
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size_t old;\
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asm volatile ("csrrw %0, " csr ", %1" : "=r"(old) : "r"(v));\
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old;\
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})
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#define make_satp(mode, ppn) (((size_t)(mode) << 60) | ((size_t)(ppn) >> 12))
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#define locked_read(var) ({ \
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typeof(*var) locked_read__ret; \
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asm volatile ( \
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"ld %0, (%1); fence r, rw" \
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: "=r"(locked_read__ret) \
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: "r"(var) \
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: "memory" \
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); \
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locked_read__ret; \
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})
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#else
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#error Unknown architecture
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#endif
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#endif
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