306 lines
10 KiB
C
306 lines
10 KiB
C
#include <stdint.h>
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#include <stddef.h>
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#include <mm/vmm.h>
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#include <mm/pmm.h>
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#include <lib/blib.h>
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#include <lib/print.h>
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#include <sys/cpu.h>
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#define PT_SIZE ((uint64_t)0x1000)
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typedef uint64_t pt_entry_t;
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static pt_entry_t *get_next_level(pagemap_t pagemap, pt_entry_t *current_level,
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uint64_t virt, enum page_size desired_sz,
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size_t level_idx, size_t entry);
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#if defined (__x86_64__) || defined (__i386__)
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#define PT_FLAG_VALID ((uint64_t)1 << 0)
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#define PT_FLAG_WRITE ((uint64_t)1 << 1)
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#define PT_FLAG_USER ((uint64_t)1 << 2)
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#define PT_FLAG_LARGE ((uint64_t)1 << 7)
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#define PT_FLAG_NX ((uint64_t)1 << 63)
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#define PT_PADDR_MASK ((uint64_t)0x0000FFFFFFFFF000)
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#define PT_TABLE_FLAGS (PT_FLAG_VALID | PT_FLAG_WRITE | PT_FLAG_USER)
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#define PT_IS_TABLE(x) (((x) & (PT_FLAG_VALID | PT_FLAG_LARGE)) == PT_FLAG_VALID)
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#define PT_IS_LARGE(x) (((x) & (PT_FLAG_VALID | PT_FLAG_LARGE)) == (PT_FLAG_VALID | PT_FLAG_LARGE))
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#define PT_TO_VMM_FLAGS(x) ((x) & (PT_FLAG_WRITE | PT_FLAG_NX))
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void vmm_assert_nx(void) {
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uint32_t a, b, c, d;
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if (!cpuid(0x80000001, 0, &a, &b, &c, &d) || !(d & (1 << 20))) {
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panic(false, "vmm: NX functionality not available on this CPU.");
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}
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}
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pagemap_t new_pagemap(int lv) {
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pagemap_t pagemap;
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pagemap.levels = lv;
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pagemap.top_level = ext_mem_alloc(PT_SIZE);
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return pagemap;
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}
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static bool is_1gib_page_supported(void) {
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// Cache the cpuid result :^)
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static bool CACHE_INIT = false;
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static bool CACHE = false;
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if (!CACHE_INIT) {
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// Check if 1GiB pages are supported:
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uint32_t eax, ebx, ecx, edx;
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CACHE = cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx) && ((edx & 1 << 26) == 1 << 26);
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CACHE_INIT = true;
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printv("paging: 1GiB pages are %s!\n", CACHE ? "supported" : "not supported");
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}
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return CACHE;
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}
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void map_page(pagemap_t pagemap, uint64_t virt_addr, uint64_t phys_addr, uint64_t flags, enum page_size pg_size) {
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// Calculate the indices in the various tables using the virtual address
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size_t pml5_entry = (virt_addr & ((uint64_t)0x1ff << 48)) >> 48;
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size_t pml4_entry = (virt_addr & ((uint64_t)0x1ff << 39)) >> 39;
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size_t pml3_entry = (virt_addr & ((uint64_t)0x1ff << 30)) >> 30;
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size_t pml2_entry = (virt_addr & ((uint64_t)0x1ff << 21)) >> 21;
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size_t pml1_entry = (virt_addr & ((uint64_t)0x1ff << 12)) >> 12;
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pt_entry_t *pml5, *pml4, *pml3, *pml2, *pml1;
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flags |= PT_FLAG_VALID; // Always present
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// Paging levels
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switch (pagemap.levels) {
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case 5:
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pml5 = pagemap.top_level;
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goto level5;
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case 4:
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pml4 = pagemap.top_level;
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goto level4;
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default:
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__builtin_unreachable();
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}
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level5:
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pml4 = get_next_level(pagemap, pml5, virt_addr, pg_size, 4, pml5_entry);
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level4:
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pml3 = get_next_level(pagemap, pml4, virt_addr, pg_size, 3, pml4_entry);
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if (pg_size == Size1GiB) {
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// Check if 1GiB pages are avaliable.
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if (is_1gib_page_supported()) {
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pml3[pml3_entry] = (pt_entry_t)(phys_addr | flags | PT_FLAG_LARGE);
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} else {
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// If 1GiB pages are not supported then emulate it by splitting them into
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// 2MiB pages.
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for (uint64_t i = 0; i < 0x40000000; i += 0x200000) {
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map_page(pagemap, virt_addr + i, phys_addr + i, flags, Size2MiB);
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}
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}
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return;
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}
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pml2 = get_next_level(pagemap, pml3, virt_addr, pg_size, 2, pml3_entry);
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if (pg_size == Size2MiB) {
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pml2[pml2_entry] = (pt_entry_t)(phys_addr | flags | PT_FLAG_LARGE);
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return;
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}
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pml1 = get_next_level(pagemap, pml2, virt_addr, pg_size, 1, pml2_entry);
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pml1[pml1_entry] = (pt_entry_t)(phys_addr | flags);
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}
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#elif defined (__aarch64__)
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// Here we operate under the assumption that 4K pages are supported by the CPU.
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// This appears to be guaranteed by UEFI, as section 2.3.6 "AArch64 Platforms"
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// states that the primary processor core configuration includes 4K translation
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// granules (TCR_EL1.TG0 = 0).
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// Support for 4K pages also implies 2M, 1G and 512G blocks.
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// Sanity check that 4K pages are supported.
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void vmm_assert_4k_pages(void) {
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uint64_t aa64mmfr0;
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asm volatile ("mrs %0, id_aa64mmfr0_el1" : "=r"(aa64mmfr0));
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if (((aa64mmfr0 >> 28) & 0b1111) == 0b1111) {
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panic(false, "vmm: CPU does not support 4K pages, please make a bug report about this.");
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}
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}
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#define PT_FLAG_VALID ((uint64_t)1 << 0)
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#define PT_FLAG_TABLE ((uint64_t)1 << 1)
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#define PT_FLAG_4K_PAGE ((uint64_t)1 << 1)
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#define PT_FLAG_BLOCK ((uint64_t)0 << 1)
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#define PT_FLAG_USER ((uint64_t)1 << 6)
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#define PT_FLAG_READONLY ((uint64_t)1 << 7)
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#define PT_FLAG_INNER_SH ((uint64_t)3 << 8)
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#define PT_FLAG_ACCESS ((uint64_t)1 << 10)
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#define PT_FLAG_XN ((uint64_t)1 << 54)
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#define PT_FLAG_WB ((uint64_t)0 << 2)
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#define PT_FLAG_FB ((uint64_t)1 << 2)
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#define PT_PADDR_MASK ((uint64_t)0x0000FFFFFFFFF000)
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#define PT_TABLE_FLAGS (PT_FLAG_VALID | PT_FLAG_TABLE)
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#define PT_IS_TABLE(x) (((x) & (PT_FLAG_VALID | PT_FLAG_TABLE)) == (PT_FLAG_VALID | PT_FLAG_TABLE))
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#define PT_IS_LARGE(x) (((x) & (PT_FLAG_VALID | PT_FLAG_TABLE)) == PT_FLAG_VALID)
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#define PT_TO_VMM_FLAGS(x) (pt_to_vmm_flags_internal(x))
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static uint64_t pt_to_vmm_flags_internal(pt_entry_t entry) {
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uint64_t flags = 0;
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if (!(entry & PT_FLAG_READONLY))
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flags |= VMM_FLAG_WRITE;
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if (entry & PT_FLAG_XN)
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flags |= VMM_FLAG_NOEXEC;
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if (entry & PT_FLAG_FB)
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flags |= VMM_FLAG_FB;
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return flags;
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}
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pagemap_t new_pagemap(int lv) {
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pagemap_t pagemap;
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pagemap.levels = lv;
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pagemap.top_level[0] = ext_mem_alloc(PT_SIZE);
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pagemap.top_level[1] = ext_mem_alloc(PT_SIZE);
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return pagemap;
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}
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void map_page(pagemap_t pagemap, uint64_t virt_addr, uint64_t phys_addr, uint64_t flags, enum page_size pg_size) {
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// Calculate the indices in the various tables using the virtual address
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size_t pml5_entry = (virt_addr & ((uint64_t)0xf << 48)) >> 48;
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size_t pml4_entry = (virt_addr & ((uint64_t)0x1ff << 39)) >> 39;
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size_t pml3_entry = (virt_addr & ((uint64_t)0x1ff << 30)) >> 30;
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size_t pml2_entry = (virt_addr & ((uint64_t)0x1ff << 21)) >> 21;
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size_t pml1_entry = (virt_addr & ((uint64_t)0x1ff << 12)) >> 12;
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pt_entry_t *pml5, *pml4, *pml3, *pml2, *pml1;
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bool is_higher_half = virt_addr & ((uint64_t)1 << 63);
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uint64_t real_flags = PT_FLAG_VALID | PT_FLAG_INNER_SH | PT_FLAG_ACCESS | PT_FLAG_WB;
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if (!(flags & VMM_FLAG_WRITE))
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real_flags |= PT_FLAG_READONLY;
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if (flags & VMM_FLAG_NOEXEC)
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real_flags |= PT_FLAG_XN;
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if (flags & VMM_FLAG_FB)
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real_flags |= PT_FLAG_FB;
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// Paging levels
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switch (pagemap.levels) {
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case 5:
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pml5 = pagemap.top_level[is_higher_half];
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goto level5;
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case 4:
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pml4 = pagemap.top_level[is_higher_half];
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goto level4;
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default:
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__builtin_unreachable();
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}
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level5:
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pml4 = get_next_level(pagemap, pml5, virt_addr, pg_size, 4, pml5_entry);
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level4:
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pml3 = get_next_level(pagemap, pml4, virt_addr, pg_size, 3, pml4_entry);
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if (pg_size == Size1GiB) {
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pml3[pml3_entry] = (pt_entry_t)(phys_addr | real_flags | PT_FLAG_BLOCK);
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return;
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}
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pml2 = get_next_level(pagemap, pml3, virt_addr, pg_size, 2, pml3_entry);
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if (pg_size == Size2MiB) {
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pml2[pml2_entry] = (pt_entry_t)(phys_addr | real_flags | PT_FLAG_BLOCK);
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return;
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}
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pml1 = get_next_level(pagemap, pml2, virt_addr, pg_size, 1, pml2_entry);
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pml1[pml1_entry] = (pt_entry_t)(phys_addr | real_flags | PT_FLAG_4K_PAGE);
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}
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#else
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#error Unknown architecture
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#endif
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static pt_entry_t *get_next_level(pagemap_t pagemap, pt_entry_t *current_level,
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uint64_t virt, enum page_size desired_sz,
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size_t level_idx, size_t entry) {
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pt_entry_t *ret;
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if (PT_IS_TABLE(current_level[entry])) {
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ret = (pt_entry_t *)(size_t)(current_level[entry] & PT_PADDR_MASK);
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} else {
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if (PT_IS_LARGE(current_level[entry])) {
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// We are replacing an existing large page with a smaller page.
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// Split the previous mapping into mappings of the newly requested size
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// before performing the requested map operation.
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uint64_t old_page_size, new_page_size;
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switch (level_idx) {
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case 2:
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old_page_size = 0x40000000;
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break;
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case 1:
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old_page_size = 0x200000;
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break;
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default:
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panic(false, "Unexpected level in get_next_level");
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}
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switch (desired_sz) {
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case Size1GiB:
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new_page_size = 0x40000000;
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break;
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case Size2MiB:
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new_page_size = 0x200000;
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break;
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case Size4KiB:
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new_page_size = 0x1000;
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break;
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default:
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panic(false, "Unexpected page size in get_next_level");
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}
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// Save all the information from the old entry at this level
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uint64_t old_flags = PT_TO_VMM_FLAGS(current_level[entry]);
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uint64_t old_phys = current_level[entry] & PT_PADDR_MASK;
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uint64_t old_virt = virt & ~(old_page_size - 1);
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if (old_phys & (old_page_size - 1))
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panic(false, "Unexpected page table entry address in get_next_level");
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// Allocate a table for the next level
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ret = ext_mem_alloc(PT_SIZE);
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current_level[entry] = (pt_entry_t)(size_t)ret | PT_TABLE_FLAGS;
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// Recreate the old mapping with smaller pages
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for (uint64_t i = 0; i < old_page_size; i += new_page_size) {
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map_page(pagemap, old_virt + i, old_phys + i, old_flags, desired_sz);
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}
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} else {
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// Allocate a table for the next level
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ret = ext_mem_alloc(PT_SIZE);
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current_level[entry] = (pt_entry_t)(size_t)ret | PT_TABLE_FLAGS;
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}
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}
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return ret;
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}
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