mintsuki 2f844f3f48 stivale1&2: Pass higher half GDTR.base when returning higher half pointers

2021-11-25 22:46:16 +01:00

..

a20.h

…

a20.s2.c

misc: Change how bios and uefi macros are defined and tested

2021-07-15 10:03:47 +02:00

cpu.h

idt: Move flush_irq() logic to stage 3

2021-09-21 17:44:01 +02:00

dummy_isr.asm32

asm: Reorganise assembly code to avoid symlink use

2021-10-22 15:45:47 +02:00

dummy_isr.asm64

idt: Move dummy_isr() to its own assembly file

2021-10-22 12:17:16 +02:00

e820.h

pmm: Rework conventional memory allocator

2021-04-15 02:21:38 +02:00

e820.s2.c

pmm: Allocate memory map dynamically using EFI

2021-09-03 03:10:23 +02:00

exceptions.s2.c

misc: Change how bios and uefi macros are defined and tested

2021-07-15 10:03:47 +02:00

gdt.h

stivale1&2: Pass higher half GDTR.base when returning higher half pointers

2021-11-25 22:46:16 +01:00

gdt.s2.c

gdt: Allocate GDT on the heap on UEFI

2021-11-25 21:51:41 +01:00

idt.c

idt: Move dummy_isr() to its own assembly file

2021-10-22 12:17:16 +02:00

idt.h

apic: Do not attempt an APIC flush for protocols that don't mask IRQs

2021-09-22 12:33:56 +02:00

idt.s2.c

idt: Move flush_irq() logic to stage 3

2021-09-21 17:44:01 +02:00

int_thunks.s2.asmb

asm: Reorganise assembly code to avoid symlink use

2021-10-22 15:45:47 +02:00

lapic.c

apic: Improve pending IRQ flushing mechanism

2021-09-21 17:28:32 +02:00

lapic.h

apic: Improve pending IRQ flushing mechanism

2021-09-21 17:28:32 +02:00

pic.c

misc: Change the way stage 2 and 3 are divided

2021-03-01 23:38:55 +01:00

pic.h

…

smp_trampoline.real

stivale2: Implement PMRs

2021-07-15 16:20:29 +02:00

smp.c

apic: Improve pending IRQ flushing mechanism

2021-09-21 17:28:32 +02:00

smp.h

stivale2: Implement PMRs

2021-07-15 16:20:29 +02:00