e1f6ac8860
* Initial aarch64 port * Enable chainload on aarch64 No changes necessary since it's all UEFI anyway. * Add specification for Limine protocol for aarch64 * PROTOCOL: Specify state of information in DT /chosen node * common: Add spinup code for aarch64 * common: Port elf and term to aarch64 * common: Port vmm to aarch64 Also prepare to drop VMM_FLAG_PRESENT on x86. * protos: Port limine boot protocol to aarch64 Also drop VMM_FLAG_PRESENT since we never unmap pages anyway. * test: Add DTB request * PROTOCOL: Port SMP request to aarch64 * cpu: Add cache maintenance functions for aarch64 * protos/limine, sys: Port SMP to aarch64 Also move common asm macros into a header file. * test: Start up APs * vmm: Unify get_next_level and implement large page splitting * protos/limine: Map framebuffer using correct caching mode on AArch64 * CI: Fix GCC build for aarch64 * entry, menu: Replace uses of naked attribute with separate asm file GCC does not understand the naked attribute on aarch64, and didn't understand it for x86 in older versions.
67 lines
819 B
Plaintext
67 lines
819 B
Plaintext
.section .text
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.global memcpy
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memcpy:
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mov x3, x0
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0:
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cbz x2, 1f
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ldrb w4, [x1], #1
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strb w4, [x0], #1
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sub x2, x2, #1
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b 0b
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1:
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mov x0, x3
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ret
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.global memset
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memset:
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mov x3, x0
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0:
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cbz x2, 1f
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strb w1, [x0], #1
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sub x2, x2, #1
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b 0b
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1:
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mov x0, x3
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ret
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.global memmove
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memmove:
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mov x3, x0
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mov x5, x2
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cmp x0, x1
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b.gt 1f
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0:
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cbz x2, 2f
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ldrb w4, [x1], #1
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strb w4, [x0], #1
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sub x2, x2, #1
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b 0b
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1:
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sub x5, x5, #1
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cbz x2, 2f
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ldrb w4, [x1, x5]
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strb w4, [x0, x5]
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sub x2, x2, #1
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b 1b
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2:
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mov x0, x3
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ret
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.global memcmp
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memcmp:
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mov x3, xzr
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0:
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cbz x2, 1f
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ldrb w3, [x0], #1
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ldrb w4, [x1], #1
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sub w3, w3, w4
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cbnz w3, 1f
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sub x2, x2, #1
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b 0b
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1:
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sxtw x0, w3
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mov x0, x3
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ret
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