66 lines
1.5 KiB
C
66 lines
1.5 KiB
C
#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include <sys/lapic.h>
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#include <sys/cpu.h>
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#include <lib/blib.h>
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#include <lib/acpi.h>
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struct dmar {
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struct sdt;
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uint8_t host_address_width;
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uint8_t flags;
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uint8_t reserved[10];
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symbol remapping_structures;
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} __attribute__((packed));
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uint32_t lapic_read(uint32_t reg) {
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size_t lapic_mmio_base = (size_t)(rdmsr(0x1b) & 0xfffff000);
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return mmind((void *)(lapic_mmio_base + reg));
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}
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void lapic_write(uint32_t reg, uint32_t data) {
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size_t lapic_mmio_base = (size_t)(rdmsr(0x1b) & 0xfffff000);
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mmoutd((void *)(lapic_mmio_base + reg), data);
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}
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bool x2apic_check(void) {
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uint32_t eax, ebx, ecx, edx;
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cpuid(1, 0, &eax, &ebx, &ecx, &edx);
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if (!(ecx & (1 << 21)))
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return false;
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// According to the Intel VT-d spec, we're required
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// to check if bit 0 and 1 of the flags field of the
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// DMAR ACPI table are set, and if they are, we should
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// not report x2APIC capabilities.
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struct dmar *dmar = acpi_get_table("DMAR", 0);
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if (!dmar)
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return true;
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if ((dmar->flags & (1 << 0)) && (dmar->flags & (1 << 1)))
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return false;
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return true;
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}
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bool x2apic_enable(void) {
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if (!x2apic_check())
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return false;
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uint64_t ia32_apic_base = rdmsr(0x1b);
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ia32_apic_base |= (1 << 10);
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wrmsr(0x1b, ia32_apic_base);
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return true;
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}
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uint64_t x2apic_read(uint32_t reg) {
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return rdmsr(0x800 + (reg >> 4));
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}
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void x2apic_write(uint32_t reg, uint64_t data) {
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wrmsr(0x800 + (reg >> 4), data);
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}
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