From c1cc581816529510d23034d4e7648c5291164358 Mon Sep 17 00:00:00 2001
From: xvanc <xvancm@gmail.com>
Date: Wed, 6 Sep 2023 19:12:25 -0500
Subject: [PATCH] docs: caching/riscv: add info about caching

---
 PROTOCOL.md | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/PROTOCOL.md b/PROTOCOL.md
index 9189d8f1..94b49e6a 100644
--- a/PROTOCOL.md
+++ b/PROTOCOL.md
@@ -142,6 +142,16 @@ caching modes, in an unspecified order.
 In order to access MMIO regions, the kernel must ensure the correct caching mode
 is used on it's own.
 
+### riscv64
+
+If the `Svpbmt` extension is available, all framebuffer memory regions are mapped
+with `PBMT=NC` to enable write-combining optimizations. The kernel executable,
+loaded at or above `0xffffffff80000000`, and all HHDM memory regions are mapped
+with the default `PBMT=PMA`.
+
+If the `Svpbmt` extension is not available, no PMAs can be overridden (effectively,
+everything is mapped with `PBMT=PMA`).
+
 ## Entry machine state
 
 ### x86_64