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elf: aarch64: Don't needlessly invalidate the data cache

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Cleaning the data cache to PoC without invalidating it is enough when
invalidating the instruction cache to PoU.
This commit is contained in:
Kacper Słomiński 2023-08-17 23:13:46 +02:00 committed by mintsuki
parent 573d0095bf
commit ba5d63b82a
3 changed files with 15 additions and 1 deletions
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2
common/lib/elf.c
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@ -577,7 +577,7 @@ again:
} }
#if defined (__aarch64__) #if defined (__aarch64__)
clean_inval_dcache_poc(mem_base, mem_base + mem_size); clean_dcache_poc(mem_base, mem_base + mem_size);
inval_icache_pou(mem_base, mem_base + mem_size); inval_icache_pou(mem_base, mem_base + mem_size);
#endif #endif
} }

1
common/sys/cpu.c
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@ -24,5 +24,6 @@ extern void delay(uint64_t cycles);
extern size_t icache_line_size(void); extern size_t icache_line_size(void);
extern size_t dcache_line_size(void); extern size_t dcache_line_size(void);
extern void clean_inval_dcache_poc(uintptr_t start, uintptr_t end); extern void clean_inval_dcache_poc(uintptr_t start, uintptr_t end);
extern void clean_dcache_poc(uintptr_t start, uintptr_t end);
extern void inval_icache_pou(uintptr_t start, uintptr_t end); extern void inval_icache_pou(uintptr_t start, uintptr_t end);
extern int current_el(void); extern int current_el(void);

13
common/sys/cpu.h
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@ -265,6 +265,19 @@ inline void clean_inval_dcache_poc(uintptr_t start, uintptr_t end) {
asm volatile ("dsb sy\n\tisb"); asm volatile ("dsb sy\n\tisb");
} }
// Clean D-Cache to Point of Coherency
inline void clean_dcache_poc(uintptr_t start, uintptr_t end) {
size_t dsz = dcache_line_size();
uintptr_t addr = start & ~(dsz - 1);
while (addr < end) {
asm volatile ("dc cvac, %0" :: "r"(addr) : "memory");
addr += dsz;
}
asm volatile ("dsb sy\n\tisb");
}
// Invalidate I-Cache to Point of Unification // Invalidate I-Cache to Point of Unification
inline void inval_icache_pou(uintptr_t start, uintptr_t end) { inline void inval_icache_pou(uintptr_t start, uintptr_t end) {
size_t isz = icache_line_size(); size_t isz = icache_line_size();