misc: Backports from trunk
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1b72dd32a0
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a6e115d486
@ -119,6 +119,12 @@ level4:
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pml1 = get_next_level(pagemap, pml2, virt_addr, pg_size, 1, pml2_entry);
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// PML1 wants PAT bit at 7 instead of 12
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if (flags & ((uint64_t)1 << 12)) {
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flags &= ~((uint64_t)1 << 12);
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flags |= ((uint64_t)1 << 7);
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}
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pml1[pml1_entry] = (pt_entry_t)(phys_addr | flags);
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}
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@ -8,7 +8,7 @@
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#define VMM_FLAG_WRITE ((uint64_t)1 << 1)
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#define VMM_FLAG_NOEXEC ((uint64_t)1 << 63)
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#define VMM_FLAG_FB ((uint64_t)0)
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#define VMM_FLAG_FB (((uint64_t)1 << 3) | ((uint64_t)1 << 12))
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#define VMM_MAX_LEVEL 3
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@ -41,28 +41,25 @@ static pagemap_t build_pagemap(int paging_mode, bool nx, struct elf_range *range
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pagemap_t pagemap = new_pagemap(paging_mode);
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if (ranges_count == 0) {
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// Map 0 to 2GiB at 0xffffffff80000000
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for (uint64_t i = 0; i < 0x80000000; i += 0x40000000) {
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map_page(pagemap, 0xffffffff80000000 + i, i, VMM_FLAG_WRITE, Size1GiB);
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panic(true, "limine: ranges_count == 0");
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}
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for (size_t i = 0; i < ranges_count; i++) {
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uint64_t virt = ranges[i].base;
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uint64_t phys;
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if (virt & ((uint64_t)1 << 63)) {
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phys = physical_base + (virt - virtual_base);
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} else {
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panic(false, "limine: Virtual address of a PHDR in lower half");
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}
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} else {
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for (size_t i = 0; i < ranges_count; i++) {
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uint64_t virt = ranges[i].base;
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uint64_t phys;
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if (virt & ((uint64_t)1 << 63)) {
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phys = physical_base + (virt - virtual_base);
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} else {
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panic(false, "limine: Protected memory ranges are only supported for higher half kernels");
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}
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uint64_t pf =
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(ranges[i].permissions & ELF_PF_X ? 0 : (nx ? VMM_FLAG_NOEXEC : 0)) |
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(ranges[i].permissions & ELF_PF_W ? VMM_FLAG_WRITE : 0);
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uint64_t pf =
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(ranges[i].permissions & ELF_PF_X ? 0 : (nx ? VMM_FLAG_NOEXEC : 0)) |
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(ranges[i].permissions & ELF_PF_W ? VMM_FLAG_WRITE : 0);
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for (uint64_t j = 0; j < ranges[i].length; j += 0x1000) {
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map_page(pagemap, virt + j, phys + j, pf, Size4KiB);
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}
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for (uint64_t j = 0; j < ranges[i].length; j += 0x1000) {
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map_page(pagemap, virt + j, phys + j, pf, Size4KiB);
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}
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}
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@ -108,11 +105,13 @@ static pagemap_t build_pagemap(int paging_mode, bool nx, struct elf_range *range
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uint64_t length = _memmap[i].length;
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uint64_t top = base + length;
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if (base < 0x100000000)
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if (base < 0x100000000) {
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base = 0x100000000;
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}
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if (base >= top)
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if (base >= top) {
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continue;
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}
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uint64_t aligned_base = ALIGN_DOWN(base, 0x40000000);
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uint64_t aligned_top = ALIGN_UP(top, 0x40000000);
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@ -125,16 +124,16 @@ static pagemap_t build_pagemap(int paging_mode, bool nx, struct elf_range *range
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}
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}
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// Map the framebuffer as uncacheable
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#if defined (__aarch64__)
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// Map the framebuffer with appropriate permissions
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for (size_t i = 0; i < _memmap_entries; i++) {
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if (_memmap[i].type != MEMMAP_FRAMEBUFFER) {
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continue;
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}
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uint64_t base = _memmap[i].base;
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uint64_t length = _memmap[i].length;
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uint64_t top = base + length;
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if (_memmap[i].type != MEMMAP_FRAMEBUFFER)
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continue;
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uint64_t aligned_base = ALIGN_DOWN(base, 0x1000);
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uint64_t aligned_top = ALIGN_UP(top, 0x1000);
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uint64_t aligned_length = aligned_top - aligned_base;
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@ -145,7 +144,6 @@ static pagemap_t build_pagemap(int paging_mode, bool nx, struct elf_range *range
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map_page(pagemap, direct_map_offset + page, page, VMM_FLAG_WRITE | VMM_FLAG_FB, Size4KiB);
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}
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}
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#endif
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return pagemap;
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}
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@ -1214,6 +1212,16 @@ FEAT_END
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rm_int(0x15, &r, &r);
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#endif
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// Set PAT as:
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// PAT0 -> WB (06)
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// PAT1 -> WT (04)
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// PAT2 -> UC- (07)
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// PAT3 -> UC (00)
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// PAT4 -> WP (05)
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// PAT5 -> WC (01)
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uint64_t pat = (uint64_t)0x010500070406;
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wrmsr(0x277, pat);
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pic_mask_all();
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io_apic_mask_all();
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@ -39,6 +39,11 @@ smp_trampoline_start:
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xor eax, eax
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mov cr4, eax
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mov ecx, 0x277
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mov eax, 0x00070406
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mov edx, 0x00000105
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wrmsr
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test dword [ebx + (passed_info.target_mode - smp_trampoline_start)], (1 << 2)
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jz .nox2apic
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