docs: PROTOCOL.md: Backport caching section from trunk
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PROTOCOL.md
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PROTOCOL.md
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@ -112,6 +112,57 @@ If the kernel is a position independent executable, the bootloader is free to
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relocate it as it sees fit, potentially performing KASLR (as specified by the
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relocate it as it sees fit, potentially performing KASLR (as specified by the
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config).
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config).
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## Caching
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### x86-64
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The kernel executable, loaded at or above `0xffffffff80000000`, sees all of its
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segments mapped using write-back (WB) caching at the page tables level.
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All HHDM and identity map memory regions are mapped using write-back (WB) caching at the page
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tables level, except framebuffer regions which are mapped using write-combining
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(WC) caching at the page tables level.
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The PAT's (Page Attribute Table) layout is specified to be as follows:
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```
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PAT0 -> WB
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PAT1 -> WT
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PAT2 -> UC-
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PAT3 -> UC
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PAT4 -> WP
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PAT5 -> WC
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PAT6 -> unspecified
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PAT7 -> unspecified
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```
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The MTRRs are left as the firmware set them up.
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### aarch64
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The kernel executable, loaded at or above `0xffffffff80000000`, sees all of its
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segments mapped using Normal Write-Back RW-Allocate non-transient caching mode.
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All HHDM and identity map memory regions are mapped using the Normal Write-Back RW-Allocate
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non-transient caching mode, except for the framebuffer regions, which are
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mapped in using an unspecified caching mode, correct for use with the
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framebuffer on the platform.
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The `MAIR_EL1` register will at least contain entries for the above-mentioned
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caching modes, in an unspecified order.
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In order to access MMIO regions, the kernel must ensure the correct caching mode
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is used on its own.
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### riscv64
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If the `Svpbmt` extension is available, all framebuffer memory regions are mapped
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with `PBMT=NC` to enable write-combining optimizations. The kernel executable,
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loaded at or above `0xffffffff80000000`, and all HHDM and identity map memory regions are mapped
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with the default `PBMT=PMA`.
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If the `Svpbmt` extension is not available, no PMAs can be overridden (effectively,
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everything is mapped with `PBMT=PMA`).
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## Machine state at entry
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## Machine state at entry
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### x86-64
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### x86-64
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@ -163,27 +214,25 @@ All other general purpose registers are set to 0.
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unless the an Entry Point feature is requested (see below), in which case,
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unless the an Entry Point feature is requested (see below), in which case,
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the value of `PC` is going to be taken from there.
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the value of `PC` is going to be taken from there.
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The contents of the `VBAR_EL1` register are undefined, and the kernel must load it's own.
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The contents of the `VBAR_EL1` register are undefined, and the kernel must load
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its own.
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The `MAIR_EL1` register will contain at least these entries, in an unspecified order:
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The `MAIR_EL1` register contents are described above, in the caching section.
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- Normal, Write-back RW-Allocate non-transient (`0b11111111`),
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- Unspecified, correct for use with the framebuffer.
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The kernel and the lower-half identity mapping will be mapped with Normal write-back memory,
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while the framebuffer is mapped with the correct caching mode. The kernel must ensure that
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MMIO it wants to access is mapped with the correct caching mode.
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All interrupts are masked (`PSTATE.{D, A, I, F}` are set to 1).
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All interrupts are masked (`PSTATE.{D, A, I, F}` are set to 1).
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The kernel is entered in little-endian AArch64 EL1t (EL1 with `PSTATE.SP` set to 0, `PSTATE.E` set to 0, and `PSTATE.nRW` set to 0).
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The kernel is entered in little-endian AArch64 EL1t (EL1 with `PSTATE.SP` set to
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0, `PSTATE.E` set to 0, and `PSTATE.nRW` set to 0).
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Other fields of `PSTATE` are undefined.
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Other fields of `PSTATE` are undefined.
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At entry: the MMU (`SCTLR_EL1.M`) is enabled, the I-Cache and D-Cache (`SCTLR_EL1.{I, C}`) are enabled,
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At entry: the MMU (`SCTLR_EL1.M`) is enabled, the I-Cache and D-Cache
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data alignment checking (`SCTLR_EL1.A`) is disabled. SP alignment checking (`SCTLR_EL1.{SA, SA0}`) is enabled.
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(`SCTLR_EL1.{I, C}`) are enabled, data alignment checking (`SCTLR_EL1.A`) is
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Other fields of `SCTLR_EL1` are reset to 0 or to their reserved value.
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disabled. SP alignment checking (`SCTLR_EL1.{SA, SA0}`) is enabled. Other fields
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of `SCTLR_EL1` are reset to 0 or to their reserved value.
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Higher ELs do not interfere with accesses to vector or floating point instructions or registers.
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Higher ELs do not interfere with accesses to vector or floating point
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instructions or registers.
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Higher ELs do not interfere with accesses to the generic timer and counter.
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Higher ELs do not interfere with accesses to the generic timer and counter.
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@ -195,7 +244,8 @@ If booted by EFI/UEFI, boot services are exited.
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at least 64KiB (65536 bytes) in size, or the size specified in the Stack
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at least 64KiB (65536 bytes) in size, or the size specified in the Stack
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Size Request (see below).
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Size Request (see below).
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All other general purpose registers (including `X29` and `X30`) are set to 0. Vector registers are in an undefined state.
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All other general purpose registers (including `X29` and `X30`) are set to 0.
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Vector registers are in an undefined state.
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### riscv64
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### riscv64
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