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misc: Fix a bunch of warnings related to potentially used uninitialised variables

This commit is contained in:
mintsuki 2020-11-16 21:23:11 +01:00
parent 873ebc3878
commit 970b4e3fc9
7 changed files with 14 additions and 14 deletions
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limine-pxe.bin
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limine.bin
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stage2.map
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10
stage2/mm/vmm.c
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@ -44,13 +44,17 @@ void map_page(pagemap_t pagemap, uint64_t virt_addr, uint64_t phys_addr, uint64_
switch (pagemap.levels) {
case 5:
pml5 = pagemap.top_level;
pml4 = get_next_level(pml5, pml5_entry);
break;
goto level5;
case 4:
pml4 = pagemap.top_level;
break;
goto level4;
default:
panic("");
}
level5:
pml4 = get_next_level(pml5, pml5_entry);
level4:
pml3 = get_next_level(pml4, pml4_entry);
pml2 = get_next_level(pml3, pml3_entry);

6
stage2/protos/stivale.c
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@ -51,13 +51,11 @@ void stivale_load(char *cmdline) {
case 64: {
// Check if 64 bit CPU
uint32_t eax, ebx, ecx, edx;
cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
if (!(edx & (1 << 29))) {
if (!cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx) || !(edx & (1 << 29))) {
panic("stivale: This CPU does not support 64-bit mode.");
}
// Check if 5-level paging is available
cpuid(0x00000007, 0, &eax, &ebx, &ecx, &edx);
if (ecx & (1 << 16)) {
if (cpuid(0x00000007, 0, &eax, &ebx, &ecx, &edx) && (ecx & (1 << 16))) {
print("stivale: CPU has 5-level paging support\n");
level5pg = true;
}

10
stage2/protos/stivale2.c
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@ -74,14 +74,12 @@ void stivale2_load(char *cmdline) {
case 64: {
// Check if 64 bit CPU
uint32_t eax, ebx, ecx, edx;
cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
if (!(edx & (1 << 29))) {
panic("stivale2: This CPU does not support 64-bit mode.");
if (!cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx) || !(edx & (1 << 29))) {
panic("stivale: This CPU does not support 64-bit mode.");
}
// Check if 5-level paging is available
cpuid(0x00000007, 0, &eax, &ebx, &ecx, &edx);
if (ecx & (1 << 16)) {
print("stivale2: CPU has 5-level paging support\n");
if (cpuid(0x00000007, 0, &eax, &ebx, &ecx, &edx) && (ecx & (1 << 16))) {
print("stivale: CPU has 5-level paging support\n");
level5pg = true;
}

2
stage2/sys/smp.c
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@ -124,7 +124,7 @@ struct smp_information *init_smp(size_t header_hack_size,
x2apic = x2apic && x2apic_enable();
uint32_t bsp_x2apic_id;
uint32_t bsp_x2apic_id = 0;
if (x2apic) {
// The Intel manual recommends checking if leaf 0x1f exists first, and
// using that in place of 0xb if that's the case