docs: PROTOCOL.md: Fix minor grammar mistakes
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@ -149,7 +149,7 @@ The `MAIR_EL1` register will at least contain entries for the above-mentioned
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caching modes, in an unspecified order.
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In order to access MMIO regions, the kernel must ensure the correct caching mode
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is used on it's own.
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is used on its own.
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### riscv64
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@ -213,7 +213,7 @@ unless the an Entry Point feature is requested (see below), in which case,
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the value of `PC` is going to be taken from there.
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The contents of the `VBAR_EL1` register are undefined, and the kernel must load
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it's own.
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its own.
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The `MAIR_EL1` register contents are described above, in the caching section.
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