smp: aarch64: Don't needlessly invalidate the data cache
Also get rid of the function to do clean + invalidate as not to be tempted by it.
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@ -23,7 +23,6 @@ extern void delay(uint64_t cycles);
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extern size_t icache_line_size(void);
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extern size_t dcache_line_size(void);
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extern void clean_inval_dcache_poc(uintptr_t start, uintptr_t end);
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extern void clean_dcache_poc(uintptr_t start, uintptr_t end);
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extern void inval_icache_pou(uintptr_t start, uintptr_t end);
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extern int current_el(void);
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@ -252,19 +252,6 @@ inline size_t dcache_line_size(void) {
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return ((ctr >> 16) & 0b1111) << 4;
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}
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// Clean and invalidate D-Cache to Point of Coherency
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inline void clean_inval_dcache_poc(uintptr_t start, uintptr_t end) {
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size_t dsz = dcache_line_size();
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uintptr_t addr = start & ~(dsz - 1);
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while (addr < end) {
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asm volatile ("dc civac, %0" :: "r"(addr) : "memory");
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addr += dsz;
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}
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asm volatile ("dsb sy\n\tisb");
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}
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// Clean D-Cache to Point of Coherency
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inline void clean_dcache_poc(uintptr_t start, uintptr_t end) {
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size_t dsz = dcache_line_size();
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@ -366,7 +366,7 @@ static bool try_start_ap(int boot_method, uint64_t method_ptr,
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// Additionally, the newly-booted AP may have caches disabled which implies
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// it possibly does not see our cache contents either.
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clean_inval_dcache_poc((uintptr_t)trampoline, (uintptr_t)trampoline + 0x1000);
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clean_dcache_poc((uintptr_t)trampoline, (uintptr_t)trampoline + 0x1000);
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inval_icache_pou((uintptr_t)trampoline, (uintptr_t)trampoline + 0x1000);
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asm volatile ("" ::: "memory");
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@ -374,7 +374,7 @@ static bool try_start_ap(int boot_method, uint64_t method_ptr,
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switch (boot_method) {
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case BOOT_WITH_SPIN_TBL:
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*(volatile uint64_t *)method_ptr = (uint64_t)(uintptr_t)trampoline;
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clean_inval_dcache_poc(method_ptr, method_ptr + 8);
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clean_dcache_poc(method_ptr, method_ptr + 8);
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asm ("sev");
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break;
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