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paging: emulate support for 1gib pages if not avaliable 

Signed-off-by: Andy-Python-Programmer <andypythonappdeveloper@gmail.com>
This commit is contained in:
Andy-Python-Programmer 2022-01-27 15:01:59 +11:00
parent 51f5e5b092
commit 4af12fe517
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GPG Key ID: 80E0357347554B89
1 changed files with 29 additions and 2 deletions
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31
stage23/mm/vmm.c
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@ -39,6 +39,24 @@ pagemap_t new_pagemap(int lv) {
return pagemap; return pagemap;
} }
static bool is_1gib_page_supported() {
// Cache the cpuid result :^)
static bool CACHE_INIT = false;
static bool CACHE = false;
if (!CACHE_INIT) {
// Check if 1GiB pages are supported:
uint32_t eax, ebx, ecx, edx;
CACHE = cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx) && ((edx & 1 << 26) == 1 << 26);
CACHE_INIT = true;
print("paging: 1GiB pages are %s!\n", CACHE ? "supported" : "not supported");
}
return CACHE;
}
void map_page(pagemap_t pagemap, uint64_t virt_addr, uint64_t phys_addr, uint64_t flags, enum page_size pg_size) { void map_page(pagemap_t pagemap, uint64_t virt_addr, uint64_t phys_addr, uint64_t flags, enum page_size pg_size) {
// Calculate the indices in the various tables using the virtual address // Calculate the indices in the various tables using the virtual address
size_t pml5_entry = (virt_addr & ((uint64_t)0x1ff << 48)) >> 48; size_t pml5_entry = (virt_addr & ((uint64_t)0x1ff << 48)) >> 48;
@ -67,8 +85,17 @@ level4:
pml3 = get_next_level(pml4, pml4_entry); pml3 = get_next_level(pml4, pml4_entry);
if (pg_size == Size1GiB) { if (pg_size == Size1GiB) {
pml3[pml3_entry] = (pt_entry_t)(phys_addr | flags | (1 << 7)); // Check if 1GiB pages are avaliable.
return; if (is_1gib_page_supported()) {
pml3[pml3_entry] = (pt_entry_t)(phys_addr | flags | (1 << 7));
return;
} else {
// If 1GiB pages are not supported then emulate it by splitting them into
// 2MiB pages.
for (uint64_t i = 0; i < 0x40000000; i += 0x200000) {
map_page(pagemap, virt_addr + i, phys_addr + i, flags, Size2MiB);
}
}
} }
pml2 = get_next_level(pml3, pml3_entry); pml2 = get_next_level(pml3, pml3_entry);