docs: Initial Limine protocol draft
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# The Limine Boot Protocol
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The Limine boot protocol is a modern, minimal, fast, and extensible boot
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protocol, with a focus on backwards and forwards compatibility,
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created from the experienced gained by working on the
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[stivale boot protocols](https://github.com/stivale).
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This file serves as the official centralised collection of features that
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the Limine boot protocol is composed of. Other bootloaders may support extra
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unofficial features, but it is strongly recommended to avoid fragmentation
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and submit new features by opening a pull request to this repository.
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## Features
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The protocol is centered around the concept of request/response - collectively
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named "features" - where the kernel requests some action or information from
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the bootloader, and the bootloader responds accordingly, if it is capable of
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doing so.
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In C terms, a feature is composed of 2 structure: the request, and the response.
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A request has 3 mandatory members at the beginning of the structure:
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```c
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struct limine_example_request {
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uint64_t id[4];
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uint64_t revision;
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struct limine_example_response *response;
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... optional members follow ...
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};
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```
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* `id` - The ID of the request. This is an 8-byte aligned magic number that the
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bootloader will scan for inside the executable file to find requests. Requests
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may be located anywhere inside the executable as long as they are 8-byte
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aligned. There may only be 1 of the same request. The bootloader will refuse
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to boot an executable with multiple of the same request IDs.
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* `revision` - The revision of the request that the kernel provides. This is
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bumped whenever new members or functionality are added to the request structure.
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Bootloaders process requests in a backwards compatible manner, *always*. This
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means that if the bootloader does not support the revision of the request,
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it will process the request as if were the highest revision that the bootloader
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supports.
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* `response` - This field is filled in by the bootloader at load time, with a
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pointer to the response structure, if the request was successfully processed.
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If the request is unsupported or was not successfully processed, this field
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is *left untouched*, meaning that if it was set to `NULL`, it will stay that
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way.
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A response has only 1 mandatory member at the beginning of the structure:
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```c
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struct limine_example_response {
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uint64_t revision;
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... optional members follow ...
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};
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```
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* `revision` - Like for requests, bootloaders will instead mark responses with a
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revision number. This revision is not coupled between requests and responses,
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as they are bumped individually when new members are added or functionality is
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changed. Bootloaders will set the revision to the one they provide, and this is
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*always backwards compatible*, meaning higher revisions support all that lower
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revisions do.
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This is all there is to features. For a list of official Limine features, read
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the "Feature List" section below.
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## Executable memory layout
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The protocol mandates kernels to load themselves at or above
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`0xffffffff80000000`. Lower half kernels are *not supported*.
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At handoff, the kernel will be properly loaded and mapped with appropriate
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MMU permissions at the requested virtual memory address (provided it is at
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or above `0xffffffff80000000`).
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No specific physical memory placement is guaranteed. In order to determine
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where the kernel is loaded in physical memory, see the Kernel Address feature
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below.
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Alongside the loaded kernel, the bootloader will set up memory mappings as such:
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```
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Base Physical Address - Size -> Virtual address
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0x0000000000001000 - 4 GiB plus any additional memory map entry -> 0x0000000000001000
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0x0000000000000000 - 4 GiB plus any additional memory map entry -> HHDM start
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```
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Where HHDM start is returned by the Higher Half Direct Map feature (see below).
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These mappings are supervisor, read, write, execute (-rwx).
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The bootloader page tables are in bootloader-reclaimable memory (see Memory Map
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feature below), and their specific layout is undefined as long as they provide
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the above memory mappings.
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If the kernel is a position independent executable, the bootloader is free to
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relocate it as it sees fit, potentially performing KASLR (as specified by the
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config).
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## Entry machine state
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### x86_64
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`rip` will be the entry point as defined as part of the executable file format,
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unless the an Entry Point feature is requested (see below), in which case,
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the value of `rip` is going to be taken from there.
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At entry all segment registers are loaded as 64 bit code/data segments, limits
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and bases are ignored since this is 64-bit mode.
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The GDT register is loaded to point to a GDT, in bootloader-reserved memory,
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with at least the following entries, starting at offset 0:
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- Null descriptor
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- 16-bit code descriptor. Base = `0`, limit = `0xffff`. Readable.
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- 16-bit data descriptor. Base = `0`, limit = `0xffff`. Writable.
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- 32-bit code descriptor. Base = `0`, limit = `0xffffffff`. Readable.
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- 32-bit data descriptor. Base = `0`, limit = `0xffffffff`. Writable.
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- 64-bit code descriptor. Base and limit irrelevant. Readable.
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- 64-bit data descriptor. Base and limit irrelevant. Writable.
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The IDT is in an undefined state. Kernel must load its own.
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IF flag, VM flag, and direction flag are cleared on entry. Other flags undefined.
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PG is enabled (`cr0`), PE is enabled (`cr0`), PAE is enabled (`cr4`),
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LME is enabled (`EFER`).
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If 5-level paging is requested and available, then 5-level paging is enabled
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(LA57 bit in `cr4`).
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The NX bit will be enabled (NX bit in `EFER`).
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The A20 gate is opened.
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Legacy PIC and IO APIC IRQs are all masked.
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If booted by EFI/UEFI, boot services are exited.
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`rsp` is set to point to a stack, in bootloader-reserved memory, which is
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at least 8KiB (8192 bytes) in size. An invalid return address of 0 is pushed
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to the stack before jumping to the kernel.
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All other general purpose registers are set to 0.
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