limine: Make WP flag enabled as per spec
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6caaada636
commit
15f111f5c3
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@ -137,10 +137,9 @@ IF flag, VM flag, and direction flag are cleared on entry. Other flags
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undefined.
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PG is enabled (`cr0`), PE is enabled (`cr0`), PAE is enabled (`cr4`),
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LME is enabled (`EFER`).
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WP is enabled (`cr0`), LME is enabled (`EFER`), NX is enabled (`EFER`).
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If 5-level paging is requested and available, then 5-level paging is enabled
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(LA57 bit in `cr4`).
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The NX bit will be enabled (NX bit in `EFER`).
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The A20 gate is opened.
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@ -699,7 +699,7 @@ FEAT_START
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&cpu_count, &bsp_lapic_id,
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true, want_5lv,
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pagemap, smp_request->flags & LIMINE_SMP_X2APIC, true,
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direct_map_offset);
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direct_map_offset, true);
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if (smp_info == NULL) {
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break;
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@ -800,7 +800,7 @@ FEAT_END
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term_runtime = true;
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stivale_spinup(64, want_5lv, &pagemap, entry_point, 0,
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reported_addr(stack), true, (uintptr_t)local_gdt);
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reported_addr(stack), true, true, (uintptr_t)local_gdt);
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__builtin_unreachable();
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}
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@ -5,7 +5,7 @@
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#include <mm/vmm.h>
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noreturn void stivale_spinup_32(
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int bits, bool level5pg, bool enable_nx, uint32_t pagemap_top_lv,
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int bits, bool level5pg, bool enable_nx, bool wp, uint32_t pagemap_top_lv,
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uint32_t entry_point_lo, uint32_t entry_point_hi,
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uint32_t stivale_struct_lo, uint32_t stivale_struct_hi,
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uint32_t stack_lo, uint32_t stack_hi,
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@ -38,6 +38,15 @@ noreturn void stivale_spinup_32(
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);
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}
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if (wp) {
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asm volatile (
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"movl %%cr0, %%eax\n\t"
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"btsl $16, %%eax\n\t"
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"movl %%eax, %%cr0\n\t"
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::: "eax", "memory"
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);
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}
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asm volatile (
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"cld\n\t"
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"movl %%eax, %%cr3\n\t"
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@ -368,7 +368,7 @@ bool stivale_load(char *config, char *cmdline) {
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stivale_spinup(bits, want_5lv, &pagemap,
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entry_point, REPORTED_ADDR((uint64_t)(uintptr_t)stivale_struct),
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stivale_hdr.stack, false, (uintptr_t)local_gdt);
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stivale_hdr.stack, false, false, (uintptr_t)local_gdt);
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__builtin_unreachable();
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@ -487,7 +487,7 @@ noreturn void stivale_spinup_32(
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noreturn void stivale_spinup(
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int bits, bool level5pg, pagemap_t *pagemap,
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uint64_t entry_point, uint64_t _stivale_struct, uint64_t stack,
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bool enable_nx, uint32_t local_gdt) {
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bool enable_nx, bool wp, uint32_t local_gdt) {
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#if bios == 1
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if (bits == 64) {
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// If we're going 64, we might as well call this BIOS interrupt
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@ -509,8 +509,8 @@ noreturn void stivale_spinup(
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irq_flush_type = IRQ_PIC_APIC_FLUSH;
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common_spinup(stivale_spinup_32, 11,
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bits, level5pg, enable_nx, (uint32_t)(uintptr_t)pagemap->top_level,
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common_spinup(stivale_spinup_32, 12,
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bits, level5pg, enable_nx, wp, (uint32_t)(uintptr_t)pagemap->top_level,
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(uint32_t)entry_point, (uint32_t)(entry_point >> 32),
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(uint32_t)_stivale_struct, (uint32_t)(_stivale_struct >> 32),
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(uint32_t)stack, (uint32_t)(stack >> 32), local_gdt);
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@ -17,6 +17,6 @@ pagemap_t stivale_build_pagemap(bool level5pg, bool unmap_null, struct elf_range
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noreturn void stivale_spinup(
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int bits, bool level5pg, pagemap_t *pagemap,
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uint64_t entry_point, uint64_t stivale_struct, uint64_t stack,
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bool enable_nx, uint32_t local_gdt);
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bool enable_nx, bool wp, uint32_t local_gdt);
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#endif
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@ -765,7 +765,8 @@ have_tm_tag:;
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&cpu_count, &bsp_lapic_id,
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bits == 64, want_5lv,
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pagemap, smp_hdr_tag->flags & 1, want_pmrs,
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stivale2_hdr.flags & (1 << 1) ? direct_map_offset : 0);
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stivale2_hdr.flags & (1 << 1) ? direct_map_offset : 0,
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want_pmrs);
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if (smp_info != NULL) {
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tag->tag.identifier = STIVALE2_STRUCT_TAG_SMP_ID;
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@ -833,7 +834,7 @@ have_tm_tag:;
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stivale_spinup(bits, want_5lv, &pagemap, entry_point,
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REPORTED_ADDR((uint64_t)(uintptr_t)stivale2_struct),
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stivale2_hdr.stack, want_pmrs, (uintptr_t)local_gdt);
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stivale2_hdr.stack, want_pmrs, want_pmrs, (uintptr_t)local_gdt);
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__builtin_unreachable();
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@ -54,7 +54,7 @@ struct trampoline_passed_info {
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static bool smp_start_ap(uint32_t lapic_id, struct gdtr *gdtr,
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struct smp_information *info_struct,
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bool longmode, bool lv5, uint32_t pagemap,
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bool x2apic, bool nx, uint64_t hhdm) {
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bool x2apic, bool nx, uint64_t hhdm, bool wp) {
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size_t trampoline_size = (size_t)_binary_smp_trampoline_bin_end
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- (size_t)_binary_smp_trampoline_bin_start;
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@ -78,6 +78,7 @@ static bool smp_start_ap(uint32_t lapic_id, struct gdtr *gdtr,
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passed_info->smp_tpl_target_mode = ((uint32_t)x2apic << 2)
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| ((uint32_t)lv5 << 1)
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| ((uint32_t)nx << 3)
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| ((uint32_t)wp << 4)
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| (uint32_t)longmode;
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passed_info->smp_tpl_gdt = *gdtr;
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passed_info->smp_tpl_booted_flag = 0;
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@ -122,7 +123,8 @@ struct smp_information *init_smp(size_t header_hack_size,
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pagemap_t pagemap,
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bool x2apic,
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bool nx,
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uint64_t hhdm) {
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uint64_t hhdm,
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bool wp) {
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if (!lapic_check())
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return NULL;
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@ -227,7 +229,7 @@ struct smp_information *init_smp(size_t header_hack_size,
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// Try to start the AP
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if (!smp_start_ap(lapic->lapic_id, &gdtr, info_struct,
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longmode, lv5, (uintptr_t)pagemap.top_level,
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x2apic, nx, hhdm)) {
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x2apic, nx, hhdm, wp)) {
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print("smp: FAILED to bring-up AP\n");
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continue;
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}
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@ -264,7 +266,7 @@ struct smp_information *init_smp(size_t header_hack_size,
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// Try to start the AP
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if (!smp_start_ap(x2lapic->x2apic_id, &gdtr, info_struct,
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longmode, lv5, (uintptr_t)pagemap.top_level,
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true, nx, hhdm)) {
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true, nx, hhdm, wp)) {
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print("smp: FAILED to bring-up AP\n");
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continue;
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}
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@ -23,6 +23,7 @@ struct smp_information *init_smp(size_t header_hack_size,
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pagemap_t pagemap,
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bool x2apic,
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bool nx,
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uint64_t hhdm);
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uint64_t hhdm,
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bool wp);
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#endif
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@ -101,6 +101,14 @@ smp_trampoline:
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wrmsr
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.nonx:
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test dword [rbx + passed_info.target_mode], (1 << 4)
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jz .nowp
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mov rax, cr0
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bts rax, 16
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mov cr0, rax
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.nowp:
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mov rax, qword [rbx + passed_info.hhdm]
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add qword [rbx + passed_info.gdtr + 2], rax
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lgdt [rbx + passed_info.gdtr]
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