Merge pull request #295 from qookei/arm-cache

AArch64 cache-related changes

PROTOCOL.md

@@ -128,6 +128,9 @@ The MTRRs are left as the firmware set them up.
 
 ### aarch64
 
+The kernel executable, loaded at or above `0xffffffff80000000`, see all of its
+segments mapped using Normal Write-Back RW-Allocate non-transient caching mode.
+
 All HHDM memory regions are mapped using the Normal Write-Back RW-Allocate
 non-transient caching mode, except for the framebuffer regions, which are
 mapped in using an unspecified caching mode, correct for use with the

common/lib/elf.c

@@ -577,7 +577,7 @@ again:
         }
 
 #if defined (__aarch64__)
-        clean_inval_dcache_poc(mem_base, mem_base + mem_size);
+        clean_dcache_poc(mem_base, mem_base + mem_size);
         inval_icache_pou(mem_base, mem_base + mem_size);
 #endif
     }

common/sys/cpu.c

@@ -24,5 +24,6 @@ extern void delay(uint64_t cycles);
 extern size_t icache_line_size(void);
 extern size_t dcache_line_size(void);
 extern void clean_inval_dcache_poc(uintptr_t start, uintptr_t end);
+extern void clean_dcache_poc(uintptr_t start, uintptr_t end);
 extern void inval_icache_pou(uintptr_t start, uintptr_t end);
 extern int current_el(void);

common/sys/cpu.h

@@ -265,6 +265,19 @@ inline void clean_inval_dcache_poc(uintptr_t start, uintptr_t end) {
     asm volatile ("dsb sy\n\tisb");
 }
 
+// Clean D-Cache to Point of Coherency
+inline void clean_dcache_poc(uintptr_t start, uintptr_t end) {
+    size_t dsz = dcache_line_size();
+
+    uintptr_t addr = start & ~(dsz - 1);
+    while (addr < end) {
+        asm volatile ("dc cvac, %0" :: "r"(addr) : "memory");
+        addr += dsz;
+    }
+
+    asm volatile ("dsb sy\n\tisb");
+}
+
 // Invalidate I-Cache to Point of Unification
 inline void inval_icache_pou(uintptr_t start, uintptr_t end) {
     size_t isz = icache_line_size();