109 lines
2.0 KiB
Plaintext
109 lines
2.0 KiB
Plaintext
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#include <lib/macros.aarch64_asm.h>
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// noreturn void enter_in_current_el(uint64_t entry, uint64_t sp, uint64_t sctlr,
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// uint64_t target_x0)
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// Configure current EL state and jump to kernel. Used for Linux hence
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// no paging register configuration (which requires SCTLR.M = 0).
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.global enter_in_current_el
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enter_in_current_el:
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msr sp_el0, x1
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// Sanity check that SCTLR.M = 0
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and x8, x2, #0b1
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cbnz x8, 99f
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99:
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wfi
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b 99b
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PICK_EL x8, 0f, 1f
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0:
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msr sctlr_el1, x2
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dsb sy
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isb
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// Enter kernel in EL1
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mov x8, #0x3c4
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msr spsr_el1, x8
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msr elr_el1, x0
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mov x0, x3
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ZERO_REGS_EXCEPT_X0
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eret
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1:
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msr sctlr_el2, x2
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dsb sy
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isb
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// Enter kernel in EL2
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mov x8, #0x3c8
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msr spsr_el2, x8
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msr elr_el2, x0
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mov x0, x3
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ZERO_REGS_EXCEPT_X0
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eret
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// noreturn void enter_in_el1(uint64_t entry, uint64_t sp, uint64_t sctlr,
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// uint64_t mair, uint64_t tcr, uint64_t ttbr0,
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// uint64_t ttbr1, uint64_t target_x0)
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// Potentially drop to EL1 from EL2 (and also disable trapping to EL2), then
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// configure EL1 state and jump to kernel.
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.global enter_in_el1
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enter_in_el1:
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msr spsel, #0
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mov sp, x1
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// Configure EL1 state
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msr mair_el1, x3
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msr tcr_el1, x4
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msr ttbr0_el1, x5
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msr ttbr1_el1, x6
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msr sctlr_el1, x2
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dsb sy
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isb
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PICK_EL x8, 0f, 1f
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0:
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// Enter kernel in EL1
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mov x8, #0x3c4
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msr spsr_el1, x8
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msr elr_el1, x0
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mov x0, x7
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ZERO_REGS_EXCEPT_X0
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eret
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1:
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// Configure EL2-specific state for EL1
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// Don't trap counters to EL2
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mrs x8, cnthctl_el2
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orr x8, x8, #3
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msr cnthctl_el2, x8
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msr cntvoff_el2, xzr
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// Enable AArch64 in EL1
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ldr x8, =0x80000002
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msr hcr_el2, x8
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// Don't trap FP/SIMD to EL2
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mov x8, #0x33FF
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msr cptr_el2, x8
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msr hstr_el2, xzr
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// Enter kernel in EL1
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mov x8, #0x3c4
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msr spsr_el2, x8
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msr elr_el2, x0
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mov x0, x7
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ZERO_REGS_EXCEPT_X0
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eret
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