629 lines
17 KiB
C
629 lines
17 KiB
C
// SPDX-License-Identifier: GPL-1.0+
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/*
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* OHCI HCD (Host Controller Driver) for USB.
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*
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* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
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* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
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* (C) Copyright 2002 Hewlett-Packard Company
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*
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* Bus Glue for pxa27x
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*
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* Written by Christopher Hoover <ch@hpl.hp.com>
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* Based on fragments of previous driver by Russell King et al.
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*
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* Modified for LH7A404 from ohci-sa1111.c
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* by Durgesh Pattamatta <pattamattad@sharpsec.com>
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*
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* Modified for pxa27x from ohci-lh7a404.c
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* by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
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*
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* This file is licenced under the GPL.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_data/usb-ohci-pxa27x.h>
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#include <linux/platform_data/usb-pxa3xx-ulpi.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/signal.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include <linux/usb/otg.h>
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#include <mach/hardware.h>
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#include "ohci.h"
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#define DRIVER_DESC "OHCI PXA27x/PXA3x driver"
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/*
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* UHC: USB Host Controller (OHCI-like) register definitions
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*/
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#define UHCREV (0x0000) /* UHC HCI Spec Revision */
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#define UHCHCON (0x0004) /* UHC Host Control Register */
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#define UHCCOMS (0x0008) /* UHC Command Status Register */
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#define UHCINTS (0x000C) /* UHC Interrupt Status Register */
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#define UHCINTE (0x0010) /* UHC Interrupt Enable */
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#define UHCINTD (0x0014) /* UHC Interrupt Disable */
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#define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
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#define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
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#define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
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#define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
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#define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
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#define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
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#define UHCDHEAD (0x0030) /* UHC Done Head */
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#define UHCFMI (0x0034) /* UHC Frame Interval */
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#define UHCFMR (0x0038) /* UHC Frame Remaining */
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#define UHCFMN (0x003C) /* UHC Frame Number */
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#define UHCPERS (0x0040) /* UHC Periodic Start */
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#define UHCLS (0x0044) /* UHC Low Speed Threshold */
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#define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
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#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
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#define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
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#define UHCRHDA_POTPGT(x) \
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(((x) & 0xff) << 24) /* Power On To Power Good Time */
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#define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
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#define UHCRHS (0x0050) /* UHC Root Hub Status */
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#define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
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#define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
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#define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
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#define UHCSTAT (0x0060) /* UHC Status Register */
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#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
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#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
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#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
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#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
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#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
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#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
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#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
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#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
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#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
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#define UHCHR (0x0064) /* UHC Reset Register */
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#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
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#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
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#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
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#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
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#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
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#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
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#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
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#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
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#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
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#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
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#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
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#define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
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#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
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#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
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#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
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#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
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#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
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Interrupt Enable*/
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#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
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#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
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#define UHCHIT (0x006C) /* UHC Interrupt Test register */
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#define PXA_UHC_MAX_PORTNUM 3
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static const char hcd_name[] = "ohci-pxa27x";
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static struct hc_driver __read_mostly ohci_pxa27x_hc_driver;
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struct pxa27x_ohci {
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struct clk *clk;
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void __iomem *mmio_base;
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struct regulator *vbus[3];
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bool vbus_enabled[3];
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};
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#define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv)
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/*
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PMM_NPS_MODE -- PMM Non-power switching mode
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Ports are powered continuously.
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PMM_GLOBAL_MODE -- PMM global switching mode
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All ports are powered at the same time.
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PMM_PERPORT_MODE -- PMM per port switching mode
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Ports are powered individually.
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*/
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static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode)
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{
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uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
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uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);
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switch (mode) {
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case PMM_NPS_MODE:
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uhcrhda |= RH_A_NPS;
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break;
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case PMM_GLOBAL_MODE:
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uhcrhda &= ~(RH_A_NPS | RH_A_PSM);
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break;
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case PMM_PERPORT_MODE:
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uhcrhda &= ~(RH_A_NPS);
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uhcrhda |= RH_A_PSM;
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/* Set port power control mask bits, only 3 ports. */
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uhcrhdb |= (0x7<<17);
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break;
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default:
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printk( KERN_ERR
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"Invalid mode %d, set to non-power switch mode.\n",
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mode );
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uhcrhda |= RH_A_NPS;
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}
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__raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
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__raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
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return 0;
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}
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static int pxa27x_ohci_set_vbus_power(struct pxa27x_ohci *pxa_ohci,
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unsigned int port, bool enable)
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{
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struct regulator *vbus = pxa_ohci->vbus[port];
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int ret = 0;
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if (IS_ERR_OR_NULL(vbus))
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return 0;
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if (enable && !pxa_ohci->vbus_enabled[port])
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ret = regulator_enable(vbus);
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else if (!enable && pxa_ohci->vbus_enabled[port])
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ret = regulator_disable(vbus);
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if (ret < 0)
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return ret;
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pxa_ohci->vbus_enabled[port] = enable;
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return 0;
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}
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static int pxa27x_ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
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u16 wIndex, char *buf, u16 wLength)
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{
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struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
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int ret;
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switch (typeReq) {
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case SetPortFeature:
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case ClearPortFeature:
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if (!wIndex || wIndex > 3)
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return -EPIPE;
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if (wValue != USB_PORT_FEAT_POWER)
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break;
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ret = pxa27x_ohci_set_vbus_power(pxa_ohci, wIndex - 1,
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typeReq == SetPortFeature);
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if (ret)
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return ret;
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break;
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}
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return ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
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}
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/*-------------------------------------------------------------------------*/
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static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci,
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struct pxaohci_platform_data *inf)
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{
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uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
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uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
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if (inf->flags & ENABLE_PORT1)
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uhchr &= ~UHCHR_SSEP1;
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if (inf->flags & ENABLE_PORT2)
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uhchr &= ~UHCHR_SSEP2;
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if (inf->flags & ENABLE_PORT3)
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uhchr &= ~UHCHR_SSEP3;
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if (inf->flags & POWER_CONTROL_LOW)
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uhchr |= UHCHR_PCPL;
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if (inf->flags & POWER_SENSE_LOW)
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uhchr |= UHCHR_PSPL;
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if (inf->flags & NO_OC_PROTECTION)
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uhcrhda |= UHCRHDA_NOCP;
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else
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uhcrhda &= ~UHCRHDA_NOCP;
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if (inf->flags & OC_MODE_PERPORT)
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uhcrhda |= UHCRHDA_OCPM;
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else
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uhcrhda &= ~UHCRHDA_OCPM;
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if (inf->power_on_delay) {
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uhcrhda &= ~UHCRHDA_POTPGT(0xff);
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uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
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}
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__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
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__raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
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}
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static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci)
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{
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uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
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__raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
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udelay(11);
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__raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
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}
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#ifdef CONFIG_PXA27x
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extern void pxa27x_clear_otgph(void);
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#else
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#define pxa27x_clear_otgph() do {} while (0)
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#endif
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static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
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{
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int retval;
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struct pxaohci_platform_data *inf;
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uint32_t uhchr;
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struct usb_hcd *hcd = dev_get_drvdata(dev);
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inf = dev_get_platdata(dev);
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retval = clk_prepare_enable(pxa_ohci->clk);
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if (retval)
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return retval;
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pxa27x_reset_hc(pxa_ohci);
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uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
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__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
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while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
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cpu_relax();
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pxa27x_setup_hc(pxa_ohci, inf);
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if (inf->init)
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retval = inf->init(dev);
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if (retval < 0) {
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clk_disable_unprepare(pxa_ohci->clk);
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return retval;
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}
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if (cpu_is_pxa3xx())
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pxa3xx_u2d_start_hc(&hcd->self);
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uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
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__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
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__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);
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/* Clear any OTG Pin Hold */
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pxa27x_clear_otgph();
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return 0;
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}
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static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
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{
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struct pxaohci_platform_data *inf;
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struct usb_hcd *hcd = dev_get_drvdata(dev);
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uint32_t uhccoms;
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inf = dev_get_platdata(dev);
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if (cpu_is_pxa3xx())
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pxa3xx_u2d_stop_hc(&hcd->self);
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if (inf->exit)
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inf->exit(dev);
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pxa27x_reset_hc(pxa_ohci);
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/* Host Controller Reset */
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uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01;
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__raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);
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udelay(10);
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clk_disable_unprepare(pxa_ohci->clk);
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}
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#ifdef CONFIG_OF
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static const struct of_device_id pxa_ohci_dt_ids[] = {
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{ .compatible = "marvell,pxa-ohci" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);
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static int ohci_pxa_of_init(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct pxaohci_platform_data *pdata;
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u32 tmp;
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int ret;
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if (!np)
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return 0;
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/* Right now device-tree probed devices don't get dma_mask set.
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* Since shared usb code relies on it, set it here for now.
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* Once we have dma capability bindings this can go away.
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*/
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ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
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if (ret)
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return ret;
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return -ENOMEM;
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if (of_property_read_bool(np, "marvell,enable-port1"))
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pdata->flags |= ENABLE_PORT1;
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if (of_property_read_bool(np, "marvell,enable-port2"))
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pdata->flags |= ENABLE_PORT2;
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if (of_property_read_bool(np, "marvell,enable-port3"))
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pdata->flags |= ENABLE_PORT3;
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if (of_property_read_bool(np, "marvell,port-sense-low"))
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pdata->flags |= POWER_SENSE_LOW;
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if (of_property_read_bool(np, "marvell,power-control-low"))
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pdata->flags |= POWER_CONTROL_LOW;
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if (of_property_read_bool(np, "marvell,no-oc-protection"))
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pdata->flags |= NO_OC_PROTECTION;
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if (of_property_read_bool(np, "marvell,oc-mode-perport"))
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pdata->flags |= OC_MODE_PERPORT;
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if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp))
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pdata->power_on_delay = tmp;
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if (!of_property_read_u32(np, "marvell,port-mode", &tmp))
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pdata->port_mode = tmp;
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if (!of_property_read_u32(np, "marvell,power-budget", &tmp))
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pdata->power_budget = tmp;
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pdev->dev.platform_data = pdata;
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return 0;
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}
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#else
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static int ohci_pxa_of_init(struct platform_device *pdev)
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{
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return 0;
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}
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#endif
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/*-------------------------------------------------------------------------*/
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/* configure so an HC device and id are always provided */
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/* always called with process context; sleeping is OK */
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/**
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* ohci_hcd_pxa27x_probe - initialize pxa27x-based HCDs
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* Context: !in_interrupt()
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*
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* Allocates basic resources for this USB host controller, and
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* then invokes the start() method for the HCD associated with it
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* through the hotplug entry's driver_data.
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*
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*/
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static int ohci_hcd_pxa27x_probe(struct platform_device *pdev)
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{
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int retval, irq;
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struct usb_hcd *hcd;
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struct pxaohci_platform_data *inf;
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struct pxa27x_ohci *pxa_ohci;
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struct ohci_hcd *ohci;
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struct resource *r;
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struct clk *usb_clk;
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unsigned int i;
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retval = ohci_pxa_of_init(pdev);
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if (retval)
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return retval;
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inf = dev_get_platdata(&pdev->dev);
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if (!inf)
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return -ENODEV;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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pr_err("no resource of IORESOURCE_IRQ");
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return irq;
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}
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usb_clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(usb_clk))
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return PTR_ERR(usb_clk);
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|
|
hcd = usb_create_hcd(&ohci_pxa27x_hc_driver, &pdev->dev, "pxa27x");
|
|
if (!hcd)
|
|
return -ENOMEM;
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
hcd->regs = devm_ioremap_resource(&pdev->dev, r);
|
|
if (IS_ERR(hcd->regs)) {
|
|
retval = PTR_ERR(hcd->regs);
|
|
goto err;
|
|
}
|
|
hcd->rsrc_start = r->start;
|
|
hcd->rsrc_len = resource_size(r);
|
|
|
|
/* initialize "struct pxa27x_ohci" */
|
|
pxa_ohci = to_pxa27x_ohci(hcd);
|
|
pxa_ohci->clk = usb_clk;
|
|
pxa_ohci->mmio_base = (void __iomem *)hcd->regs;
|
|
|
|
for (i = 0; i < 3; ++i) {
|
|
char name[6];
|
|
|
|
if (!(inf->flags & (ENABLE_PORT1 << i)))
|
|
continue;
|
|
|
|
sprintf(name, "vbus%u", i + 1);
|
|
pxa_ohci->vbus[i] = devm_regulator_get(&pdev->dev, name);
|
|
}
|
|
|
|
retval = pxa27x_start_hc(pxa_ohci, &pdev->dev);
|
|
if (retval < 0) {
|
|
pr_debug("pxa27x_start_hc failed");
|
|
goto err;
|
|
}
|
|
|
|
/* Select Power Management Mode */
|
|
pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
|
|
|
|
if (inf->power_budget)
|
|
hcd->power_budget = inf->power_budget;
|
|
|
|
/* The value of NDP in roothub_a is incorrect on this hardware */
|
|
ohci = hcd_to_ohci(hcd);
|
|
ohci->num_ports = 3;
|
|
|
|
retval = usb_add_hcd(hcd, irq, 0);
|
|
if (retval == 0) {
|
|
device_wakeup_enable(hcd->self.controller);
|
|
return retval;
|
|
}
|
|
|
|
pxa27x_stop_hc(pxa_ohci, &pdev->dev);
|
|
err:
|
|
usb_put_hcd(hcd);
|
|
return retval;
|
|
}
|
|
|
|
|
|
/* may be called without controller electrically present */
|
|
/* may be called with controller, bus, and devices active */
|
|
|
|
/**
|
|
* ohci_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
|
|
* @dev: USB Host Controller being removed
|
|
* Context: !in_interrupt()
|
|
*
|
|
* Reverses the effect of ohci_hcd_pxa27x_probe(), first invoking
|
|
* the HCD's stop() method. It is always called from a thread
|
|
* context, normally "rmmod", "apmd", or something similar.
|
|
*
|
|
*/
|
|
static int ohci_hcd_pxa27x_remove(struct platform_device *pdev)
|
|
{
|
|
struct usb_hcd *hcd = platform_get_drvdata(pdev);
|
|
struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
|
|
unsigned int i;
|
|
|
|
usb_remove_hcd(hcd);
|
|
pxa27x_stop_hc(pxa_ohci, &pdev->dev);
|
|
|
|
for (i = 0; i < 3; ++i)
|
|
pxa27x_ohci_set_vbus_power(pxa_ohci, i, false);
|
|
|
|
usb_put_hcd(hcd);
|
|
return 0;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
#ifdef CONFIG_PM
|
|
static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
|
|
{
|
|
struct usb_hcd *hcd = dev_get_drvdata(dev);
|
|
struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
|
|
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
|
|
bool do_wakeup = device_may_wakeup(dev);
|
|
int ret;
|
|
|
|
|
|
if (time_before(jiffies, ohci->next_statechange))
|
|
msleep(5);
|
|
ohci->next_statechange = jiffies;
|
|
|
|
ret = ohci_suspend(hcd, do_wakeup);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pxa27x_stop_hc(pxa_ohci, dev);
|
|
return ret;
|
|
}
|
|
|
|
static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
|
|
{
|
|
struct usb_hcd *hcd = dev_get_drvdata(dev);
|
|
struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
|
|
struct pxaohci_platform_data *inf = dev_get_platdata(dev);
|
|
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
|
|
int status;
|
|
|
|
if (time_before(jiffies, ohci->next_statechange))
|
|
msleep(5);
|
|
ohci->next_statechange = jiffies;
|
|
|
|
status = pxa27x_start_hc(pxa_ohci, dev);
|
|
if (status < 0)
|
|
return status;
|
|
|
|
/* Select Power Management Mode */
|
|
pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
|
|
|
|
ohci_resume(hcd, false);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
|
|
.suspend = ohci_hcd_pxa27x_drv_suspend,
|
|
.resume = ohci_hcd_pxa27x_drv_resume,
|
|
};
|
|
#endif
|
|
|
|
static struct platform_driver ohci_hcd_pxa27x_driver = {
|
|
.probe = ohci_hcd_pxa27x_probe,
|
|
.remove = ohci_hcd_pxa27x_remove,
|
|
.shutdown = usb_hcd_platform_shutdown,
|
|
.driver = {
|
|
.name = "pxa27x-ohci",
|
|
.of_match_table = of_match_ptr(pxa_ohci_dt_ids),
|
|
#ifdef CONFIG_PM
|
|
.pm = &ohci_hcd_pxa27x_pm_ops,
|
|
#endif
|
|
},
|
|
};
|
|
|
|
static const struct ohci_driver_overrides pxa27x_overrides __initconst = {
|
|
.extra_priv_size = sizeof(struct pxa27x_ohci),
|
|
};
|
|
|
|
static int __init ohci_pxa27x_init(void)
|
|
{
|
|
if (usb_disabled())
|
|
return -ENODEV;
|
|
|
|
pr_info("%s: " DRIVER_DESC "\n", hcd_name);
|
|
|
|
ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides);
|
|
ohci_pxa27x_hc_driver.hub_control = pxa27x_ohci_hub_control;
|
|
|
|
return platform_driver_register(&ohci_hcd_pxa27x_driver);
|
|
}
|
|
module_init(ohci_pxa27x_init);
|
|
|
|
static void __exit ohci_pxa27x_cleanup(void)
|
|
{
|
|
platform_driver_unregister(&ohci_hcd_pxa27x_driver);
|
|
}
|
|
module_exit(ohci_pxa27x_cleanup);
|
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:pxa27x-ohci");
|