123 lines
3.7 KiB
Diff
123 lines
3.7 KiB
Diff
--- a/src/hd/cpu.c 2020-02-20 20:48:57.078283266 +0300
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+++ b/src/hd/cpu.c 2020-02-20 20:57:29.405932805 +0300
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@@ -104,6 +104,7 @@
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#ifdef __alpha__
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char model_id[80], system_id[80], serial_number[80], platform[80];
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unsigned cpu_variation, cpu_revision, u, hz;
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+ double bogo;
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cpu_info_t *ct1;
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#endif
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@@ -154,6 +155,12 @@
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char uarch[80];
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#endif
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+#if defined __e2k__
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+ char model_id[80], vendor_id[80];
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+ unsigned mhz, cache, family, model, cpu_revision;
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+ double bogo;
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+#endif
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+
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hd_data->cpu = read_file(PROC_CPUINFO, 0, 0);
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if((hd_data->debug & HD_DEB_CPU)) dump_cpu_data(hd_data);
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if(!hd_data->cpu) return;
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@@ -161,6 +168,7 @@
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#ifdef __alpha__
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*model_id = *system_id = *serial_number = *platform = 0;
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cpu_variation = cpu_revision = hz = 0;
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+ bogo = 0;
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for(sl = hd_data->cpu; sl; sl = sl->next) {
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if(sscanf(sl->str, "cpu model : %79[^\n]", model_id) == 1) continue;
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@@ -171,6 +179,7 @@
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if(sscanf(sl->str, "cpus detected : %u", &cpus) == 1) continue;
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if(sscanf(sl->str, "cycle frequency [Hz] : %u", &hz) == 1) continue;
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if(sscanf(sl->str, "system variation : %79[^\n]", platform) == 1) continue;
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+ if(sscanf(sl->str, "BogoMIPS : %lg", &bogo) == 1) continue;
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}
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if(*model_id || *system_id) { /* at least one of those */
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@@ -715,6 +724,82 @@
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}
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}
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#endif /* __riscv */
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+
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+#if defined __e2k__
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+ *model_id = *vendor_id = 0;
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+ mhz = cache = family = model = cpu_revision = 0;
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+ bogo = 0;
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+
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+ for(sl = hd_data->cpu; sl; sl = sl->next) {
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+ if(sscanf(sl->str, "model name : %79[^\n]", model_id) == 1);
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+ if(sscanf(sl->str, "vendor_id : %79[^\n]", vendor_id) == 1);
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+ if(sscanf(sl->str, "bogomips : %lg", &bogo) == 1);
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+ if(sscanf(sl->str, "cpu MHz : %u", &mhz) == 1);
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+ if(sscanf(sl->str, "L2 cache size : %u KB", &cache) == 1);
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+
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+ if(sscanf(sl->str, "cpu family : %u", &family) == 1);
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+ if(sscanf(sl->str, "model : %u", &model) == 1);
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+ if(sscanf(sl->str, "revision : %u", &cpu_revision) == 1);
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+
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+ if(strstr(sl->str, "processor") == sl->str || !sl->next) { /* EOF */
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+ if(*model_id || *vendor_id) { /* at least one of those */
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+ ct = new_mem(sizeof *ct);
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+ ct->architecture = arch_e2k;
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+ if(*model_id) ct->model_name = new_str(model_id);
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+ if(*vendor_id) ct->vend_name = new_str(vendor_id);
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+ ct->family = family;
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+ ct->model = model;
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+ ct->stepping = cpu_revision;
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+ ct->cache = cache;
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+ ct->bogo = bogo;
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+
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+ /* round clock to typical values */
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+ if(mhz >= 38 && mhz <= 42)
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+ mhz = 40;
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+ else if(mhz >= 88 && mhz <= 92)
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+ mhz = 90;
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+ else {
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+ unsigned u, v;
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+
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+ u = (mhz + 2) % 100;
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+ v = (mhz + 2) / 100;
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+ if(u <= 4)
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+ u = 2;
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+ else if(u >= 25 && u <= 29)
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+ u = 25 + 2;
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+ else if(u >= 33 && u <= 37)
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+ u = 33 + 2;
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+ else if(u >= 50 && u <= 54)
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+ u = 50 + 2;
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+ else if(u >= 66 && u <= 70)
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+ u = 66 + 2;
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+ else if(u >= 75 && u <= 79)
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+ u = 75 + 2;
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+ else if(u >= 80 && u <= 84) /* there are 180MHz PPros */
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+ u = 80 + 2;
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+ u -= 2;
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+ mhz = v * 100 + u;
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+ }
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+
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+ ct->clock = mhz;
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+
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+ hd = add_hd_entry(hd_data, __LINE__, 0);
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+ hd->base_class.id = bc_internal;
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+ hd->sub_class.id = sc_int_cpu;
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+ hd->slot = cpus;
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+ hd->detail = new_mem(sizeof *hd->detail);
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+ hd->detail->type = hd_detail_cpu;
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+ hd->detail->cpu.data = ct;
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+
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+ *model_id = *vendor_id = 0;
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+ mhz = cache = family = model= 0;
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+ bogo = 0;
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+ cpus++;
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+ }
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+ }
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+ }
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+#endif /* __e2k__ */
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+
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}
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/*
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